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Merge tag 'kvm-x86-docs-6.7' of https://github.com/kvm-x86/linux into HEAD
[thirdparty/kernel/stable.git] / drivers / media / platform / intel / pxa_camera.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * V4L2 Driver for PXA camera host
4 *
5 * Copyright (C) 2006, Sascha Hauer, Pengutronix
6 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
8 */
9
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/io.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/errno.h>
18 #include <linux/fs.h>
19 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/mm.h>
22 #include <linux/moduleparam.h>
23 #include <linux/of.h>
24 #include <linux/of_graph.h>
25 #include <linux/time.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/dmaengine.h>
31 #include <linux/dma/pxa-dma.h>
32
33 #include <media/v4l2-async.h>
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-ctrls.h>
36 #include <media/v4l2-device.h>
37 #include <media/v4l2-event.h>
38 #include <media/v4l2-ioctl.h>
39 #include <media/v4l2-fwnode.h>
40
41 #include <media/videobuf2-dma-sg.h>
42
43 #include <linux/videodev2.h>
44
45 #include <linux/platform_data/media/camera-pxa.h>
46
47 #define PXA_CAM_VERSION "0.0.6"
48 #define PXA_CAM_DRV_NAME "pxa27x-camera"
49
50 #define DEFAULT_WIDTH 640
51 #define DEFAULT_HEIGHT 480
52
53 /* Camera Interface */
54 #define CICR0 0x0000
55 #define CICR1 0x0004
56 #define CICR2 0x0008
57 #define CICR3 0x000C
58 #define CICR4 0x0010
59 #define CISR 0x0014
60 #define CIFR 0x0018
61 #define CITOR 0x001C
62 #define CIBR0 0x0028
63 #define CIBR1 0x0030
64 #define CIBR2 0x0038
65
66 #define CICR0_DMAEN (1UL << 31) /* DMA request enable */
67 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
68 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
69 #define CICR0_ENB (1 << 28) /* Camera interface enable */
70 #define CICR0_DIS (1 << 27) /* Camera interface disable */
71 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
72 #define CICR0_TOM (1 << 9) /* Time-out mask */
73 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
74 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
75 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
76 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
77 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
78 #define CICR0_CDM (1 << 3) /* Disable-done mask */
79 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
80 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
81 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
82
83 #define CICR1_TBIT (1UL << 31) /* Transparency bit */
84 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
85 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
86 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
87 #define CICR1_RGB_F (1 << 11) /* RGB format */
88 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
89 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
90 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
91 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
92 #define CICR1_DW (0x7 << 0) /* Data width mask */
93
94 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
95 wait count mask */
96 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
97 wait count mask */
98 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
99 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
100 wait count mask */
101 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
102 wait count mask */
103
104 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
105 wait count mask */
106 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
107 wait count mask */
108 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
109 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
110 wait count mask */
111 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
112
113 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
114 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
115 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
116 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
117 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
118 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
119 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
120 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
121
122 #define CISR_FTO (1 << 15) /* FIFO time-out */
123 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
124 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
125 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
126 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
127 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
128 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
129 #define CISR_EOL (1 << 8) /* End of line */
130 #define CISR_PAR_ERR (1 << 7) /* Parity error */
131 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
132 #define CISR_CDD (1 << 5) /* Camera interface disable done */
133 #define CISR_SOF (1 << 4) /* Start of frame */
134 #define CISR_EOF (1 << 3) /* End of frame */
135 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
136 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
137 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
138
139 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
140 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
141 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
142 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
143 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
144 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
145 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
146 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
147
148 #define CICR0_SIM_MP (0 << 24)
149 #define CICR0_SIM_SP (1 << 24)
150 #define CICR0_SIM_MS (2 << 24)
151 #define CICR0_SIM_EP (3 << 24)
152 #define CICR0_SIM_ES (4 << 24)
153
154 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
155 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
156 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
157 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
158 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
159
160 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
161 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
162 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
163 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
164 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
165
166 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
167 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
168 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
169 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
170
171 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
172 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
173 CICR0_EOFM | CICR0_FOM)
174
175 #define sensor_call(cam, o, f, args...) \
176 v4l2_subdev_call(cam->sensor, o, f, ##args)
177
178 /*
179 * Format handling
180 */
181
182 /**
183 * enum pxa_mbus_packing - data packing types on the media-bus
184 * @PXA_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
185 * sample represents one pixel
186 * @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
187 * possibly incomplete byte high bits are padding
188 * @PXA_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
189 * to 16 bits
190 */
191 enum pxa_mbus_packing {
192 PXA_MBUS_PACKING_NONE,
193 PXA_MBUS_PACKING_2X8_PADHI,
194 PXA_MBUS_PACKING_EXTEND16,
195 };
196
197 /**
198 * enum pxa_mbus_order - sample order on the media bus
199 * @PXA_MBUS_ORDER_LE: least significant sample first
200 * @PXA_MBUS_ORDER_BE: most significant sample first
201 */
202 enum pxa_mbus_order {
203 PXA_MBUS_ORDER_LE,
204 PXA_MBUS_ORDER_BE,
205 };
206
207 /**
208 * enum pxa_mbus_layout - planes layout in memory
209 * @PXA_MBUS_LAYOUT_PACKED: color components packed
210 * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2)
211 * @PXA_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a
212 * chroma plane (C plane is half the size
213 * of Y plane)
214 * @PXA_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a
215 * chroma plane (C plane is the same size
216 * as Y plane)
217 */
218 enum pxa_mbus_layout {
219 PXA_MBUS_LAYOUT_PACKED = 0,
220 PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
221 PXA_MBUS_LAYOUT_PLANAR_2Y_C,
222 PXA_MBUS_LAYOUT_PLANAR_Y_C,
223 };
224
225 /**
226 * struct pxa_mbus_pixelfmt - Data format on the media bus
227 * @name: Name of the format
228 * @fourcc: Fourcc code, that will be obtained if the data is
229 * stored in memory in the following way:
230 * @packing: Type of sample-packing, that has to be used
231 * @order: Sample order when storing in memory
232 * @layout: Planes layout in memory
233 * @bits_per_sample: How many bits the bridge has to sample
234 */
235 struct pxa_mbus_pixelfmt {
236 const char *name;
237 u32 fourcc;
238 enum pxa_mbus_packing packing;
239 enum pxa_mbus_order order;
240 enum pxa_mbus_layout layout;
241 u8 bits_per_sample;
242 };
243
244 /**
245 * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
246 * @code: mediabus pixel-code
247 * @fmt: pixel format description
248 */
249 struct pxa_mbus_lookup {
250 u32 code;
251 struct pxa_mbus_pixelfmt fmt;
252 };
253
254 static const struct pxa_mbus_lookup mbus_fmt[] = {
255 {
256 .code = MEDIA_BUS_FMT_YUYV8_2X8,
257 .fmt = {
258 .fourcc = V4L2_PIX_FMT_YUYV,
259 .name = "YUYV",
260 .bits_per_sample = 8,
261 .packing = PXA_MBUS_PACKING_2X8_PADHI,
262 .order = PXA_MBUS_ORDER_LE,
263 .layout = PXA_MBUS_LAYOUT_PACKED,
264 },
265 }, {
266 .code = MEDIA_BUS_FMT_YVYU8_2X8,
267 .fmt = {
268 .fourcc = V4L2_PIX_FMT_YVYU,
269 .name = "YVYU",
270 .bits_per_sample = 8,
271 .packing = PXA_MBUS_PACKING_2X8_PADHI,
272 .order = PXA_MBUS_ORDER_LE,
273 .layout = PXA_MBUS_LAYOUT_PACKED,
274 },
275 }, {
276 .code = MEDIA_BUS_FMT_UYVY8_2X8,
277 .fmt = {
278 .fourcc = V4L2_PIX_FMT_UYVY,
279 .name = "UYVY",
280 .bits_per_sample = 8,
281 .packing = PXA_MBUS_PACKING_2X8_PADHI,
282 .order = PXA_MBUS_ORDER_LE,
283 .layout = PXA_MBUS_LAYOUT_PACKED,
284 },
285 }, {
286 .code = MEDIA_BUS_FMT_VYUY8_2X8,
287 .fmt = {
288 .fourcc = V4L2_PIX_FMT_VYUY,
289 .name = "VYUY",
290 .bits_per_sample = 8,
291 .packing = PXA_MBUS_PACKING_2X8_PADHI,
292 .order = PXA_MBUS_ORDER_LE,
293 .layout = PXA_MBUS_LAYOUT_PACKED,
294 },
295 }, {
296 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
297 .fmt = {
298 .fourcc = V4L2_PIX_FMT_RGB555,
299 .name = "RGB555",
300 .bits_per_sample = 8,
301 .packing = PXA_MBUS_PACKING_2X8_PADHI,
302 .order = PXA_MBUS_ORDER_LE,
303 .layout = PXA_MBUS_LAYOUT_PACKED,
304 },
305 }, {
306 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
307 .fmt = {
308 .fourcc = V4L2_PIX_FMT_RGB555X,
309 .name = "RGB555X",
310 .bits_per_sample = 8,
311 .packing = PXA_MBUS_PACKING_2X8_PADHI,
312 .order = PXA_MBUS_ORDER_BE,
313 .layout = PXA_MBUS_LAYOUT_PACKED,
314 },
315 }, {
316 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
317 .fmt = {
318 .fourcc = V4L2_PIX_FMT_RGB565,
319 .name = "RGB565",
320 .bits_per_sample = 8,
321 .packing = PXA_MBUS_PACKING_2X8_PADHI,
322 .order = PXA_MBUS_ORDER_LE,
323 .layout = PXA_MBUS_LAYOUT_PACKED,
324 },
325 }, {
326 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
327 .fmt = {
328 .fourcc = V4L2_PIX_FMT_RGB565X,
329 .name = "RGB565X",
330 .bits_per_sample = 8,
331 .packing = PXA_MBUS_PACKING_2X8_PADHI,
332 .order = PXA_MBUS_ORDER_BE,
333 .layout = PXA_MBUS_LAYOUT_PACKED,
334 },
335 }, {
336 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
337 .fmt = {
338 .fourcc = V4L2_PIX_FMT_SBGGR8,
339 .name = "Bayer 8 BGGR",
340 .bits_per_sample = 8,
341 .packing = PXA_MBUS_PACKING_NONE,
342 .order = PXA_MBUS_ORDER_LE,
343 .layout = PXA_MBUS_LAYOUT_PACKED,
344 },
345 }, {
346 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
347 .fmt = {
348 .fourcc = V4L2_PIX_FMT_SGBRG8,
349 .name = "Bayer 8 GBRG",
350 .bits_per_sample = 8,
351 .packing = PXA_MBUS_PACKING_NONE,
352 .order = PXA_MBUS_ORDER_LE,
353 .layout = PXA_MBUS_LAYOUT_PACKED,
354 },
355 }, {
356 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
357 .fmt = {
358 .fourcc = V4L2_PIX_FMT_SGRBG8,
359 .name = "Bayer 8 GRBG",
360 .bits_per_sample = 8,
361 .packing = PXA_MBUS_PACKING_NONE,
362 .order = PXA_MBUS_ORDER_LE,
363 .layout = PXA_MBUS_LAYOUT_PACKED,
364 },
365 }, {
366 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
367 .fmt = {
368 .fourcc = V4L2_PIX_FMT_SRGGB8,
369 .name = "Bayer 8 RGGB",
370 .bits_per_sample = 8,
371 .packing = PXA_MBUS_PACKING_NONE,
372 .order = PXA_MBUS_ORDER_LE,
373 .layout = PXA_MBUS_LAYOUT_PACKED,
374 },
375 }, {
376 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
377 .fmt = {
378 .fourcc = V4L2_PIX_FMT_SBGGR10,
379 .name = "Bayer 10 BGGR",
380 .bits_per_sample = 10,
381 .packing = PXA_MBUS_PACKING_EXTEND16,
382 .order = PXA_MBUS_ORDER_LE,
383 .layout = PXA_MBUS_LAYOUT_PACKED,
384 },
385 }, {
386 .code = MEDIA_BUS_FMT_Y8_1X8,
387 .fmt = {
388 .fourcc = V4L2_PIX_FMT_GREY,
389 .name = "Grey",
390 .bits_per_sample = 8,
391 .packing = PXA_MBUS_PACKING_NONE,
392 .order = PXA_MBUS_ORDER_LE,
393 .layout = PXA_MBUS_LAYOUT_PACKED,
394 },
395 }, {
396 .code = MEDIA_BUS_FMT_Y10_1X10,
397 .fmt = {
398 .fourcc = V4L2_PIX_FMT_Y10,
399 .name = "Grey 10bit",
400 .bits_per_sample = 10,
401 .packing = PXA_MBUS_PACKING_EXTEND16,
402 .order = PXA_MBUS_ORDER_LE,
403 .layout = PXA_MBUS_LAYOUT_PACKED,
404 },
405 }, {
406 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
407 .fmt = {
408 .fourcc = V4L2_PIX_FMT_SBGGR10,
409 .name = "Bayer 10 BGGR",
410 .bits_per_sample = 8,
411 .packing = PXA_MBUS_PACKING_2X8_PADHI,
412 .order = PXA_MBUS_ORDER_LE,
413 .layout = PXA_MBUS_LAYOUT_PACKED,
414 },
415 }, {
416 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
417 .fmt = {
418 .fourcc = V4L2_PIX_FMT_SBGGR10,
419 .name = "Bayer 10 BGGR",
420 .bits_per_sample = 8,
421 .packing = PXA_MBUS_PACKING_2X8_PADHI,
422 .order = PXA_MBUS_ORDER_BE,
423 .layout = PXA_MBUS_LAYOUT_PACKED,
424 },
425 }, {
426 .code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
427 .fmt = {
428 .fourcc = V4L2_PIX_FMT_RGB444,
429 .name = "RGB444",
430 .bits_per_sample = 8,
431 .packing = PXA_MBUS_PACKING_2X8_PADHI,
432 .order = PXA_MBUS_ORDER_BE,
433 .layout = PXA_MBUS_LAYOUT_PACKED,
434 },
435 }, {
436 .code = MEDIA_BUS_FMT_UYVY8_1X16,
437 .fmt = {
438 .fourcc = V4L2_PIX_FMT_UYVY,
439 .name = "UYVY 16bit",
440 .bits_per_sample = 16,
441 .packing = PXA_MBUS_PACKING_EXTEND16,
442 .order = PXA_MBUS_ORDER_LE,
443 .layout = PXA_MBUS_LAYOUT_PACKED,
444 },
445 }, {
446 .code = MEDIA_BUS_FMT_VYUY8_1X16,
447 .fmt = {
448 .fourcc = V4L2_PIX_FMT_VYUY,
449 .name = "VYUY 16bit",
450 .bits_per_sample = 16,
451 .packing = PXA_MBUS_PACKING_EXTEND16,
452 .order = PXA_MBUS_ORDER_LE,
453 .layout = PXA_MBUS_LAYOUT_PACKED,
454 },
455 }, {
456 .code = MEDIA_BUS_FMT_YUYV8_1X16,
457 .fmt = {
458 .fourcc = V4L2_PIX_FMT_YUYV,
459 .name = "YUYV 16bit",
460 .bits_per_sample = 16,
461 .packing = PXA_MBUS_PACKING_EXTEND16,
462 .order = PXA_MBUS_ORDER_LE,
463 .layout = PXA_MBUS_LAYOUT_PACKED,
464 },
465 }, {
466 .code = MEDIA_BUS_FMT_YVYU8_1X16,
467 .fmt = {
468 .fourcc = V4L2_PIX_FMT_YVYU,
469 .name = "YVYU 16bit",
470 .bits_per_sample = 16,
471 .packing = PXA_MBUS_PACKING_EXTEND16,
472 .order = PXA_MBUS_ORDER_LE,
473 .layout = PXA_MBUS_LAYOUT_PACKED,
474 },
475 }, {
476 .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
477 .fmt = {
478 .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8,
479 .name = "Bayer 10 BGGR DPCM 8",
480 .bits_per_sample = 8,
481 .packing = PXA_MBUS_PACKING_NONE,
482 .order = PXA_MBUS_ORDER_LE,
483 .layout = PXA_MBUS_LAYOUT_PACKED,
484 },
485 }, {
486 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
487 .fmt = {
488 .fourcc = V4L2_PIX_FMT_SGBRG10,
489 .name = "Bayer 10 GBRG",
490 .bits_per_sample = 10,
491 .packing = PXA_MBUS_PACKING_EXTEND16,
492 .order = PXA_MBUS_ORDER_LE,
493 .layout = PXA_MBUS_LAYOUT_PACKED,
494 },
495 }, {
496 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
497 .fmt = {
498 .fourcc = V4L2_PIX_FMT_SGRBG10,
499 .name = "Bayer 10 GRBG",
500 .bits_per_sample = 10,
501 .packing = PXA_MBUS_PACKING_EXTEND16,
502 .order = PXA_MBUS_ORDER_LE,
503 .layout = PXA_MBUS_LAYOUT_PACKED,
504 },
505 }, {
506 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
507 .fmt = {
508 .fourcc = V4L2_PIX_FMT_SRGGB10,
509 .name = "Bayer 10 RGGB",
510 .bits_per_sample = 10,
511 .packing = PXA_MBUS_PACKING_EXTEND16,
512 .order = PXA_MBUS_ORDER_LE,
513 .layout = PXA_MBUS_LAYOUT_PACKED,
514 },
515 }, {
516 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
517 .fmt = {
518 .fourcc = V4L2_PIX_FMT_SBGGR12,
519 .name = "Bayer 12 BGGR",
520 .bits_per_sample = 12,
521 .packing = PXA_MBUS_PACKING_EXTEND16,
522 .order = PXA_MBUS_ORDER_LE,
523 .layout = PXA_MBUS_LAYOUT_PACKED,
524 },
525 }, {
526 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
527 .fmt = {
528 .fourcc = V4L2_PIX_FMT_SGBRG12,
529 .name = "Bayer 12 GBRG",
530 .bits_per_sample = 12,
531 .packing = PXA_MBUS_PACKING_EXTEND16,
532 .order = PXA_MBUS_ORDER_LE,
533 .layout = PXA_MBUS_LAYOUT_PACKED,
534 },
535 }, {
536 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
537 .fmt = {
538 .fourcc = V4L2_PIX_FMT_SGRBG12,
539 .name = "Bayer 12 GRBG",
540 .bits_per_sample = 12,
541 .packing = PXA_MBUS_PACKING_EXTEND16,
542 .order = PXA_MBUS_ORDER_LE,
543 .layout = PXA_MBUS_LAYOUT_PACKED,
544 },
545 }, {
546 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
547 .fmt = {
548 .fourcc = V4L2_PIX_FMT_SRGGB12,
549 .name = "Bayer 12 RGGB",
550 .bits_per_sample = 12,
551 .packing = PXA_MBUS_PACKING_EXTEND16,
552 .order = PXA_MBUS_ORDER_LE,
553 .layout = PXA_MBUS_LAYOUT_PACKED,
554 },
555 },
556 };
557
558 static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
559 {
560 if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
561 return width * mf->bits_per_sample / 8;
562
563 switch (mf->packing) {
564 case PXA_MBUS_PACKING_NONE:
565 return width * mf->bits_per_sample / 8;
566 case PXA_MBUS_PACKING_2X8_PADHI:
567 case PXA_MBUS_PACKING_EXTEND16:
568 return width * 2;
569 }
570 return -EINVAL;
571 }
572
573 static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
574 u32 bytes_per_line, u32 height)
575 {
576 if (mf->layout == PXA_MBUS_LAYOUT_PACKED)
577 return bytes_per_line * height;
578
579 switch (mf->packing) {
580 case PXA_MBUS_PACKING_2X8_PADHI:
581 return bytes_per_line * height * 2;
582 default:
583 return -EINVAL;
584 }
585 }
586
587 static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
588 u32 code,
589 const struct pxa_mbus_lookup *lookup,
590 int n)
591 {
592 int i;
593
594 for (i = 0; i < n; i++)
595 if (lookup[i].code == code)
596 return &lookup[i].fmt;
597
598 return NULL;
599 }
600
601 static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
602 u32 code)
603 {
604 return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
605 }
606
607 /**
608 * struct pxa_camera_format_xlate - match between host and sensor formats
609 * @code: code of a sensor provided format
610 * @host_fmt: host format after host translation from code
611 *
612 * Host and sensor translation structure. Used in table of host and sensor
613 * formats matchings in pxa_camera_device. A host can override the generic list
614 * generation by implementing get_formats(), and use it for format checks and
615 * format setup.
616 */
617 struct pxa_camera_format_xlate {
618 u32 code;
619 const struct pxa_mbus_pixelfmt *host_fmt;
620 };
621
622 /*
623 * Structures
624 */
625 enum pxa_camera_active_dma {
626 DMA_Y = 0x1,
627 DMA_U = 0x2,
628 DMA_V = 0x4,
629 };
630
631 /* buffer for one video frame */
632 struct pxa_buffer {
633 /* common v4l buffer stuff -- must be first */
634 struct vb2_v4l2_buffer vbuf;
635 struct list_head queue;
636 u32 code;
637 int nb_planes;
638 /* our descriptor lists for Y, U and V channels */
639 struct dma_async_tx_descriptor *descs[3];
640 dma_cookie_t cookie[3];
641 struct scatterlist *sg[3];
642 int sg_len[3];
643 size_t plane_sizes[3];
644 int inwork;
645 enum pxa_camera_active_dma active_dma;
646 };
647
648 struct pxa_camera_dev {
649 struct v4l2_device v4l2_dev;
650 struct video_device vdev;
651 struct v4l2_async_notifier notifier;
652 struct vb2_queue vb2_vq;
653 struct v4l2_subdev *sensor;
654 struct pxa_camera_format_xlate *user_formats;
655 const struct pxa_camera_format_xlate *current_fmt;
656 struct v4l2_pix_format current_pix;
657
658 /*
659 * PXA27x is only supposed to handle one camera on its Quick Capture
660 * interface. If anyone ever builds hardware to enable more than
661 * one camera, they will have to modify this driver too
662 */
663 struct clk *clk;
664
665 unsigned int irq;
666 void __iomem *base;
667
668 int channels;
669 struct dma_chan *dma_chans[3];
670
671 struct pxacamera_platform_data *pdata;
672 struct resource *res;
673 unsigned long platform_flags;
674 unsigned long ciclk;
675 unsigned long mclk;
676 u32 mclk_divisor;
677 u16 width_flags; /* max 10 bits */
678
679 struct list_head capture;
680
681 spinlock_t lock;
682 struct mutex mlock;
683 unsigned int buf_sequence;
684
685 struct pxa_buffer *active;
686 struct tasklet_struct task_eof;
687
688 u32 save_cicr[5];
689 };
690
691 struct pxa_cam {
692 unsigned long flags;
693 };
694
695 static const char *pxa_cam_driver_description = "PXA_Camera";
696
697 /*
698 * Format translation functions
699 */
700 static const struct pxa_camera_format_xlate
701 *pxa_mbus_xlate_by_fourcc(struct pxa_camera_format_xlate *user_formats,
702 unsigned int fourcc)
703 {
704 unsigned int i;
705
706 for (i = 0; user_formats[i].code; i++)
707 if (user_formats[i].host_fmt->fourcc == fourcc)
708 return user_formats + i;
709 return NULL;
710 }
711
712 static struct pxa_camera_format_xlate *pxa_mbus_build_fmts_xlate(
713 struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
714 int (*get_formats)(struct v4l2_device *, unsigned int,
715 struct pxa_camera_format_xlate *xlate))
716 {
717 unsigned int i, fmts = 0, raw_fmts = 0;
718 int ret;
719 struct v4l2_subdev_mbus_code_enum code = {
720 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
721 };
722 struct pxa_camera_format_xlate *user_formats;
723
724 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
725 raw_fmts++;
726 code.index++;
727 }
728
729 /*
730 * First pass - only count formats this host-sensor
731 * configuration can provide
732 */
733 for (i = 0; i < raw_fmts; i++) {
734 ret = get_formats(v4l2_dev, i, NULL);
735 if (ret < 0)
736 return ERR_PTR(ret);
737 fmts += ret;
738 }
739
740 if (!fmts)
741 return ERR_PTR(-ENXIO);
742
743 user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
744 if (!user_formats)
745 return ERR_PTR(-ENOMEM);
746
747 /* Second pass - actually fill data formats */
748 fmts = 0;
749 for (i = 0; i < raw_fmts; i++) {
750 ret = get_formats(v4l2_dev, i, user_formats + fmts);
751 if (ret < 0)
752 goto egfmt;
753 fmts += ret;
754 }
755 user_formats[fmts].code = 0;
756
757 return user_formats;
758 egfmt:
759 kfree(user_formats);
760 return ERR_PTR(ret);
761 }
762
763 /*
764 * Videobuf operations
765 */
766 static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
767 {
768 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
769
770 return container_of(vbuf, struct pxa_buffer, vbuf);
771 }
772
773 static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
774 {
775 return pcdev->v4l2_dev.dev;
776 }
777
778 static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
779 {
780 return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
781 }
782
783 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
784 enum pxa_camera_active_dma act_dma);
785
786 static void pxa_camera_dma_irq_y(void *data)
787 {
788 struct pxa_camera_dev *pcdev = data;
789
790 pxa_camera_dma_irq(pcdev, DMA_Y);
791 }
792
793 static void pxa_camera_dma_irq_u(void *data)
794 {
795 struct pxa_camera_dev *pcdev = data;
796
797 pxa_camera_dma_irq(pcdev, DMA_U);
798 }
799
800 static void pxa_camera_dma_irq_v(void *data)
801 {
802 struct pxa_camera_dev *pcdev = data;
803
804 pxa_camera_dma_irq(pcdev, DMA_V);
805 }
806
807 /**
808 * pxa_init_dma_channel - init dma descriptors
809 * @pcdev: pxa camera device
810 * @buf: pxa camera buffer
811 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
812 * @sg: dma scatter list
813 * @sglen: dma scatter list length
814 *
815 * Prepares the pxa dma descriptors to transfer one camera channel.
816 *
817 * Returns 0 if success or -ENOMEM if no memory is available
818 */
819 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
820 struct pxa_buffer *buf, int channel,
821 struct scatterlist *sg, int sglen)
822 {
823 struct dma_chan *dma_chan = pcdev->dma_chans[channel];
824 struct dma_async_tx_descriptor *tx;
825
826 tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
827 DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
828 if (!tx) {
829 dev_err(pcdev_to_dev(pcdev),
830 "dmaengine_prep_slave_sg failed\n");
831 goto fail;
832 }
833
834 tx->callback_param = pcdev;
835 switch (channel) {
836 case 0:
837 tx->callback = pxa_camera_dma_irq_y;
838 break;
839 case 1:
840 tx->callback = pxa_camera_dma_irq_u;
841 break;
842 case 2:
843 tx->callback = pxa_camera_dma_irq_v;
844 break;
845 }
846
847 buf->descs[channel] = tx;
848 return 0;
849 fail:
850 dev_dbg(pcdev_to_dev(pcdev),
851 "%s (vb=%p) dma_tx=%p\n",
852 __func__, buf, tx);
853
854 return -ENOMEM;
855 }
856
857 static void pxa_video_buf_set_actdma(struct pxa_camera_dev *pcdev,
858 struct pxa_buffer *buf)
859 {
860 buf->active_dma = DMA_Y;
861 if (buf->nb_planes == 3)
862 buf->active_dma |= DMA_U | DMA_V;
863 }
864
865 /**
866 * pxa_dma_start_channels - start DMA channel for active buffer
867 * @pcdev: pxa camera device
868 *
869 * Initialize DMA channels to the beginning of the active video buffer, and
870 * start these channels.
871 */
872 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
873 {
874 int i;
875
876 for (i = 0; i < pcdev->channels; i++) {
877 dev_dbg(pcdev_to_dev(pcdev),
878 "%s (channel=%d)\n", __func__, i);
879 dma_async_issue_pending(pcdev->dma_chans[i]);
880 }
881 }
882
883 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
884 {
885 int i;
886
887 for (i = 0; i < pcdev->channels; i++) {
888 dev_dbg(pcdev_to_dev(pcdev),
889 "%s (channel=%d)\n", __func__, i);
890 dmaengine_terminate_all(pcdev->dma_chans[i]);
891 }
892 }
893
894 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
895 struct pxa_buffer *buf)
896 {
897 int i;
898
899 for (i = 0; i < pcdev->channels; i++) {
900 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
901 dev_dbg(pcdev_to_dev(pcdev),
902 "%s (channel=%d) : submit vb=%p cookie=%d\n",
903 __func__, i, buf, buf->descs[i]->cookie);
904 }
905 }
906
907 /**
908 * pxa_camera_start_capture - start video capturing
909 * @pcdev: camera device
910 *
911 * Launch capturing. DMA channels should not be active yet. They should get
912 * activated at the end of frame interrupt, to capture only whole frames, and
913 * never begin the capture of a partial frame.
914 */
915 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
916 {
917 unsigned long cicr0;
918
919 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
920 __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
921 /* Enable End-Of-Frame Interrupt */
922 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
923 cicr0 &= ~CICR0_EOFM;
924 __raw_writel(cicr0, pcdev->base + CICR0);
925 }
926
927 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
928 {
929 unsigned long cicr0;
930
931 pxa_dma_stop_channels(pcdev);
932
933 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
934 __raw_writel(cicr0, pcdev->base + CICR0);
935
936 pcdev->active = NULL;
937 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
938 }
939
940 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
941 struct pxa_buffer *buf,
942 enum vb2_buffer_state state)
943 {
944 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
945 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
946
947 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
948 list_del_init(&buf->queue);
949 vb->timestamp = ktime_get_ns();
950 vbuf->sequence = pcdev->buf_sequence++;
951 vbuf->field = V4L2_FIELD_NONE;
952 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
953 dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
954 __func__, buf);
955
956 if (list_empty(&pcdev->capture)) {
957 pxa_camera_stop_capture(pcdev);
958 return;
959 }
960
961 pcdev->active = list_entry(pcdev->capture.next,
962 struct pxa_buffer, queue);
963 }
964
965 /**
966 * pxa_camera_check_link_miss - check missed DMA linking
967 * @pcdev: camera device
968 * @last_submitted: an opaque DMA cookie for last submitted
969 * @last_issued: an opaque DMA cookie for last issued
970 *
971 * The DMA chaining is done with DMA running. This means a tiny temporal window
972 * remains, where a buffer is queued on the chain, while the chain is already
973 * stopped. This means the tailed buffer would never be transferred by DMA.
974 * This function restarts the capture for this corner case, where :
975 * - DADR() == DADDR_STOP
976 * - a video buffer is queued on the pcdev->capture list
977 *
978 * Please check the "DMA hot chaining timeslice issue" in
979 * Documentation/driver-api/media/drivers/pxa_camera.rst
980 *
981 * Context: should only be called within the dma irq handler
982 */
983 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
984 dma_cookie_t last_submitted,
985 dma_cookie_t last_issued)
986 {
987 bool is_dma_stopped = last_submitted != last_issued;
988
989 dev_dbg(pcdev_to_dev(pcdev),
990 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
991 __func__, pcdev->active, is_dma_stopped);
992
993 if (pcdev->active && is_dma_stopped)
994 pxa_camera_start_capture(pcdev);
995 }
996
997 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
998 enum pxa_camera_active_dma act_dma)
999 {
1000 struct pxa_buffer *buf, *last_buf;
1001 unsigned long flags;
1002 u32 camera_status, overrun;
1003 int chan;
1004 enum dma_status last_status;
1005 dma_cookie_t last_issued;
1006
1007 spin_lock_irqsave(&pcdev->lock, flags);
1008
1009 camera_status = __raw_readl(pcdev->base + CISR);
1010 dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1011 camera_status, act_dma);
1012 overrun = CISR_IFO_0;
1013 if (pcdev->channels == 3)
1014 overrun |= CISR_IFO_1 | CISR_IFO_2;
1015
1016 /*
1017 * pcdev->active should not be NULL in DMA irq handler.
1018 *
1019 * But there is one corner case : if capture was stopped due to an
1020 * overrun of channel 1, and at that same channel 2 was completed.
1021 *
1022 * When handling the overrun in DMA irq for channel 1, we'll stop the
1023 * capture and restart it (and thus set pcdev->active to NULL). But the
1024 * DMA irq handler will already be pending for channel 2. So on entering
1025 * the DMA irq handler for channel 2 there will be no active buffer, yet
1026 * that is normal.
1027 */
1028 if (!pcdev->active)
1029 goto out;
1030
1031 buf = pcdev->active;
1032 WARN_ON(buf->inwork || list_empty(&buf->queue));
1033
1034 /*
1035 * It's normal if the last frame creates an overrun, as there
1036 * are no more DMA descriptors to fetch from QCI fifos
1037 */
1038 switch (act_dma) {
1039 case DMA_U:
1040 chan = 1;
1041 break;
1042 case DMA_V:
1043 chan = 2;
1044 break;
1045 default:
1046 chan = 0;
1047 break;
1048 }
1049 last_buf = list_entry(pcdev->capture.prev,
1050 struct pxa_buffer, queue);
1051 last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
1052 last_buf->cookie[chan],
1053 NULL, &last_issued);
1054 if (camera_status & overrun &&
1055 last_status != DMA_COMPLETE) {
1056 dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1057 camera_status);
1058 pxa_camera_stop_capture(pcdev);
1059 list_for_each_entry(buf, &pcdev->capture, queue)
1060 pxa_dma_add_tail_buf(pcdev, buf);
1061 pxa_camera_start_capture(pcdev);
1062 goto out;
1063 }
1064 buf->active_dma &= ~act_dma;
1065 if (!buf->active_dma) {
1066 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1067 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
1068 last_issued);
1069 }
1070
1071 out:
1072 spin_unlock_irqrestore(&pcdev->lock, flags);
1073 }
1074
1075 static u32 mclk_get_divisor(struct platform_device *pdev,
1076 struct pxa_camera_dev *pcdev)
1077 {
1078 unsigned long mclk = pcdev->mclk;
1079 u32 div;
1080 unsigned long lcdclk;
1081
1082 lcdclk = clk_get_rate(pcdev->clk);
1083 pcdev->ciclk = lcdclk;
1084
1085 /* mclk <= ciclk / 4 (27.4.2) */
1086 if (mclk > lcdclk / 4) {
1087 mclk = lcdclk / 4;
1088 dev_warn(&pdev->dev,
1089 "Limiting master clock to %lu\n", mclk);
1090 }
1091
1092 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
1093 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1094
1095 /* If we're not supplying MCLK, leave it at 0 */
1096 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1097 pcdev->mclk = lcdclk / (2 * (div + 1));
1098
1099 dev_dbg(&pdev->dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
1100 lcdclk, mclk, div);
1101
1102 return div;
1103 }
1104
1105 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
1106 unsigned long pclk)
1107 {
1108 /* We want a timeout > 1 pixel time, not ">=" */
1109 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
1110
1111 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
1112 }
1113
1114 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1115 {
1116 u32 cicr4 = 0;
1117
1118 /* disable all interrupts */
1119 __raw_writel(0x3ff, pcdev->base + CICR0);
1120
1121 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1122 cicr4 |= CICR4_PCLK_EN;
1123 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1124 cicr4 |= CICR4_MCLK_EN;
1125 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1126 cicr4 |= CICR4_PCP;
1127 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1128 cicr4 |= CICR4_HSP;
1129 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1130 cicr4 |= CICR4_VSP;
1131
1132 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
1133
1134 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1135 /* Initialise the timeout under the assumption pclk = mclk */
1136 recalculate_fifo_timeout(pcdev, pcdev->mclk);
1137 else
1138 /* "Safe default" - 13MHz */
1139 recalculate_fifo_timeout(pcdev, 13000000);
1140
1141 clk_prepare_enable(pcdev->clk);
1142 }
1143
1144 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1145 {
1146 clk_disable_unprepare(pcdev->clk);
1147 }
1148
1149 static void pxa_camera_eof(struct tasklet_struct *t)
1150 {
1151 struct pxa_camera_dev *pcdev = from_tasklet(pcdev, t, task_eof);
1152 unsigned long cifr;
1153 struct pxa_buffer *buf;
1154
1155 dev_dbg(pcdev_to_dev(pcdev),
1156 "Camera interrupt status 0x%x\n",
1157 __raw_readl(pcdev->base + CISR));
1158
1159 /* Reset the FIFOs */
1160 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1161 __raw_writel(cifr, pcdev->base + CIFR);
1162
1163 pcdev->active = list_first_entry(&pcdev->capture,
1164 struct pxa_buffer, queue);
1165 buf = pcdev->active;
1166 pxa_video_buf_set_actdma(pcdev, buf);
1167
1168 pxa_dma_start_channels(pcdev);
1169 }
1170
1171 static irqreturn_t pxa_camera_irq(int irq, void *data)
1172 {
1173 struct pxa_camera_dev *pcdev = data;
1174 unsigned long status, cicr0;
1175
1176 status = __raw_readl(pcdev->base + CISR);
1177 dev_dbg(pcdev_to_dev(pcdev),
1178 "Camera interrupt status 0x%lx\n", status);
1179
1180 if (!status)
1181 return IRQ_NONE;
1182
1183 __raw_writel(status, pcdev->base + CISR);
1184
1185 if (status & CISR_EOF) {
1186 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
1187 __raw_writel(cicr0, pcdev->base + CICR0);
1188 tasklet_schedule(&pcdev->task_eof);
1189 }
1190
1191 return IRQ_HANDLED;
1192 }
1193
1194 static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1195 unsigned long flags, __u32 pixfmt)
1196 {
1197 unsigned long dw, bpp;
1198 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1199 int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1200
1201 if (ret < 0)
1202 y_skip_top = 0;
1203
1204 /*
1205 * Datawidth is now guaranteed to be equal to one of the three values.
1206 * We fix bit-per-pixel equal to data-width...
1207 */
1208 switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1209 case 10:
1210 dw = 4;
1211 bpp = 0x40;
1212 break;
1213 case 9:
1214 dw = 3;
1215 bpp = 0x20;
1216 break;
1217 default:
1218 /*
1219 * Actually it can only be 8 now,
1220 * default is just to silence compiler warnings
1221 */
1222 case 8:
1223 dw = 2;
1224 bpp = 0;
1225 }
1226
1227 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1228 cicr4 |= CICR4_PCLK_EN;
1229 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1230 cicr4 |= CICR4_MCLK_EN;
1231 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1232 cicr4 |= CICR4_PCP;
1233 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1234 cicr4 |= CICR4_HSP;
1235 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1236 cicr4 |= CICR4_VSP;
1237
1238 cicr0 = __raw_readl(pcdev->base + CICR0);
1239 if (cicr0 & CICR0_ENB)
1240 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1241
1242 cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1243
1244 switch (pixfmt) {
1245 case V4L2_PIX_FMT_YUV422P:
1246 pcdev->channels = 3;
1247 cicr1 |= CICR1_YCBCR_F;
1248 /*
1249 * Normally, pxa bus wants as input UYVY format. We allow all
1250 * reorderings of the YUV422 format, as no processing is done,
1251 * and the YUV stream is just passed through without any
1252 * transformation. Note that UYVY is the only format that
1253 * should be used if pxa framebuffer Overlay2 is used.
1254 */
1255 fallthrough;
1256 case V4L2_PIX_FMT_UYVY:
1257 case V4L2_PIX_FMT_VYUY:
1258 case V4L2_PIX_FMT_YUYV:
1259 case V4L2_PIX_FMT_YVYU:
1260 cicr1 |= CICR1_COLOR_SP_VAL(2);
1261 break;
1262 case V4L2_PIX_FMT_RGB555:
1263 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1264 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1265 break;
1266 case V4L2_PIX_FMT_RGB565:
1267 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1268 break;
1269 }
1270
1271 cicr2 = 0;
1272 cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1273 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1274 cicr4 |= pcdev->mclk_divisor;
1275
1276 __raw_writel(cicr1, pcdev->base + CICR1);
1277 __raw_writel(cicr2, pcdev->base + CICR2);
1278 __raw_writel(cicr3, pcdev->base + CICR3);
1279 __raw_writel(cicr4, pcdev->base + CICR4);
1280
1281 /* CIF interrupts are not used, only DMA */
1282 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1283 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1284 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1285 __raw_writel(cicr0, pcdev->base + CICR0);
1286 }
1287
1288 /*
1289 * Videobuf2 section
1290 */
1291 static void pxa_buffer_cleanup(struct pxa_buffer *buf)
1292 {
1293 int i;
1294
1295 for (i = 0; i < 3 && buf->descs[i]; i++) {
1296 dmaengine_desc_free(buf->descs[i]);
1297 kfree(buf->sg[i]);
1298 buf->descs[i] = NULL;
1299 buf->sg[i] = NULL;
1300 buf->sg_len[i] = 0;
1301 buf->plane_sizes[i] = 0;
1302 }
1303 buf->nb_planes = 0;
1304 }
1305
1306 static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
1307 struct pxa_buffer *buf)
1308 {
1309 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
1310 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1311 int nb_channels = pcdev->channels;
1312 int i, ret = 0;
1313 unsigned long size = vb2_plane_size(vb, 0);
1314
1315 switch (nb_channels) {
1316 case 1:
1317 buf->plane_sizes[0] = size;
1318 break;
1319 case 3:
1320 buf->plane_sizes[0] = size / 2;
1321 buf->plane_sizes[1] = size / 4;
1322 buf->plane_sizes[2] = size / 4;
1323 break;
1324 default:
1325 return -EINVAL;
1326 }
1327 buf->nb_planes = nb_channels;
1328
1329 ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
1330 buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
1331 if (ret < 0) {
1332 dev_err(pcdev_to_dev(pcdev),
1333 "sg_split failed: %d\n", ret);
1334 return ret;
1335 }
1336 for (i = 0; i < nb_channels; i++) {
1337 ret = pxa_init_dma_channel(pcdev, buf, i,
1338 buf->sg[i], buf->sg_len[i]);
1339 if (ret) {
1340 pxa_buffer_cleanup(buf);
1341 return ret;
1342 }
1343 }
1344 INIT_LIST_HEAD(&buf->queue);
1345
1346 return ret;
1347 }
1348
1349 static void pxac_vb2_cleanup(struct vb2_buffer *vb)
1350 {
1351 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1352 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1353
1354 dev_dbg(pcdev_to_dev(pcdev),
1355 "%s(vb=%p)\n", __func__, vb);
1356 pxa_buffer_cleanup(buf);
1357 }
1358
1359 static void pxac_vb2_queue(struct vb2_buffer *vb)
1360 {
1361 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1362 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1363
1364 dev_dbg(pcdev_to_dev(pcdev),
1365 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
1366 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
1367 pcdev->active);
1368
1369 list_add_tail(&buf->queue, &pcdev->capture);
1370
1371 pxa_dma_add_tail_buf(pcdev, buf);
1372 }
1373
1374 /*
1375 * Please check the DMA prepared buffer structure in :
1376 * Documentation/driver-api/media/drivers/pxa_camera.rst
1377 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
1378 * modification while DMA chain is running will work anyway.
1379 */
1380 static int pxac_vb2_prepare(struct vb2_buffer *vb)
1381 {
1382 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1383 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1384 int ret = 0;
1385 #ifdef DEBUG
1386 int i;
1387 #endif
1388
1389 switch (pcdev->channels) {
1390 case 1:
1391 case 3:
1392 vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1393 break;
1394 default:
1395 return -EINVAL;
1396 }
1397
1398 dev_dbg(pcdev_to_dev(pcdev),
1399 "%s (vb=%p) nb_channels=%d size=%lu\n",
1400 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
1401
1402 WARN_ON(!pcdev->current_fmt);
1403
1404 #ifdef DEBUG
1405 /*
1406 * This can be useful if you want to see if we actually fill
1407 * the buffer with something
1408 */
1409 for (i = 0; i < vb->num_planes; i++)
1410 memset((void *)vb2_plane_vaddr(vb, i),
1411 0xaa, vb2_get_plane_payload(vb, i));
1412 #endif
1413
1414 /*
1415 * I think, in buf_prepare you only have to protect global data,
1416 * the actual buffer is yours
1417 */
1418 buf->inwork = 0;
1419 pxa_video_buf_set_actdma(pcdev, buf);
1420
1421 return ret;
1422 }
1423
1424 static int pxac_vb2_init(struct vb2_buffer *vb)
1425 {
1426 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1427 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1428
1429 dev_dbg(pcdev_to_dev(pcdev),
1430 "%s(nb_channels=%d)\n",
1431 __func__, pcdev->channels);
1432
1433 return pxa_buffer_init(pcdev, buf);
1434 }
1435
1436 static int pxac_vb2_queue_setup(struct vb2_queue *vq,
1437 unsigned int *nbufs,
1438 unsigned int *num_planes, unsigned int sizes[],
1439 struct device *alloc_devs[])
1440 {
1441 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1442 int size = pcdev->current_pix.sizeimage;
1443
1444 dev_dbg(pcdev_to_dev(pcdev),
1445 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
1446 __func__, vq, *nbufs, *num_planes, size);
1447 /*
1448 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1449 * format, even if there are 3 planes Y, U and V, we reply there is only
1450 * one plane, containing Y, U and V data, one after the other.
1451 */
1452 if (*num_planes)
1453 return sizes[0] < size ? -EINVAL : 0;
1454
1455 *num_planes = 1;
1456 switch (pcdev->channels) {
1457 case 1:
1458 case 3:
1459 sizes[0] = size;
1460 break;
1461 default:
1462 return -EINVAL;
1463 }
1464
1465 if (!*nbufs)
1466 *nbufs = 1;
1467
1468 return 0;
1469 }
1470
1471 static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1472 {
1473 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1474
1475 dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1476 __func__, count, pcdev->active);
1477
1478 pcdev->buf_sequence = 0;
1479 if (!pcdev->active)
1480 pxa_camera_start_capture(pcdev);
1481
1482 return 0;
1483 }
1484
1485 static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1486 {
1487 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1488 struct pxa_buffer *buf, *tmp;
1489
1490 dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
1491 __func__, pcdev->active);
1492 pxa_camera_stop_capture(pcdev);
1493
1494 list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
1495 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1496 }
1497
1498 static const struct vb2_ops pxac_vb2_ops = {
1499 .queue_setup = pxac_vb2_queue_setup,
1500 .buf_init = pxac_vb2_init,
1501 .buf_prepare = pxac_vb2_prepare,
1502 .buf_queue = pxac_vb2_queue,
1503 .buf_cleanup = pxac_vb2_cleanup,
1504 .start_streaming = pxac_vb2_start_streaming,
1505 .stop_streaming = pxac_vb2_stop_streaming,
1506 .wait_prepare = vb2_ops_wait_prepare,
1507 .wait_finish = vb2_ops_wait_finish,
1508 };
1509
1510 static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1511 {
1512 int ret;
1513 struct vb2_queue *vq = &pcdev->vb2_vq;
1514
1515 memset(vq, 0, sizeof(*vq));
1516 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1517 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1518 vq->drv_priv = pcdev;
1519 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1520 vq->buf_struct_size = sizeof(struct pxa_buffer);
1521 vq->dev = pcdev->v4l2_dev.dev;
1522
1523 vq->ops = &pxac_vb2_ops;
1524 vq->mem_ops = &vb2_dma_sg_memops;
1525 vq->lock = &pcdev->mlock;
1526
1527 ret = vb2_queue_init(vq);
1528 dev_dbg(pcdev_to_dev(pcdev),
1529 "vb2_queue_init(vq=%p): %d\n", vq, ret);
1530
1531 return ret;
1532 }
1533
1534 /*
1535 * Video ioctls section
1536 */
1537 static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1538 {
1539 unsigned int bus_width = pcdev->current_fmt->host_fmt->bits_per_sample;
1540 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1541 u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1542 int mbus_config;
1543 int ret;
1544
1545 if (!((1 << (bus_width - 1)) & pcdev->width_flags)) {
1546 dev_err(pcdev_to_dev(pcdev), "Unsupported bus width %u",
1547 bus_width);
1548 return -EINVAL;
1549 }
1550
1551 pcdev->channels = 1;
1552
1553 /* Make choices, based on platform preferences */
1554 mbus_config = 0;
1555 if (pcdev->platform_flags & PXA_CAMERA_MASTER)
1556 mbus_config |= V4L2_MBUS_MASTER;
1557 else
1558 mbus_config |= V4L2_MBUS_SLAVE;
1559
1560 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1561 mbus_config |= V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1562 else
1563 mbus_config |= V4L2_MBUS_HSYNC_ACTIVE_LOW;
1564
1565 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1566 mbus_config |= V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1567 else
1568 mbus_config |= V4L2_MBUS_VSYNC_ACTIVE_LOW;
1569
1570 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1571 mbus_config |= V4L2_MBUS_PCLK_SAMPLE_RISING;
1572 else
1573 mbus_config |= V4L2_MBUS_PCLK_SAMPLE_FALLING;
1574 mbus_config |= V4L2_MBUS_DATA_ACTIVE_HIGH;
1575
1576 ret = sensor_call(pcdev, pad, get_mbus_config, 0, &cfg);
1577 if (ret < 0 && ret != -ENOIOCTLCMD) {
1578 dev_err(pcdev_to_dev(pcdev),
1579 "Failed to call get_mbus_config: %d\n", ret);
1580 return ret;
1581 }
1582
1583 /*
1584 * If the media bus configuration of the sensor differs, make sure it
1585 * is supported by the platform.
1586 *
1587 * PXA does not support V4L2_MBUS_DATA_ACTIVE_LOW and the bus mastering
1588 * roles should match.
1589 */
1590 if (cfg.bus.parallel.flags != mbus_config) {
1591 unsigned int pxa_mbus_role = mbus_config & (V4L2_MBUS_MASTER |
1592 V4L2_MBUS_SLAVE);
1593 unsigned int flags = cfg.bus.parallel.flags;
1594
1595 if (pxa_mbus_role != (flags & (V4L2_MBUS_MASTER |
1596 V4L2_MBUS_SLAVE))) {
1597 dev_err(pcdev_to_dev(pcdev),
1598 "Unsupported mbus configuration: bus mastering\n");
1599 return -EINVAL;
1600 }
1601
1602 if (flags & V4L2_MBUS_DATA_ACTIVE_LOW) {
1603 dev_err(pcdev_to_dev(pcdev),
1604 "Unsupported mbus configuration: DATA_ACTIVE_LOW\n");
1605 return -EINVAL;
1606 }
1607 }
1608
1609 pxa_camera_setup_cicr(pcdev, cfg.bus.parallel.flags, pixfmt);
1610
1611 return 0;
1612 }
1613
1614 static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1615 {
1616 .fourcc = V4L2_PIX_FMT_YUV422P,
1617 .name = "Planar YUV422 16 bit",
1618 .bits_per_sample = 8,
1619 .packing = PXA_MBUS_PACKING_2X8_PADHI,
1620 .order = PXA_MBUS_ORDER_LE,
1621 .layout = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1622 },
1623 };
1624
1625 /* This will be corrected as we get more formats */
1626 static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1627 {
1628 return fmt->packing == PXA_MBUS_PACKING_NONE ||
1629 (fmt->bits_per_sample == 8 &&
1630 fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1631 (fmt->bits_per_sample > 8 &&
1632 fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1633 }
1634
1635 static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
1636 unsigned int idx,
1637 struct pxa_camera_format_xlate *xlate)
1638 {
1639 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1640 int formats = 0, ret;
1641 struct v4l2_subdev_mbus_code_enum code = {
1642 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1643 .index = idx,
1644 };
1645 const struct pxa_mbus_pixelfmt *fmt;
1646
1647 ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1648 if (ret < 0)
1649 /* No more formats */
1650 return 0;
1651
1652 fmt = pxa_mbus_get_fmtdesc(code.code);
1653 if (!fmt) {
1654 dev_err(pcdev_to_dev(pcdev),
1655 "Invalid format code #%u: %d\n", idx, code.code);
1656 return 0;
1657 }
1658
1659 switch (code.code) {
1660 case MEDIA_BUS_FMT_UYVY8_2X8:
1661 formats++;
1662 if (xlate) {
1663 xlate->host_fmt = &pxa_camera_formats[0];
1664 xlate->code = code.code;
1665 xlate++;
1666 dev_dbg(pcdev_to_dev(pcdev),
1667 "Providing format %s using code %d\n",
1668 pxa_camera_formats[0].name, code.code);
1669 }
1670 fallthrough;
1671 case MEDIA_BUS_FMT_VYUY8_2X8:
1672 case MEDIA_BUS_FMT_YUYV8_2X8:
1673 case MEDIA_BUS_FMT_YVYU8_2X8:
1674 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1675 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1676 if (xlate)
1677 dev_dbg(pcdev_to_dev(pcdev),
1678 "Providing format %s packed\n",
1679 fmt->name);
1680 break;
1681 default:
1682 if (!pxa_camera_packing_supported(fmt))
1683 return 0;
1684 if (xlate)
1685 dev_dbg(pcdev_to_dev(pcdev),
1686 "Providing format %s in pass-through mode\n",
1687 fmt->name);
1688 break;
1689 }
1690
1691 /* Generic pass-through */
1692 formats++;
1693 if (xlate) {
1694 xlate->host_fmt = fmt;
1695 xlate->code = code.code;
1696 xlate++;
1697 }
1698
1699 return formats;
1700 }
1701
1702 static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
1703 {
1704 struct pxa_camera_format_xlate *xlate;
1705
1706 xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1707 pxa_camera_get_formats);
1708 if (IS_ERR(xlate))
1709 return PTR_ERR(xlate);
1710
1711 pcdev->user_formats = xlate;
1712 return 0;
1713 }
1714
1715 static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1716 {
1717 kfree(pcdev->user_formats);
1718 }
1719
1720 static int pxa_camera_check_frame(u32 width, u32 height)
1721 {
1722 /* limit to pxa hardware capabilities */
1723 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1724 (width & 0x01);
1725 }
1726
1727 #ifdef CONFIG_VIDEO_ADV_DEBUG
1728 static int pxac_vidioc_g_register(struct file *file, void *priv,
1729 struct v4l2_dbg_register *reg)
1730 {
1731 struct pxa_camera_dev *pcdev = video_drvdata(file);
1732
1733 if (reg->reg > CIBR2)
1734 return -ERANGE;
1735
1736 reg->val = __raw_readl(pcdev->base + reg->reg);
1737 reg->size = sizeof(__u32);
1738 return 0;
1739 }
1740
1741 static int pxac_vidioc_s_register(struct file *file, void *priv,
1742 const struct v4l2_dbg_register *reg)
1743 {
1744 struct pxa_camera_dev *pcdev = video_drvdata(file);
1745
1746 if (reg->reg > CIBR2)
1747 return -ERANGE;
1748 if (reg->size != sizeof(__u32))
1749 return -EINVAL;
1750 __raw_writel(reg->val, pcdev->base + reg->reg);
1751 return 0;
1752 }
1753 #endif
1754
1755 static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv,
1756 struct v4l2_fmtdesc *f)
1757 {
1758 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1759 const struct pxa_mbus_pixelfmt *format;
1760 unsigned int idx;
1761
1762 for (idx = 0; pcdev->user_formats[idx].code; idx++);
1763 if (f->index >= idx)
1764 return -EINVAL;
1765
1766 format = pcdev->user_formats[f->index].host_fmt;
1767 f->pixelformat = format->fourcc;
1768 return 0;
1769 }
1770
1771 static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1772 struct v4l2_format *f)
1773 {
1774 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1775 struct v4l2_pix_format *pix = &f->fmt.pix;
1776
1777 pix->width = pcdev->current_pix.width;
1778 pix->height = pcdev->current_pix.height;
1779 pix->bytesperline = pcdev->current_pix.bytesperline;
1780 pix->sizeimage = pcdev->current_pix.sizeimage;
1781 pix->field = pcdev->current_pix.field;
1782 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
1783 pix->colorspace = pcdev->current_pix.colorspace;
1784 dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
1785 pcdev->current_fmt->host_fmt->fourcc);
1786 return 0;
1787 }
1788
1789 static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1790 struct v4l2_format *f)
1791 {
1792 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1793 const struct pxa_camera_format_xlate *xlate;
1794 struct v4l2_pix_format *pix = &f->fmt.pix;
1795 struct v4l2_subdev_pad_config pad_cfg;
1796 struct v4l2_subdev_state pad_state = {
1797 .pads = &pad_cfg,
1798 };
1799 struct v4l2_subdev_format format = {
1800 .which = V4L2_SUBDEV_FORMAT_TRY,
1801 };
1802 struct v4l2_mbus_framefmt *mf = &format.format;
1803 __u32 pixfmt = pix->pixelformat;
1804 int ret;
1805
1806 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1807 if (!xlate) {
1808 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1809 return -EINVAL;
1810 }
1811
1812 /*
1813 * Limit to pxa hardware capabilities. YUV422P planar format requires
1814 * images size to be a multiple of 16 bytes. If not, zeros will be
1815 * inserted between Y and U planes, and U and V planes, which violates
1816 * the YUV422P standard.
1817 */
1818 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1819 &pix->height, 32, 2048, 0,
1820 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1821
1822 v4l2_fill_mbus_format(mf, pix, xlate->code);
1823 ret = sensor_call(pcdev, pad, set_fmt, &pad_state, &format);
1824 if (ret < 0)
1825 return ret;
1826
1827 v4l2_fill_pix_format(pix, mf);
1828
1829 /* Only progressive video supported so far */
1830 switch (mf->field) {
1831 case V4L2_FIELD_ANY:
1832 case V4L2_FIELD_NONE:
1833 pix->field = V4L2_FIELD_NONE;
1834 break;
1835 default:
1836 /* TODO: support interlaced at least in pass-through mode */
1837 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1838 mf->field);
1839 return -EINVAL;
1840 }
1841
1842 ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1843 if (ret < 0)
1844 return ret;
1845
1846 pix->bytesperline = ret;
1847 ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1848 pix->height);
1849 if (ret < 0)
1850 return ret;
1851
1852 pix->sizeimage = ret;
1853 return 0;
1854 }
1855
1856 static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1857 struct v4l2_format *f)
1858 {
1859 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1860 const struct pxa_camera_format_xlate *xlate;
1861 struct v4l2_pix_format *pix = &f->fmt.pix;
1862 struct v4l2_subdev_format format = {
1863 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1864 };
1865 unsigned long flags;
1866 int ret, is_busy;
1867
1868 dev_dbg(pcdev_to_dev(pcdev),
1869 "s_fmt_vid_cap(pix=%dx%d:%x)\n",
1870 pix->width, pix->height, pix->pixelformat);
1871
1872 spin_lock_irqsave(&pcdev->lock, flags);
1873 is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
1874 spin_unlock_irqrestore(&pcdev->lock, flags);
1875
1876 if (is_busy)
1877 return -EBUSY;
1878
1879 ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
1880 if (ret)
1881 return ret;
1882
1883 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1884 pix->pixelformat);
1885 v4l2_fill_mbus_format(&format.format, pix, xlate->code);
1886 ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1887 if (ret < 0) {
1888 dev_warn(pcdev_to_dev(pcdev),
1889 "Failed to configure for format %x\n",
1890 pix->pixelformat);
1891 } else if (pxa_camera_check_frame(pix->width, pix->height)) {
1892 dev_warn(pcdev_to_dev(pcdev),
1893 "Camera driver produced an unsupported frame %dx%d\n",
1894 pix->width, pix->height);
1895 return -EINVAL;
1896 }
1897
1898 pcdev->current_fmt = xlate;
1899 pcdev->current_pix = *pix;
1900
1901 ret = pxa_camera_set_bus_param(pcdev);
1902 return ret;
1903 }
1904
1905 static int pxac_vidioc_querycap(struct file *file, void *priv,
1906 struct v4l2_capability *cap)
1907 {
1908 strscpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
1909 strscpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
1910 strscpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1911 return 0;
1912 }
1913
1914 static int pxac_vidioc_enum_input(struct file *file, void *priv,
1915 struct v4l2_input *i)
1916 {
1917 if (i->index > 0)
1918 return -EINVAL;
1919
1920 i->type = V4L2_INPUT_TYPE_CAMERA;
1921 strscpy(i->name, "Camera", sizeof(i->name));
1922
1923 return 0;
1924 }
1925
1926 static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1927 {
1928 *i = 0;
1929
1930 return 0;
1931 }
1932
1933 static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
1934 {
1935 if (i > 0)
1936 return -EINVAL;
1937
1938 return 0;
1939 }
1940
1941 static int pxac_sensor_set_power(struct pxa_camera_dev *pcdev, int on)
1942 {
1943 int ret;
1944
1945 ret = sensor_call(pcdev, core, s_power, on);
1946 if (ret == -ENOIOCTLCMD)
1947 ret = 0;
1948 if (ret) {
1949 dev_warn(pcdev_to_dev(pcdev),
1950 "Failed to put subdevice in %s mode: %d\n",
1951 on ? "normal operation" : "power saving", ret);
1952 }
1953
1954 return ret;
1955 }
1956
1957 static int pxac_fops_camera_open(struct file *filp)
1958 {
1959 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1960 int ret;
1961
1962 mutex_lock(&pcdev->mlock);
1963 ret = v4l2_fh_open(filp);
1964 if (ret < 0)
1965 goto out;
1966
1967 if (!v4l2_fh_is_singular_file(filp))
1968 goto out;
1969
1970 ret = pxac_sensor_set_power(pcdev, 1);
1971 if (ret)
1972 v4l2_fh_release(filp);
1973 out:
1974 mutex_unlock(&pcdev->mlock);
1975 return ret;
1976 }
1977
1978 static int pxac_fops_camera_release(struct file *filp)
1979 {
1980 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1981 int ret;
1982 bool fh_singular;
1983
1984 mutex_lock(&pcdev->mlock);
1985
1986 fh_singular = v4l2_fh_is_singular_file(filp);
1987
1988 ret = _vb2_fop_release(filp, NULL);
1989
1990 if (fh_singular)
1991 ret = pxac_sensor_set_power(pcdev, 0);
1992
1993 mutex_unlock(&pcdev->mlock);
1994
1995 return ret;
1996 }
1997
1998 static const struct v4l2_file_operations pxa_camera_fops = {
1999 .owner = THIS_MODULE,
2000 .open = pxac_fops_camera_open,
2001 .release = pxac_fops_camera_release,
2002 .read = vb2_fop_read,
2003 .poll = vb2_fop_poll,
2004 .mmap = vb2_fop_mmap,
2005 .unlocked_ioctl = video_ioctl2,
2006 };
2007
2008 static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
2009 .vidioc_querycap = pxac_vidioc_querycap,
2010
2011 .vidioc_enum_input = pxac_vidioc_enum_input,
2012 .vidioc_g_input = pxac_vidioc_g_input,
2013 .vidioc_s_input = pxac_vidioc_s_input,
2014
2015 .vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap,
2016 .vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap,
2017 .vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap,
2018 .vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap,
2019
2020 .vidioc_reqbufs = vb2_ioctl_reqbufs,
2021 .vidioc_create_bufs = vb2_ioctl_create_bufs,
2022 .vidioc_querybuf = vb2_ioctl_querybuf,
2023 .vidioc_qbuf = vb2_ioctl_qbuf,
2024 .vidioc_dqbuf = vb2_ioctl_dqbuf,
2025 .vidioc_expbuf = vb2_ioctl_expbuf,
2026 .vidioc_streamon = vb2_ioctl_streamon,
2027 .vidioc_streamoff = vb2_ioctl_streamoff,
2028 #ifdef CONFIG_VIDEO_ADV_DEBUG
2029 .vidioc_g_register = pxac_vidioc_g_register,
2030 .vidioc_s_register = pxac_vidioc_s_register,
2031 #endif
2032 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
2033 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2034 };
2035
2036 static const struct video_device pxa_camera_videodev_template = {
2037 .name = "pxa-camera",
2038 .minor = -1,
2039 .fops = &pxa_camera_fops,
2040 .ioctl_ops = &pxa_camera_ioctl_ops,
2041 .release = video_device_release_empty,
2042 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
2043 };
2044
2045 static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
2046 struct v4l2_subdev *subdev,
2047 struct v4l2_async_connection *asd)
2048 {
2049 int err;
2050 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
2051 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
2052 struct video_device *vdev = &pcdev->vdev;
2053 struct v4l2_pix_format *pix = &pcdev->current_pix;
2054 struct v4l2_subdev_format format = {
2055 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2056 };
2057 struct v4l2_mbus_framefmt *mf = &format.format;
2058
2059 dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
2060 __func__);
2061 mutex_lock(&pcdev->mlock);
2062 *vdev = pxa_camera_videodev_template;
2063 vdev->v4l2_dev = v4l2_dev;
2064 vdev->lock = &pcdev->mlock;
2065 pcdev->sensor = subdev;
2066 pcdev->vdev.queue = &pcdev->vb2_vq;
2067 pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
2068 pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
2069 video_set_drvdata(&pcdev->vdev, pcdev);
2070
2071 err = pxa_camera_build_formats(pcdev);
2072 if (err) {
2073 dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
2074 err);
2075 goto out;
2076 }
2077
2078 pcdev->current_fmt = pcdev->user_formats;
2079 pix->field = V4L2_FIELD_NONE;
2080 pix->width = DEFAULT_WIDTH;
2081 pix->height = DEFAULT_HEIGHT;
2082 pix->bytesperline =
2083 pxa_mbus_bytes_per_line(pix->width,
2084 pcdev->current_fmt->host_fmt);
2085 pix->sizeimage =
2086 pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2087 pix->bytesperline, pix->height);
2088 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
2089 v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
2090
2091 err = pxac_sensor_set_power(pcdev, 1);
2092 if (err)
2093 goto out;
2094
2095 err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
2096 if (err)
2097 goto out_sensor_poweroff;
2098
2099 v4l2_fill_pix_format(pix, mf);
2100 pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
2101 __func__, pix->colorspace, pix->pixelformat);
2102
2103 err = pxa_camera_init_videobuf2(pcdev);
2104 if (err)
2105 goto out_sensor_poweroff;
2106
2107 err = video_register_device(&pcdev->vdev, VFL_TYPE_VIDEO, -1);
2108 if (err) {
2109 v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
2110 pcdev->sensor = NULL;
2111 } else {
2112 dev_info(pcdev_to_dev(pcdev),
2113 "PXA Camera driver attached to camera %s\n",
2114 subdev->name);
2115 }
2116
2117 out_sensor_poweroff:
2118 err = pxac_sensor_set_power(pcdev, 0);
2119 out:
2120 mutex_unlock(&pcdev->mlock);
2121 return err;
2122 }
2123
2124 static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
2125 struct v4l2_subdev *subdev,
2126 struct v4l2_async_connection *asd)
2127 {
2128 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
2129
2130 mutex_lock(&pcdev->mlock);
2131 dev_info(pcdev_to_dev(pcdev),
2132 "PXA Camera driver detached from camera %s\n",
2133 subdev->name);
2134
2135 /* disable capture, disable interrupts */
2136 __raw_writel(0x3ff, pcdev->base + CICR0);
2137
2138 /* Stop DMA engine */
2139 pxa_dma_stop_channels(pcdev);
2140
2141 pxa_camera_destroy_formats(pcdev);
2142
2143 video_unregister_device(&pcdev->vdev);
2144 pcdev->sensor = NULL;
2145
2146 mutex_unlock(&pcdev->mlock);
2147 }
2148
2149 static const struct v4l2_async_notifier_operations pxa_camera_sensor_ops = {
2150 .bound = pxa_camera_sensor_bound,
2151 .unbind = pxa_camera_sensor_unbind,
2152 };
2153
2154 /*
2155 * Driver probe, remove, suspend and resume operations
2156 */
2157 static int pxa_camera_suspend(struct device *dev)
2158 {
2159 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2160 int i = 0, ret = 0;
2161
2162 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
2163 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
2164 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
2165 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
2166 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2167
2168 if (pcdev->sensor)
2169 ret = pxac_sensor_set_power(pcdev, 0);
2170
2171 return ret;
2172 }
2173
2174 static int pxa_camera_resume(struct device *dev)
2175 {
2176 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2177 int i = 0, ret = 0;
2178
2179 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
2180 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
2181 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
2182 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
2183 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2184
2185 if (pcdev->sensor) {
2186 ret = pxac_sensor_set_power(pcdev, 1);
2187 }
2188
2189 /* Restart frame capture if active buffer exists */
2190 if (!ret && pcdev->active)
2191 pxa_camera_start_capture(pcdev);
2192
2193 return ret;
2194 }
2195
2196 static int pxa_camera_pdata_from_dt(struct device *dev,
2197 struct pxa_camera_dev *pcdev)
2198 {
2199 u32 mclk_rate;
2200 struct v4l2_async_connection *asd;
2201 struct device_node *np = dev->of_node;
2202 struct v4l2_fwnode_endpoint ep = { .bus_type = 0 };
2203 int err = of_property_read_u32(np, "clock-frequency",
2204 &mclk_rate);
2205 if (!err) {
2206 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
2207 pcdev->mclk = mclk_rate;
2208 }
2209
2210 np = of_graph_get_next_endpoint(np, NULL);
2211 if (!np) {
2212 dev_err(dev, "could not find endpoint\n");
2213 return -EINVAL;
2214 }
2215
2216 err = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
2217 if (err) {
2218 dev_err(dev, "could not parse endpoint\n");
2219 goto out;
2220 }
2221
2222 switch (ep.bus.parallel.bus_width) {
2223 case 4:
2224 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
2225 break;
2226 case 5:
2227 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
2228 break;
2229 case 8:
2230 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
2231 break;
2232 case 9:
2233 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
2234 break;
2235 case 10:
2236 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2237 break;
2238 default:
2239 break;
2240 }
2241
2242 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
2243 pcdev->platform_flags |= PXA_CAMERA_MASTER;
2244 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2245 pcdev->platform_flags |= PXA_CAMERA_HSP;
2246 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2247 pcdev->platform_flags |= PXA_CAMERA_VSP;
2248 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2249 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
2250 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
2251 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
2252
2253 asd = v4l2_async_nf_add_fwnode_remote(&pcdev->notifier,
2254 of_fwnode_handle(np),
2255 struct v4l2_async_connection);
2256 if (IS_ERR(asd))
2257 err = PTR_ERR(asd);
2258 out:
2259 of_node_put(np);
2260
2261 return err;
2262 }
2263
2264 static int pxa_camera_probe(struct platform_device *pdev)
2265 {
2266 struct pxa_camera_dev *pcdev;
2267 struct resource *res;
2268 void __iomem *base;
2269 struct dma_slave_config config = {
2270 .src_addr_width = 0,
2271 .src_maxburst = 8,
2272 .direction = DMA_DEV_TO_MEM,
2273 };
2274 int irq;
2275 int err = 0, i;
2276
2277 irq = platform_get_irq(pdev, 0);
2278 if (irq < 0)
2279 return -ENODEV;
2280
2281 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2282 if (!pcdev) {
2283 dev_err(&pdev->dev, "Could not allocate pcdev\n");
2284 return -ENOMEM;
2285 }
2286
2287 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
2288 if (IS_ERR(pcdev->clk))
2289 return PTR_ERR(pcdev->clk);
2290
2291 /*
2292 * Request the regions.
2293 */
2294 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2295 if (IS_ERR(base))
2296 return PTR_ERR(base);
2297
2298 pcdev->irq = irq;
2299 pcdev->base = base;
2300
2301 err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2302 if (err)
2303 return err;
2304
2305 v4l2_async_nf_init(&pcdev->notifier, &pcdev->v4l2_dev);
2306 pcdev->res = res;
2307 pcdev->pdata = pdev->dev.platform_data;
2308 if (pcdev->pdata) {
2309 struct v4l2_async_connection *asd;
2310
2311 pcdev->platform_flags = pcdev->pdata->flags;
2312 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2313 asd = v4l2_async_nf_add_i2c(&pcdev->notifier,
2314 pcdev->pdata->sensor_i2c_adapter_id,
2315 pcdev->pdata->sensor_i2c_address,
2316 struct v4l2_async_connection);
2317 if (IS_ERR(asd))
2318 err = PTR_ERR(asd);
2319 } else if (pdev->dev.of_node) {
2320 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev);
2321 } else {
2322 err = -ENODEV;
2323 }
2324 if (err < 0)
2325 goto exit_v4l2_device_unregister;
2326
2327 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
2328 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2329 /*
2330 * Platform hasn't set available data widths. This is bad.
2331 * Warn and use a default.
2332 */
2333 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
2334 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2335 }
2336 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
2337 pcdev->width_flags = 1 << 7;
2338 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
2339 pcdev->width_flags |= 1 << 8;
2340 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
2341 pcdev->width_flags |= 1 << 9;
2342 if (!pcdev->mclk) {
2343 dev_warn(&pdev->dev,
2344 "mclk == 0! Please, fix your platform data. Using default 20MHz\n");
2345 pcdev->mclk = 20000000;
2346 }
2347
2348 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2349
2350 INIT_LIST_HEAD(&pcdev->capture);
2351 spin_lock_init(&pcdev->lock);
2352 mutex_init(&pcdev->mlock);
2353
2354 /* request dma */
2355 pcdev->dma_chans[0] = dma_request_chan(&pdev->dev, "CI_Y");
2356 if (IS_ERR(pcdev->dma_chans[0])) {
2357 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2358 err = PTR_ERR(pcdev->dma_chans[0]);
2359 goto exit_notifier_cleanup;
2360 }
2361
2362 pcdev->dma_chans[1] = dma_request_chan(&pdev->dev, "CI_U");
2363 if (IS_ERR(pcdev->dma_chans[1])) {
2364 dev_err(&pdev->dev, "Can't request DMA for U\n");
2365 err = PTR_ERR(pcdev->dma_chans[1]);
2366 goto exit_free_dma_y;
2367 }
2368
2369 pcdev->dma_chans[2] = dma_request_chan(&pdev->dev, "CI_V");
2370 if (IS_ERR(pcdev->dma_chans[2])) {
2371 dev_err(&pdev->dev, "Can't request DMA for V\n");
2372 err = PTR_ERR(pcdev->dma_chans[2]);
2373 goto exit_free_dma_u;
2374 }
2375
2376 for (i = 0; i < 3; i++) {
2377 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
2378 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
2379 if (err < 0) {
2380 dev_err(&pdev->dev, "dma slave config failed: %d\n",
2381 err);
2382 goto exit_free_dma;
2383 }
2384 }
2385
2386 tasklet_setup(&pcdev->task_eof, pxa_camera_eof);
2387
2388 pxa_camera_activate(pcdev);
2389
2390 platform_set_drvdata(pdev, pcdev);
2391
2392 err = pxa_camera_init_videobuf2(pcdev);
2393 if (err)
2394 goto exit_deactivate;
2395
2396 /* request irq */
2397 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
2398 PXA_CAM_DRV_NAME, pcdev);
2399 if (err) {
2400 dev_err(&pdev->dev, "Camera interrupt register failed\n");
2401 goto exit_deactivate;
2402 }
2403
2404 pcdev->notifier.ops = &pxa_camera_sensor_ops;
2405 err = v4l2_async_nf_register(&pcdev->notifier);
2406 if (err)
2407 goto exit_deactivate;
2408
2409 return 0;
2410 exit_deactivate:
2411 pxa_camera_deactivate(pcdev);
2412 tasklet_kill(&pcdev->task_eof);
2413 exit_free_dma:
2414 dma_release_channel(pcdev->dma_chans[2]);
2415 exit_free_dma_u:
2416 dma_release_channel(pcdev->dma_chans[1]);
2417 exit_free_dma_y:
2418 dma_release_channel(pcdev->dma_chans[0]);
2419 exit_notifier_cleanup:
2420 v4l2_async_nf_cleanup(&pcdev->notifier);
2421 exit_v4l2_device_unregister:
2422 v4l2_device_unregister(&pcdev->v4l2_dev);
2423 return err;
2424 }
2425
2426 static void pxa_camera_remove(struct platform_device *pdev)
2427 {
2428 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
2429
2430 pxa_camera_deactivate(pcdev);
2431 tasklet_kill(&pcdev->task_eof);
2432 dma_release_channel(pcdev->dma_chans[0]);
2433 dma_release_channel(pcdev->dma_chans[1]);
2434 dma_release_channel(pcdev->dma_chans[2]);
2435
2436 v4l2_async_nf_unregister(&pcdev->notifier);
2437 v4l2_async_nf_cleanup(&pcdev->notifier);
2438
2439 v4l2_device_unregister(&pcdev->v4l2_dev);
2440
2441 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2442 }
2443
2444 static const struct dev_pm_ops pxa_camera_pm = {
2445 .suspend = pxa_camera_suspend,
2446 .resume = pxa_camera_resume,
2447 };
2448
2449 static const struct of_device_id pxa_camera_of_match[] = {
2450 { .compatible = "marvell,pxa270-qci", },
2451 {},
2452 };
2453 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
2454
2455 static struct platform_driver pxa_camera_driver = {
2456 .driver = {
2457 .name = PXA_CAM_DRV_NAME,
2458 .pm = &pxa_camera_pm,
2459 .of_match_table = pxa_camera_of_match,
2460 },
2461 .probe = pxa_camera_probe,
2462 .remove_new = pxa_camera_remove,
2463 };
2464
2465 module_platform_driver(pxa_camera_driver);
2466
2467 MODULE_DESCRIPTION("PXA27x Camera Driver");
2468 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
2469 MODULE_LICENSE("GPL");
2470 MODULE_VERSION(PXA_CAM_VERSION);
2471 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git