drivers/misc/Kconfig

   1 #
   2 # Multifunction miscellaneous devices
   3 #
   4
   5 menu "Multifunction device drivers"
   6
   7 config MISC
   8         bool "Enable Driver Model for Misc drivers"
   9         depends on DM
  10         help
  11           Enable driver model for miscellaneous devices. This class is
  12           used only for those do not fit other more general classes. A
  13           set of generic read, write and ioctl methods may be used to
  14           access the device.
  15
  16 config SPL_MISC
  17         bool "Enable Driver Model for Misc drivers in SPL"
  18         depends on SPL_DM
  19         default MISC
  20         help
  21           Enable driver model for miscellaneous devices. This class is
  22           used only for those do not fit other more general classes. A
  23           set of generic read, write and ioctl methods may be used to
  24           access the device.
  25
  26 config TPL_MISC
  27         bool "Enable Driver Model for Misc drivers in TPL"
  28         depends on TPL_DM
  29         default MISC
  30         help
  31           Enable driver model for miscellaneous devices. This class is
  32           used only for those do not fit other more general classes. A
  33           set of generic read, write and ioctl methods may be used to
  34           access the device.
  35
  36 config VPL_MISC
  37         bool "Enable Driver Model for Misc drivers in VPL"
  38         depends on VPL_DM
  39         default MISC
  40         help
  41           Enable driver model for miscellaneous devices. This class is
  42           used only for those do not fit other more general classes. A
  43           set of generic read, write and ioctl methods may be used to
  44           access the device.
  45
  46 config NVMEM
  47         bool "NVMEM support"
  48         help
  49           This adds support for a common interface to different types of
  50           non-volatile memory. Consumers can use nvmem-cells properties to look
  51           up hardware configuration data such as MAC addresses and calibration
  52           settings.
  53
  54 config SPL_NVMEM
  55         bool "NVMEM support in SPL"
  56         help
  57           This adds support for a common interface to different types of
  58           non-volatile memory. Consumers can use nvmem-cells properties to look
  59           up hardware configuration data such as MAC addresses and calibration
  60           settings.
  61
  62 config ALTERA_SYSID
  63         bool "Altera Sysid support"
  64         depends on MISC
  65         help
  66           Select this to enable a sysid for Altera devices. Please find
  67           details on the "Embedded Peripherals IP User Guide" of Altera.
  68
  69 config ATSHA204A
  70         bool "Support for Atmel ATSHA204A module"
  71         select BITREVERSE
  72         depends on MISC
  73         help
  74            Enable support for I2C connected Atmel's ATSHA204A
  75            CryptoAuthentication module found for example on the Turris Omnia
  76            board.
  77
  78 config GATEWORKS_SC
  79         bool "Gateworks System Controller Support"
  80         depends on MISC
  81         help
  82           Enable access for the Gateworks System Controller used on Gateworks
  83           boards to provide a boot watchdog, power control, temperature monitor,
  84           voltage ADCs, and EEPROM.
  85
  86 config ROCKCHIP_EFUSE
  87         bool "Rockchip e-fuse support"
  88         depends on MISC
  89         help
  90           Enable (read-only) access for the e-fuse block found in Rockchip
  91           SoCs: accesses can either be made using byte addressing and a length
  92           or through child-nodes that are generated based on the e-fuse map
  93           retrieved from the DTS.
  94
  95           This driver currently supports the RK3399 only, but can easily be
  96           extended (by porting the read function from the Linux kernel sources)
  97           to support other recent Rockchip devices.
  98
  99 config ROCKCHIP_OTP
 100         bool "Rockchip OTP Support"
 101         depends on MISC
 102         help
 103           Enable (read-only) access for the one-time-programmable memory block
 104           found in Rockchip SoCs: accesses can either be made using byte
 105           addressing and a length or through child-nodes that are generated
 106           based on the e-fuse map retrieved from the DTS.
 107
 108 config SIFIVE_OTP
 109         bool "SiFive eMemory OTP driver"
 110         depends on MISC
 111         help
 112           Enable support for reading and writing the eMemory OTP on the
 113           SiFive SoCs.
 114
 115 config VEXPRESS_CONFIG
 116         bool "Enable support for Arm Versatile Express config bus"
 117         depends on MISC
 118         help
 119           If you say Y here, you will get support for accessing the
 120           configuration bus on the Arm Versatile Express boards via
 121           a sysreg driver.
 122
 123 config CMD_CROS_EC
 124         bool "Enable crosec command"
 125         depends on CROS_EC
 126         help
 127           Enable command-line access to the Chrome OS EC (Embedded
 128           Controller). This provides the 'crosec' command which has
 129           a number of sub-commands for performing EC tasks such as
 130           updating its flash, accessing a small saved context area
 131           and talking to the I2C bus behind the EC (if there is one).
 132
 133 config CROS_EC
 134         bool "Enable Chrome OS EC"
 135         help
 136           Enable access to the Chrome OS EC. This is a separate
 137           microcontroller typically available on a SPI bus on Chromebooks. It
 138           provides access to the keyboard, some internal storage and may
 139           control access to the battery and main PMIC depending on the
 140           device. You can use the 'crosec' command to access it.
 141
 142 config SPL_CROS_EC
 143         bool "Enable Chrome OS EC in SPL"
 144         depends on SPL_MISC
 145         help
 146           Enable access to the Chrome OS EC in SPL. This is a separate
 147           microcontroller typically available on a SPI bus on Chromebooks. It
 148           provides access to the keyboard, some internal storage and may
 149           control access to the battery and main PMIC depending on the
 150           device. You can use the 'crosec' command to access it.
 151
 152 config TPL_CROS_EC
 153         bool "Enable Chrome OS EC in TPL"
 154         depends on TPL_MISC
 155         help
 156           Enable access to the Chrome OS EC in TPL. This is a separate
 157           microcontroller typically available on a SPI bus on Chromebooks. It
 158           provides access to the keyboard, some internal storage and may
 159           control access to the battery and main PMIC depending on the
 160           device. You can use the 'crosec' command to access it.
 161
 162 config VPL_CROS_EC
 163         bool "Enable Chrome OS EC in VPL"
 164         depends on VPL_MISC
 165         help
 166           Enable access to the Chrome OS EC in VPL. This is a separate
 167           microcontroller typically available on a SPI bus on Chromebooks. It
 168           provides access to the keyboard, some internal storage and may
 169           control access to the battery and main PMIC depending on the
 170           device. You can use the 'crosec' command to access it.
 171
 172 config CROS_EC_I2C
 173         bool "Enable Chrome OS EC I2C driver"
 174         depends on CROS_EC
 175         help
 176           Enable I2C access to the Chrome OS EC. This is used on older
 177           ARM Chromebooks such as snow and spring before the standard bus
 178           changed to SPI. The EC will accept commands across the I2C using
 179           a special message protocol, and provide responses.
 180
 181 config CROS_EC_LPC
 182         bool "Enable Chrome OS EC LPC driver"
 183         depends on CROS_EC
 184         help
 185           Enable I2C access to the Chrome OS EC. This is used on x86
 186           Chromebooks such as link and falco. The keyboard is provided
 187           through a legacy port interface, so on x86 machines the main
 188           function of the EC is power and thermal management.
 189
 190 config SPL_CROS_EC_LPC
 191         bool "Enable Chrome OS EC LPC driver in SPL"
 192         depends on CROS_EC && SPL_MISC
 193         help
 194           Enable I2C access to the Chrome OS EC. This is used on x86
 195           Chromebooks such as link and falco. The keyboard is provided
 196           through a legacy port interface, so on x86 machines the main
 197           function of the EC is power and thermal management.
 198
 199 config TPL_CROS_EC_LPC
 200         bool "Enable Chrome OS EC LPC driver in TPL"
 201         depends on CROS_EC && TPL_MISC
 202         help
 203           Enable I2C access to the Chrome OS EC. This is used on x86
 204           Chromebooks such as link and falco. The keyboard is provided
 205           through a legacy port interface, so on x86 machines the main
 206           function of the EC is power and thermal management.
 207
 208 config VPL_CROS_EC_LPC
 209         bool "Enable Chrome OS EC LPC driver in VPL"
 210         depends on CROS_EC && VPL_MISC
 211         help
 212           Enable I2C access to the Chrome OS EC. This is used on x86
 213           Chromebooks such as link and falco. The keyboard is provided
 214           through a legacy port interface, so on x86 machines the main
 215           function of the EC is power and thermal management.
 216
 217 config CROS_EC_SANDBOX
 218         bool "Enable Chrome OS EC sandbox driver"
 219         depends on CROS_EC && SANDBOX
 220         help
 221           Enable a sandbox emulation of the Chrome OS EC. This supports
 222           keyboard (use the -l flag to enable the LCD), verified boot context,
 223           EC flash read/write/erase support and a few other things. It is
 224           enough to perform a Chrome OS verified boot on sandbox.
 225
 226 config SPL_CROS_EC_SANDBOX
 227         bool "Enable Chrome OS EC sandbox driver in SPL"
 228         depends on SPL_CROS_EC && SANDBOX
 229         help
 230           Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
 231           keyboard (use the -l flag to enable the LCD), verified boot context,
 232           EC flash read/write/erase support and a few other things. It is
 233           enough to perform a Chrome OS verified boot on sandbox.
 234
 235 config TPL_CROS_EC_SANDBOX
 236         bool "Enable Chrome OS EC sandbox driver in TPL"
 237         depends on TPL_CROS_EC && SANDBOX
 238         help
 239           Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
 240           keyboard (use the -l flag to enable the LCD), verified boot context,
 241           EC flash read/write/erase support and a few other things. It is
 242           enough to perform a Chrome OS verified boot on sandbox.
 243
 244 config VPL_CROS_EC_SANDBOX
 245         bool "Enable Chrome OS EC sandbox driver in VPL"
 246         depends on VPL_CROS_EC && SANDBOX
 247         help
 248           Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
 249           keyboard (use the -l flag to enable the LCD), verified boot context,
 250           EC flash read/write/erase support and a few other things. It is
 251           enough to perform a Chrome OS verified boot on sandbox.
 252
 253 config CROS_EC_SPI
 254         bool "Enable Chrome OS EC SPI driver"
 255         depends on CROS_EC
 256         help
 257           Enable SPI access to the Chrome OS EC. This is used on newer
 258           ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
 259           provides a faster and more robust interface than I2C but the bugs
 260           are less interesting.
 261
 262 config DS4510
 263         bool "Enable support for DS4510 CPU supervisor"
 264         help
 265           Enable support for the Maxim DS4510 CPU supervisor. It has an
 266           integrated 64-byte EEPROM, four programmable non-volatile I/O pins
 267           and a configurable timer for the supervisor function. The device is
 268           connected over I2C.
 269
 270 config FSL_SEC_MON
 271         bool "Enable FSL SEC_MON Driver"
 272         help
 273           Freescale Security Monitor block is responsible for monitoring
 274           system states.
 275           Security Monitor can be transitioned on any security failures,
 276           like software violations or hardware security violations.
 277
 278 config IRQ
 279         bool "Interrupt controller"
 280         help
 281           This enables support for interrupt controllers, including ITSS.
 282           Some devices have extra features, such as Apollo Lake. The
 283           device has its own uclass since there are several operations
 284           involved.
 285
 286 config JZ4780_EFUSE
 287         bool "Ingenic JZ4780 eFUSE support"
 288         depends on ARCH_JZ47XX
 289         help
 290           This selects support for the eFUSE on Ingenic JZ4780 SoCs.
 291
 292 config LS2_SFP
 293         bool "Layerscape Security Fuse Processor"
 294         depends on FSL_LSCH2 || ARCH_LS1021A
 295         depends on MISC
 296         imply DM_REGULATOR
 297         help
 298           This adds support for the Security Fuse Processor found on Layerscape
 299           SoCs. It contains various fuses related to secure boot, including the
 300           Super Root Key hash, One-Time-Programmable Master Key, Debug
 301           Challenge/Response values, and others. Fuses are numbered according
 302           to their four-byte offset from the start of the bank.
 303
 304           If you don't need to read/program fuses, say 'n'.
 305
 306 config MXC_OCOTP
 307         bool "Enable MXC OCOTP Driver"
 308         depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
 309         default y
 310         help
 311           If you say Y here, you will get support for the One Time
 312           Programmable memory pages that are stored on the some
 313           Freescale i.MX processors.
 314
 315 config SPL_MXC_OCOTP
 316         bool "Enable MXC OCOTP driver in SPL"
 317         depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
 318         default y
 319         help
 320           If you say Y here, you will get support for the One Time
 321           Programmable memory pages, that are stored on some
 322           Freescale i.MX processors, in SPL.
 323
 324 config NUVOTON_NCT6102D
 325         bool "Enable Nuvoton NCT6102D Super I/O driver"
 326         help
 327           If you say Y here, you will get support for the Nuvoton
 328           NCT6102D Super I/O driver. This can be used to enable or
 329           disable the legacy UART, the watchdog or other devices
 330           in the Nuvoton Super IO chips on X86 platforms.
 331
 332 config P2SB
 333         bool "Intel Primary to Sideband Bridge"
 334         depends on X86 || SANDBOX
 335         help
 336           This enables support for the Intel Primary to Sideband Bridge,
 337           abbreviated to P2SB. The P2SB is used to access various peripherals
 338           such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
 339           space. The space is segmented into different channels and peripherals
 340           are accessed by device-specific means within those channels. Devices
 341           should be added in the device tree as subnodes of the P2SB. A
 342           Peripheral Channel Register? (PCR) API is provided to access those
 343           devices - see pcr_readl(), etc.
 344
 345 config SPL_P2SB
 346         bool "Intel Primary to Sideband Bridge in SPL"
 347         depends on SPL_MISC && (X86 || SANDBOX)
 348         help
 349           The Primary to Sideband Bridge is used to access various peripherals
 350           through memory-mapped I/O in a large chunk of PCI space. The space is
 351           segmented into different channels and peripherals are accessed by
 352           device-specific means within those channels. Devices should be added
 353           in the device tree as subnodes of the p2sb.
 354
 355 config TPL_P2SB
 356         bool "Intel Primary to Sideband Bridge in TPL"
 357         depends on TPL_MISC && (X86 || SANDBOX)
 358         help
 359           The Primary to Sideband Bridge is used to access various peripherals
 360           through memory-mapped I/O in a large chunk of PCI space. The space is
 361           segmented into different channels and peripherals are accessed by
 362           device-specific means within those channels. Devices should be added
 363           in the device tree as subnodes of the p2sb.
 364
 365 config PWRSEQ
 366         bool "Enable power-sequencing drivers"
 367         depends on DM
 368         help
 369           Power-sequencing drivers provide support for controlling power for
 370           devices. They are typically referenced by a phandle from another
 371           device. When the device is started up, its power sequence can be
 372           initiated.
 373
 374 config SPL_PWRSEQ
 375         bool "Enable power-sequencing drivers for SPL"
 376         depends on SPL_MISC && PWRSEQ
 377         help
 378           Power-sequencing drivers provide support for controlling power for
 379           devices. They are typically referenced by a phandle from another
 380           device. When the device is started up, its power sequence can be
 381           initiated.
 382
 383 config PCA9551_LED
 384         bool "Enable PCA9551 LED driver"
 385         help
 386           Enable driver for PCA9551 LED controller. This controller
 387           is connected via I2C. So I2C needs to be enabled.
 388
 389 config PCA9551_I2C_ADDR
 390         hex "I2C address of PCA9551 LED controller"
 391         depends on PCA9551_LED
 392         default 0x60
 393         help
 394           The I2C address of the PCA9551 LED controller.
 395
 396 config STM32MP_FUSE
 397         bool "Enable STM32MP fuse wrapper providing the fuse API"
 398         depends on ARCH_STM32MP && MISC
 399         default y if CMD_FUSE
 400         help
 401           If you say Y here, you will get support for the fuse API (OTP)
 402           for STM32MP architecture.
 403           This API is needed for CMD_FUSE.
 404
 405 config STM32_RCC
 406         bool "Enable RCC driver for the STM32 SoC's family"
 407         depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
 408         help
 409           Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
 410           block) is responsible of the management of the clock and reset
 411           generation.
 412           This driver is similar to an MFD driver in the Linux kernel.
 413
 414 config TEGRA_CAR
 415         bool "Enable support for the Tegra CAR driver"
 416         depends on TEGRA_NO_BPMP
 417         help
 418           The Tegra CAR (Clock and Reset Controller) is a HW module that
 419           controls almost all clocks and resets in a Tegra SoC.
 420
 421 config TEGRA186_BPMP
 422         bool "Enable support for the Tegra186 BPMP driver"
 423         depends on TEGRA186
 424         help
 425           The Tegra BPMP (Boot and Power Management Processor) is a separate
 426           auxiliary CPU embedded into Tegra to perform power management work,
 427           and controls related features such as clocks, resets, power domains,
 428           PMIC I2C bus, etc. This driver provides the core low-level
 429           communication path by which feature-specific drivers (such as clock)
 430           can make requests to the BPMP. This driver is similar to an MFD
 431           driver in the Linux kernel.
 432
 433 config TEST_DRV
 434         bool "Enable support for test drivers"
 435         default y if SANDBOX
 436         help
 437           This enables drivers and uclasses that provides a way of testing the
 438           operations of memory allocation and driver/uclass methods in driver
 439           model. This should only be enabled for testing as it is not useful for
 440           anything else.
 441
 442 config USB_HUB_USB251XB
 443         tristate "USB251XB Hub Controller Configuration Driver"
 444         depends on I2C
 445         help
 446           This option enables support for configuration via SMBus of the
 447           Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
 448           parameters may be set in devicetree or platform data.
 449           Say Y or M here if you need to configure such a device via SMBus.
 450
 451 config TWL4030_LED
 452         bool "Enable TWL4030 LED controller"
 453         help
 454           Enable this to add support for the TWL4030 LED controller.
 455
 456 config WINBOND_W83627
 457         bool "Enable Winbond Super I/O driver"
 458         help
 459           If you say Y here, you will get support for the Winbond
 460           W83627 Super I/O driver. This can be used to enable the
 461           legacy UART or other devices in the Winbond Super IO chips
 462           on X86 platforms.
 463
 464 config QFW
 465         bool
 466         help
 467           Hidden option to enable QEMU fw_cfg interface and uclass. This will
 468           be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
 469
 470 config QFW_PIO
 471         bool
 472         depends on QFW
 473         help
 474           Hidden option to enable PIO QEMU fw_cfg interface. This will be
 475           selected by the appropriate QEMU board.
 476
 477 config QFW_MMIO
 478         bool
 479         depends on QFW
 480         help
 481           Hidden option to enable MMIO QEMU fw_cfg interface. This will be
 482           selected by the appropriate QEMU board.
 483
 484 config I2C_EEPROM
 485         bool "Enable driver for generic I2C-attached EEPROMs"
 486         depends on MISC
 487         help
 488           Enable a generic driver for EEPROMs attached via I2C.
 489
 490
 491 config SPL_I2C_EEPROM
 492         bool "Enable driver for generic I2C-attached EEPROMs for SPL"
 493         depends on SPL_MISC
 494         help
 495           This option is an SPL-variant of the I2C_EEPROM option.
 496           See the help of I2C_EEPROM for details.
 497
 498 config SYS_I2C_EEPROM_ADDR
 499         hex "Chip address of the EEPROM device"
 500         depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
 501         default 0
 502
 503 if I2C_EEPROM
 504
 505 config SYS_I2C_EEPROM_ADDR_OVERFLOW
 506         hex "EEPROM Address Overflow"
 507         default 0x0
 508         help
 509           EEPROM chips that implement "address overflow" are ones
 510           like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 511           address and the extra bits end up in the "chip address" bit
 512           slots. This makes a 24WC08 (1Kbyte) chip look like four 256
 513           byte chips.
 514
 515 endif
 516
 517 config GDSYS_RXAUI_CTRL
 518         bool "Enable gdsys RXAUI control driver"
 519         depends on MISC
 520         help
 521           Support gdsys FPGA's RXAUI control.
 522
 523 config GDSYS_IOEP
 524         bool "Enable gdsys IOEP driver"
 525         depends on MISC
 526         help
 527           Support gdsys FPGA's IO endpoint driver.
 528
 529 config MPC83XX_SERDES
 530         bool "Enable MPC83xx serdes driver"
 531         depends on MISC
 532         help
 533           Support for serdes found on MPC83xx SoCs.
 534
 535 config FS_LOADER
 536         bool "Enable loader driver for file system"
 537         help
 538           This is file system generic loader which can be used to load
 539           the file image from the storage into target such as memory.
 540
 541           The consumer driver would then use this loader to program whatever,
 542           ie. the FPGA device.
 543
 544 config SPL_FS_LOADER
 545         bool "Enable loader driver for file system"
 546         depends on SPL
 547         help
 548           This is file system generic loader which can be used to load
 549           the file image from the storage into target such as memory.
 550
 551           The consumer driver would then use this loader to program whatever,
 552           ie. the FPGA device.
 553
 554 config GDSYS_SOC
 555         bool "Enable gdsys SOC driver"
 556         depends on MISC
 557         help
 558           Support for gdsys IHS SOC, a simple bus associated with each gdsys
 559           IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
 560           register maps are contained within the FPGA's register map.
 561
 562 config IHS_FPGA
 563         bool "Enable IHS FPGA driver"
 564         depends on MISC
 565         help
 566           Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
 567           gdsys devices, which supply the majority of the functionality offered
 568           by the devices. This driver supports both CON and CPU variants of the
 569           devices, depending on the device tree entry.
 570 config ESM_K3
 571         bool "Enable K3 ESM driver"
 572         depends on ARCH_K3
 573         help
 574           Support ESM (Error Signaling Module) on TI K3 SoCs.
 575
 576 config MICROCHIP_FLEXCOM
 577         bool "Enable Microchip Flexcom driver"
 578         depends on MISC
 579         help
 580           The Atmel Flexcom is just a wrapper which embeds a SPI controller,
 581           an I2C controller and an USART.
 582           Only one function can be used at a time and is chosen at boot time
 583           according to the device tree.
 584
 585 config K3_AVS0
 586         depends on ARCH_K3 && SPL_DM_REGULATOR
 587         bool "AVS class 0 support for K3 devices"
 588         help
 589           K3 devices have the optimized voltage values for the main voltage
 590           domains stored in efuse within the VTM IP. This driver reads the
 591           optimized voltage from the efuse, so that it can be programmed
 592           to the PMIC on board.
 593
 594 config ESM_PMIC
 595         bool "Enable PMIC ESM driver"
 596         depends on DM_PMIC
 597         help
 598           Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
 599           typically to reboot the board in error condition.
 600
 601 config FSL_IFC
 602         bool
 603
 604 config SL28CPLD
 605         bool "Enable Kontron sl28cpld multi-function driver"
 606         depends on DM_I2C
 607         help
 608           Support for the Kontron sl28cpld management controller. This is
 609           the base driver which provides common access methods for the
 610           sub-drivers.
 611
 612 endmenu