]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/misc/fsl_iim.c
2 * (C) Copyright 2009-2013 ADVANSEE
3 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
5 * Based on the mpc512x iim code:
6 * Copyright 2008 Silicon Turnkey Express, Inc.
7 * Martha Marx <mmarx@silicontkx.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/errno.h>
16 #include <asm/arch/imx-regs.h>
17 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
18 #include <asm/arch/clock.h>
21 /* FSL IIM-specific constants */
22 #define STAT_BUSY 0x80
23 #define STAT_PRGD 0x02
24 #define STAT_SNSD 0x01
26 #define STATM_PRGD_M 0x02
27 #define STATM_SNSD_M 0x01
35 #define ERR_PARITYE 0x02
37 #define EMASK_PRGE_M 0x80
38 #define EMASK_WPE_M 0x40
39 #define EMASK_OPE_M 0x20
40 #define EMASK_RPE_M 0x10
41 #define EMASK_WLRE_M 0x08
42 #define EMASK_SNSE_M 0x04
43 #define EMASK_PARITYE_M 0x02
46 #define FCTL_PRG_LENGTH_MASK 0x70
47 #define FCTL_ESNS_N 0x08
48 #define FCTL_ESNS_0 0x04
49 #define FCTL_ESNS_1 0x02
52 #define UA_A_BANK_MASK 0x38
53 #define UA_A_ROWH_MASK 0x07
55 #define LA_A_ROWL_MASK 0xf8
56 #define LA_A_BIT_MASK 0x07
58 #define PREV_PROD_REV_MASK 0xf8
59 #define PREV_PROD_VT_MASK 0x07
61 /* Select the correct accessors depending on endianness */
62 #if __BYTE_ORDER == __LITTLE_ENDIAN
63 #define iim_read32 in_le32
64 #define iim_write32 out_le32
65 #define iim_clrsetbits32 clrsetbits_le32
66 #define iim_clrbits32 clrbits_le32
67 #define iim_setbits32 setbits_le32
68 #elif __BYTE_ORDER == __BIG_ENDIAN
69 #define iim_read32 in_be32
70 #define iim_write32 out_be32
71 #define iim_clrsetbits32 clrsetbits_be32
72 #define iim_clrbits32 clrbits_be32
73 #define iim_setbits32 setbits_be32
75 #error Endianess is not defined: please fix to continue
78 /* IIM control registers */
97 #if !defined(CONFIG_MX51) && !defined(CONFIG_MX53)
98 #define enable_efuse_prog_supply(enable)
101 static int prepare_access(struct fsl_iim
**regs
, u32 bank
, u32 word
, int assert,
104 *regs
= (struct fsl_iim
*)IIM_BASE_ADDR
;
106 if (bank
>= ARRAY_SIZE((*regs
)->bank
) ||
107 word
>= ARRAY_SIZE((*regs
)->bank
[0].word
) ||
109 printf("fsl_iim %s(): Invalid argument\n", caller
);
116 static void clear_status(struct fsl_iim
*regs
)
118 iim_setbits32(®s
->stat
, 0);
119 iim_setbits32(®s
->err
, 0);
122 static void finish_access(struct fsl_iim
*regs
, u32
*stat
, u32
*err
)
124 *stat
= iim_read32(®s
->stat
);
125 *err
= iim_read32(®s
->err
);
129 static int prepare_read(struct fsl_iim
**regs
, u32 bank
, u32 word
, u32
*val
,
134 ret
= prepare_access(regs
, bank
, word
, val
!= NULL
, caller
);
143 int fuse_read(u32 bank
, u32 word
, u32
*val
)
145 struct fsl_iim
*regs
;
149 ret
= prepare_read(®s
, bank
, word
, val
, __func__
);
153 *val
= iim_read32(®s
->bank
[bank
].word
[word
]);
154 finish_access(regs
, &stat
, &err
);
157 puts("fsl_iim fuse_read(): Read protect error\n");
164 static void direct_access(struct fsl_iim
*regs
, u32 bank
, u32 word
, u32 bit
,
165 u32 fctl
, u32
*stat
, u32
*err
)
167 iim_write32(®s
->ua
, bank
<< 3 | word
>> 5);
168 iim_write32(®s
->la
, (word
<< 3 | bit
) & 0xff);
169 if (fctl
== FCTL_PRG
)
170 iim_write32(®s
->prg_p
, 0xaa);
171 iim_setbits32(®s
->fctl
, fctl
);
172 while (iim_read32(®s
->stat
) & STAT_BUSY
)
174 finish_access(regs
, stat
, err
);
177 int fuse_sense(u32 bank
, u32 word
, u32
*val
)
179 struct fsl_iim
*regs
;
183 ret
= prepare_read(®s
, bank
, word
, val
, __func__
);
187 direct_access(regs
, bank
, word
, 0, FCTL_ESNS_N
, &stat
, &err
);
189 if (err
& ERR_SNSE
) {
190 puts("fsl_iim fuse_sense(): Explicit sense cycle error\n");
194 if (!(stat
& STAT_SNSD
)) {
195 puts("fsl_iim fuse_sense(): Explicit sense cycle did not complete\n");
199 *val
= iim_read32(®s
->sdat
);
203 static int prog_bit(struct fsl_iim
*regs
, u32 bank
, u32 word
, u32 bit
)
208 direct_access(regs
, bank
, word
, bit
, FCTL_PRG
, &stat
, &err
);
209 iim_write32(®s
->prg_p
, 0x00);
211 if (err
& ERR_PRGE
) {
212 puts("fsl_iim fuse_prog(): Program error\n");
217 puts("fsl_iim fuse_prog(): Write protect error\n");
221 if (!(stat
& STAT_PRGD
)) {
222 puts("fsl_iim fuse_prog(): Program did not complete\n");
229 static int prepare_write(struct fsl_iim
**regs
, u32 bank
, u32 word
, u32 val
,
232 return prepare_access(regs
, bank
, word
, !(val
& ~0xff), caller
);
235 int fuse_prog(u32 bank
, u32 word
, u32 val
)
237 struct fsl_iim
*regs
;
241 ret
= prepare_write(®s
, bank
, word
, val
, __func__
);
245 enable_efuse_prog_supply(1);
246 for (bit
= 0; val
; bit
++, val
>>= 1)
248 ret
= prog_bit(regs
, bank
, word
, bit
);
250 enable_efuse_prog_supply(0);
254 enable_efuse_prog_supply(0);
259 int fuse_override(u32 bank
, u32 word
, u32 val
)
261 struct fsl_iim
*regs
;
265 ret
= prepare_write(®s
, bank
, word
, val
, __func__
);
270 iim_write32(®s
->bank
[bank
].word
[word
], val
);
271 finish_access(regs
, &stat
, &err
);
274 puts("fsl_iim fuse_override(): Override protect error\n");