]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/misc/fsl_iim.c
2 * (C) Copyright 2009-2013 ADVANSEE
3 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
5 * Based on the mpc512x iim code:
6 * Copyright 2008 Silicon Turnkey Express, Inc.
7 * Martha Marx <mmarx@silicontkx.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
32 #ifndef CONFIG_MPC512X
33 #include <asm/arch/imx-regs.h>
36 /* FSL IIM-specific constants */
37 #define STAT_BUSY 0x80
38 #define STAT_PRGD 0x02
39 #define STAT_SNSD 0x01
41 #define STATM_PRGD_M 0x02
42 #define STATM_SNSD_M 0x01
50 #define ERR_PARITYE 0x02
52 #define EMASK_PRGE_M 0x80
53 #define EMASK_WPE_M 0x40
54 #define EMASK_OPE_M 0x20
55 #define EMASK_RPE_M 0x10
56 #define EMASK_WLRE_M 0x08
57 #define EMASK_SNSE_M 0x04
58 #define EMASK_PARITYE_M 0x02
61 #define FCTL_PRG_LENGTH_MASK 0x70
62 #define FCTL_ESNS_N 0x08
63 #define FCTL_ESNS_0 0x04
64 #define FCTL_ESNS_1 0x02
67 #define UA_A_BANK_MASK 0x38
68 #define UA_A_ROWH_MASK 0x07
70 #define LA_A_ROWL_MASK 0xf8
71 #define LA_A_BIT_MASK 0x07
73 #define PREV_PROD_REV_MASK 0xf8
74 #define PREV_PROD_VT_MASK 0x07
76 /* Select the correct accessors depending on endianness */
77 #if __BYTE_ORDER == __LITTLE_ENDIAN
78 #define iim_read32 in_le32
79 #define iim_write32 out_le32
80 #define iim_clrsetbits32 clrsetbits_le32
81 #define iim_clrbits32 clrbits_le32
82 #define iim_setbits32 setbits_le32
83 #elif __BYTE_ORDER == __BIG_ENDIAN
84 #define iim_read32 in_be32
85 #define iim_write32 out_be32
86 #define iim_clrsetbits32 clrsetbits_be32
87 #define iim_clrbits32 clrbits_be32
88 #define iim_setbits32 setbits_be32
90 #error Endianess is not defined: please fix to continue
93 /* IIM control registers */
112 static int prepare_access(struct fsl_iim
**regs
, u32 bank
, u32 word
, int assert,
115 *regs
= (struct fsl_iim
*)IIM_BASE_ADDR
;
117 if (bank
>= ARRAY_SIZE((*regs
)->bank
) ||
118 word
>= ARRAY_SIZE((*regs
)->bank
[0].word
) ||
120 printf("fsl_iim %s(): Invalid argument\n", caller
);
127 static void clear_status(struct fsl_iim
*regs
)
129 iim_setbits32(®s
->stat
, 0);
130 iim_setbits32(®s
->err
, 0);
133 static void finish_access(struct fsl_iim
*regs
, u32
*stat
, u32
*err
)
135 *stat
= iim_read32(®s
->stat
);
136 *err
= iim_read32(®s
->err
);
140 static int prepare_read(struct fsl_iim
**regs
, u32 bank
, u32 word
, u32
*val
,
145 ret
= prepare_access(regs
, bank
, word
, val
!= NULL
, caller
);
154 int fuse_read(u32 bank
, u32 word
, u32
*val
)
156 struct fsl_iim
*regs
;
160 ret
= prepare_read(®s
, bank
, word
, val
, __func__
);
164 *val
= iim_read32(®s
->bank
[bank
].word
[word
]);
165 finish_access(regs
, &stat
, &err
);
168 puts("fsl_iim fuse_read(): Read protect error\n");
175 static void direct_access(struct fsl_iim
*regs
, u32 bank
, u32 word
, u32 bit
,
176 u32 fctl
, u32
*stat
, u32
*err
)
178 iim_write32(®s
->ua
, bank
<< 3 | word
>> 5);
179 iim_write32(®s
->la
, (word
<< 3 | bit
) & 0xff);
180 if (fctl
== FCTL_PRG
)
181 iim_write32(®s
->prg_p
, 0xaa);
182 iim_setbits32(®s
->fctl
, fctl
);
183 while (iim_read32(®s
->stat
) & STAT_BUSY
)
185 finish_access(regs
, stat
, err
);
188 int fuse_sense(u32 bank
, u32 word
, u32
*val
)
190 struct fsl_iim
*regs
;
194 ret
= prepare_read(®s
, bank
, word
, val
, __func__
);
198 direct_access(regs
, bank
, word
, 0, FCTL_ESNS_N
, &stat
, &err
);
200 if (err
& ERR_SNSE
) {
201 puts("fsl_iim fuse_sense(): Explicit sense cycle error\n");
205 if (!(stat
& STAT_SNSD
)) {
206 puts("fsl_iim fuse_sense(): Explicit sense cycle did not complete\n");
210 *val
= iim_read32(®s
->sdat
);
214 static int prog_bit(struct fsl_iim
*regs
, u32 bank
, u32 word
, u32 bit
)
219 direct_access(regs
, bank
, word
, bit
, FCTL_PRG
, &stat
, &err
);
220 iim_write32(®s
->prg_p
, 0x00);
222 if (err
& ERR_PRGE
) {
223 puts("fsl_iim fuse_prog(): Program error\n");
228 puts("fsl_iim fuse_prog(): Write protect error\n");
232 if (!(stat
& STAT_PRGD
)) {
233 puts("fsl_iim fuse_prog(): Program did not complete\n");
240 static int prepare_write(struct fsl_iim
**regs
, u32 bank
, u32 word
, u32 val
,
243 return prepare_access(regs
, bank
, word
, !(val
& ~0xff), caller
);
246 int fuse_prog(u32 bank
, u32 word
, u32 val
)
248 struct fsl_iim
*regs
;
252 ret
= prepare_write(®s
, bank
, word
, val
, __func__
);
256 for (bit
= 0; val
; bit
++, val
>>= 1)
258 ret
= prog_bit(regs
, bank
, word
, bit
);
266 int fuse_override(u32 bank
, u32 word
, u32 val
)
268 struct fsl_iim
*regs
;
272 ret
= prepare_write(®s
, bank
, word
, val
, __func__
);
277 iim_write32(®s
->bank
[bank
].word
[word
], val
);
278 finish_access(regs
, &stat
, &err
);
281 puts("fsl_iim fuse_override(): Override protect error\n");