2 * This code was extracted from:
3 * git://github.com/gonzoua/u-boot-pi.git master
4 * and hence presumably (C) 2012 Oleksandr Tymoshenko
6 * Tweaks for U-Boot upstreaming
7 * (C) 2012 Stephen Warren
9 * Portions (e.g. read/write macros, concepts for back-to-back register write
10 * timing workarounds) obviously extracted from the Linux kernel at:
11 * https://github.com/raspberrypi/linux.git rpi-3.6.y
13 * The Linux kernel code has the following (c) and license, which is hence
14 * propagated to Oleksandr's tree and here:
16 * Support for SDHCI device on 2835
17 * Based on sdhci-bcm2708.c (c) 2010 Broadcom
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
34 * SDHCI platform device - Arasan SD controller in BCM2708
36 * Inspired by sdhci-pci.c, by Pierre Ossman
44 #include <asm/arch/msg.h>
45 #include <asm/arch/mbox.h>
46 #include <mach/sdhci.h>
47 #include <mach/timer.h>
49 /* 400KHz is max freq for card ID etc. Use that as min */
50 #define MIN_FREQ 400000
51 #define SDHCI_BUFFER 0x20
53 struct bcm2835_sdhci_plat
{
54 struct mmc_config cfg
;
58 struct bcm2835_sdhci_host
{
59 struct sdhci_host host
;
64 static inline struct bcm2835_sdhci_host
*to_bcm(struct sdhci_host
*host
)
66 return (struct bcm2835_sdhci_host
*)host
;
69 static inline void bcm2835_sdhci_raw_writel(struct sdhci_host
*host
, u32 val
,
72 struct bcm2835_sdhci_host
*bcm_host
= to_bcm(host
);
75 * The Arasan has a bugette whereby it may lose the content of
76 * successive writes to registers that are within two SD-card clock
77 * cycles of each other (a clock domain crossing problem).
78 * It seems, however, that the data register does not have this problem.
79 * (Which is just as well - otherwise we'd have to nobble the DMA engine
82 if (reg
!= SDHCI_BUFFER
) {
83 while (timer_get_us() - bcm_host
->last_write
<
84 bcm_host
->twoticks_delay
)
88 writel(val
, host
->ioaddr
+ reg
);
89 bcm_host
->last_write
= timer_get_us();
92 static inline u32
bcm2835_sdhci_raw_readl(struct sdhci_host
*host
, int reg
)
94 return readl(host
->ioaddr
+ reg
);
97 static void bcm2835_sdhci_writel(struct sdhci_host
*host
, u32 val
, int reg
)
99 bcm2835_sdhci_raw_writel(host
, val
, reg
);
102 static void bcm2835_sdhci_writew(struct sdhci_host
*host
, u16 val
, int reg
)
105 u32 oldval
= (reg
== SDHCI_COMMAND
) ? shadow
:
106 bcm2835_sdhci_raw_readl(host
, reg
& ~3);
107 u32 word_num
= (reg
>> 1) & 1;
108 u32 word_shift
= word_num
* 16;
109 u32 mask
= 0xffff << word_shift
;
110 u32 newval
= (oldval
& ~mask
) | (val
<< word_shift
);
112 if (reg
== SDHCI_TRANSFER_MODE
)
115 bcm2835_sdhci_raw_writel(host
, newval
, reg
& ~3);
118 static void bcm2835_sdhci_writeb(struct sdhci_host
*host
, u8 val
, int reg
)
120 u32 oldval
= bcm2835_sdhci_raw_readl(host
, reg
& ~3);
121 u32 byte_num
= reg
& 3;
122 u32 byte_shift
= byte_num
* 8;
123 u32 mask
= 0xff << byte_shift
;
124 u32 newval
= (oldval
& ~mask
) | (val
<< byte_shift
);
126 bcm2835_sdhci_raw_writel(host
, newval
, reg
& ~3);
129 static u32
bcm2835_sdhci_readl(struct sdhci_host
*host
, int reg
)
131 u32 val
= bcm2835_sdhci_raw_readl(host
, reg
);
136 static u16
bcm2835_sdhci_readw(struct sdhci_host
*host
, int reg
)
138 u32 val
= bcm2835_sdhci_raw_readl(host
, (reg
& ~3));
139 u32 word_num
= (reg
>> 1) & 1;
140 u32 word_shift
= word_num
* 16;
141 u32 word
= (val
>> word_shift
) & 0xffff;
146 static u8
bcm2835_sdhci_readb(struct sdhci_host
*host
, int reg
)
148 u32 val
= bcm2835_sdhci_raw_readl(host
, (reg
& ~3));
149 u32 byte_num
= reg
& 3;
150 u32 byte_shift
= byte_num
* 8;
151 u32 byte
= (val
>> byte_shift
) & 0xff;
156 static const struct sdhci_ops bcm2835_ops
= {
157 .write_l
= bcm2835_sdhci_writel
,
158 .write_w
= bcm2835_sdhci_writew
,
159 .write_b
= bcm2835_sdhci_writeb
,
160 .read_l
= bcm2835_sdhci_readl
,
161 .read_w
= bcm2835_sdhci_readw
,
162 .read_b
= bcm2835_sdhci_readb
,
165 static int bcm2835_sdhci_bind(struct udevice
*dev
)
167 struct bcm2835_sdhci_plat
*plat
= dev_get_platdata(dev
);
169 return sdhci_bind(dev
, &plat
->mmc
, &plat
->cfg
);
172 static int bcm2835_sdhci_probe(struct udevice
*dev
)
174 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
175 struct bcm2835_sdhci_plat
*plat
= dev_get_platdata(dev
);
176 struct bcm2835_sdhci_host
*priv
= dev_get_priv(dev
);
177 struct sdhci_host
*host
= &priv
->host
;
182 base
= dev_get_addr(dev
);
183 if (base
== FDT_ADDR_T_NONE
)
186 ret
= bcm2835_get_mmc_clock();
188 debug("%s: Failed to set MMC clock (err=%d)\n", __func__
, ret
);
194 * See the comments in bcm2835_sdhci_raw_writel().
196 * This should probably be dynamically calculated based on the actual
197 * frequency. However, this is the longest we'll have to wait, and
198 * doesn't seem to slow access down too much, so the added complexity
199 * doesn't seem worth it for now.
201 * 1/MIN_FREQ is (max) time per tick of eMMC clock.
202 * 2/MIN_FREQ is time for two ticks.
203 * Multiply by 1000000 to get uS per two ticks.
204 * +1 for hack rounding.
206 priv
->twoticks_delay
= ((2 * 1000000) / MIN_FREQ
) + 1;
207 priv
->last_write
= 0;
209 host
->name
= dev
->name
;
210 host
->ioaddr
= (void *)base
;
211 host
->quirks
= SDHCI_QUIRK_BROKEN_VOLTAGE
| SDHCI_QUIRK_BROKEN_R1B
|
212 SDHCI_QUIRK_WAIT_SEND_CMD
| SDHCI_QUIRK_NO_HISPD_BIT
;
213 host
->max_clk
= emmc_freq
;
214 host
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
215 host
->ops
= &bcm2835_ops
;
217 ret
= sdhci_setup_cfg(&plat
->cfg
, host
, emmc_freq
, MIN_FREQ
);
219 debug("%s: Failed to setup SDHCI (err=%d)\n", __func__
, ret
);
223 upriv
->mmc
= &plat
->mmc
;
224 host
->mmc
= &plat
->mmc
;
225 host
->mmc
->priv
= host
;
227 return sdhci_probe(dev
);
230 static const struct udevice_id bcm2835_sdhci_match
[] = {
231 { .compatible
= "brcm,bcm2835-sdhci" },
235 U_BOOT_DRIVER(sdhci_cdns
) = {
236 .name
= "sdhci-bcm2835",
238 .of_match
= bcm2835_sdhci_match
,
239 .bind
= bcm2835_sdhci_bind
,
240 .probe
= bcm2835_sdhci_probe
,
241 .priv_auto_alloc_size
= sizeof(struct bcm2835_sdhci_host
),
242 .platdata_auto_alloc_size
= sizeof(struct bcm2835_sdhci_plat
),