drivers/mmc/bfin_sdh.c

   1 /*
   2  * Driver for Blackfin on-chip SDH controller
   3  *
   4  * Copyright (c) 2008-2009 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <part.h>
  12 #include <mmc.h>
  13
  14 #include <asm/io.h>
  15 #include <asm/errno.h>
  16 #include <asm/byteorder.h>
  17 #include <asm/blackfin.h>
  18 #include <asm/portmux.h>
  19 #include <asm/mach-common/bits/sdh.h>
  20 #include <asm/mach-common/bits/dma.h>
  21
  22 #if defined(__ADSPBF51x__)
  23 # define bfin_read_SDH_PWR_CTL          bfin_read_RSI_PWR_CONTROL
  24 # define bfin_write_SDH_PWR_CTL         bfin_write_RSI_PWR_CONTROL
  25 # define bfin_read_SDH_CLK_CTL          bfin_read_RSI_CLK_CONTROL
  26 # define bfin_write_SDH_CLK_CTL         bfin_write_RSI_CLK_CONTROL
  27 # define bfin_write_SDH_ARGUMENT        bfin_write_RSI_ARGUMENT
  28 # define bfin_write_SDH_COMMAND         bfin_write_RSI_COMMAND
  29 # define bfin_read_SDH_RESPONSE0        bfin_read_RSI_RESPONSE0
  30 # define bfin_read_SDH_RESPONSE1        bfin_read_RSI_RESPONSE1
  31 # define bfin_read_SDH_RESPONSE2        bfin_read_RSI_RESPONSE2
  32 # define bfin_read_SDH_RESPONSE3        bfin_read_RSI_RESPONSE3
  33 # define bfin_write_SDH_DATA_TIMER      bfin_write_RSI_DATA_TIMER
  34 # define bfin_write_SDH_DATA_LGTH       bfin_write_RSI_DATA_LGTH
  35 # define bfin_read_SDH_DATA_CTL         bfin_read_RSI_DATA_CONTROL
  36 # define bfin_write_SDH_DATA_CTL        bfin_write_RSI_DATA_CONTROL
  37 # define bfin_read_SDH_STATUS           bfin_read_RSI_STATUS
  38 # define bfin_write_SDH_STATUS_CLR      bfin_write_RSI_STATUSCL
  39 # define bfin_read_SDH_CFG              bfin_read_RSI_CONFIG
  40 # define bfin_write_SDH_CFG             bfin_write_RSI_CONFIG
  41 # define bfin_write_DMA_START_ADDR      bfin_write_DMA4_START_ADDR
  42 # define bfin_write_DMA_X_COUNT         bfin_write_DMA4_X_COUNT
  43 # define bfin_write_DMA_X_MODIFY        bfin_write_DMA4_X_MODIFY
  44 # define bfin_write_DMA_CONFIG          bfin_write_DMA4_CONFIG
  45 # define PORTMUX_PINS \
  46         { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
  47 #elif defined(__ADSPBF54x__)
  48 # define bfin_write_DMA_START_ADDR      bfin_write_DMA22_START_ADDR
  49 # define bfin_write_DMA_X_COUNT         bfin_write_DMA22_X_COUNT
  50 # define bfin_write_DMA_X_MODIFY        bfin_write_DMA22_X_MODIFY
  51 # define bfin_write_DMA_CONFIG          bfin_write_DMA22_CONFIG
  52 # define PORTMUX_PINS \
  53         { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
  54 #else
  55 # error no support for this proc yet
  56 #endif
  57
  58 static int
  59 sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
  60 {
  61         unsigned int sdh_cmd;
  62         unsigned int status;
  63         int cmd = mmc_cmd->cmdidx;
  64         int flags = mmc_cmd->resp_type;
  65         int arg = mmc_cmd->cmdarg;
  66         int ret = 0;
  67         sdh_cmd = 0;
  68
  69         sdh_cmd |= cmd;
  70
  71         if (flags & MMC_RSP_PRESENT)
  72                 sdh_cmd |= CMD_RSP;
  73
  74         if (flags & MMC_RSP_136)
  75                 sdh_cmd |= CMD_L_RSP;
  76
  77         bfin_write_SDH_ARGUMENT(arg);
  78         bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
  79
  80         /* wait for a while */
  81         do {
  82                 udelay(1);
  83                 status = bfin_read_SDH_STATUS();
  84         } while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
  85                 CMD_CRC_FAIL)));
  86
  87         if (flags & MMC_RSP_PRESENT) {
  88                 mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
  89                 if (flags & MMC_RSP_136) {
  90                         mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
  91                         mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
  92                         mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
  93                 }
  94         }
  95
  96         if (status & CMD_TIME_OUT)
  97                 ret |= TIMEOUT;
  98         else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
  99                 ret |= COMM_ERR;
 100
 101         bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
 102                                 CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
 103         return ret;
 104 }
 105
 106 /* set data for single block transfer */
 107 static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
 108 {
 109         u16 data_ctl = 0;
 110         u16 dma_cfg = 0;
 111         int ret = 0;
 112
 113         /* Don't support write yet. */
 114         if (data->flags & MMC_DATA_WRITE)
 115                 return UNUSABLE_ERR;
 116         data_ctl |= ((ffs(data->blocksize) - 1) << 4);
 117         data_ctl |= DTX_DIR;
 118         bfin_write_SDH_DATA_CTL(data_ctl);
 119         dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;
 120
 121         bfin_write_SDH_DATA_TIMER(0xFFFF);
 122
 123         blackfin_dcache_flush_invalidate_range(data->dest,
 124                         data->dest + data->blocksize);
 125         /* configure DMA */
 126         bfin_write_DMA_START_ADDR(data->dest);
 127         bfin_write_DMA_X_COUNT(data->blocksize / 4);
 128         bfin_write_DMA_X_MODIFY(4);
 129         bfin_write_DMA_CONFIG(dma_cfg);
 130         bfin_write_SDH_DATA_LGTH(data->blocksize);
 131         /* kick off transfer */
 132         bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
 133
 134         return ret;
 135 }
 136
 137
 138 static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
 139                 struct mmc_data *data)
 140 {
 141         u32 status;
 142         int ret = 0;
 143
 144         ret = sdh_send_cmd(mmc, cmd);
 145         if (ret) {
 146                 printf("sending CMD%d failed\n", cmd->cmdidx);
 147                 return ret;
 148         }
 149         if (data) {
 150                 ret = sdh_setup_data(mmc, data);
 151                 do {
 152                         udelay(1);
 153                         status = bfin_read_SDH_STATUS();
 154                 } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));
 155
 156                 if (status & DAT_TIME_OUT) {
 157                         bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
 158                         ret |= TIMEOUT;
 159                 } else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
 160                         bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
 161                         ret |= COMM_ERR;
 162                 } else
 163                         bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
 164
 165                 if (ret) {
 166                         printf("tranfering data failed\n");
 167                         return ret;
 168                 }
 169         }
 170         return 0;
 171 }
 172
 173 static void sdh_set_clk(unsigned long clk)
 174 {
 175         unsigned long sys_clk;
 176         unsigned long clk_div;
 177         u16 clk_ctl = 0;
 178
 179         clk_ctl = bfin_read_SDH_CLK_CTL();
 180         if (clk) {
 181                 /* setting SD_CLK */
 182                 sys_clk = get_sclk();
 183                 bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
 184                 if (sys_clk % (2 * clk) == 0)
 185                         clk_div = sys_clk / (2 * clk) - 1;
 186                 else
 187                         clk_div = sys_clk / (2 * clk);
 188
 189                 if (clk_div > 0xff)
 190                         clk_div = 0xff;
 191                 clk_ctl |= (clk_div & 0xff);
 192                 clk_ctl |= CLK_E;
 193                 bfin_write_SDH_CLK_CTL(clk_ctl);
 194         } else
 195                 bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
 196 }
 197
 198 static void bfin_sdh_set_ios(struct mmc *mmc)
 199 {
 200         u16 cfg = 0;
 201         u16 clk_ctl = 0;
 202
 203         if (mmc->bus_width == 4) {
 204                 cfg = bfin_read_SDH_CFG();
 205                 cfg &= ~0x80;
 206                 cfg |= 0x40;
 207                 bfin_write_SDH_CFG(cfg);
 208                 clk_ctl |= WIDE_BUS;
 209         }
 210         bfin_write_SDH_CLK_CTL(clk_ctl);
 211         sdh_set_clk(mmc->clock);
 212 }
 213
 214 static int bfin_sdh_init(struct mmc *mmc)
 215 {
 216         const unsigned short pins[] = PORTMUX_PINS;
 217         u16 pwr_ctl = 0;
 218
 219         /* Initialize sdh controller */
 220         peripheral_request_list(pins, "bfin_sdh");
 221 #if defined(__ADSPBF54x__)
 222         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
 223 #endif
 224         bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
 225         /* Disable card detect pin */
 226         bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
 227
 228         pwr_ctl |= ROD_CTL;
 229         pwr_ctl |= PWR_ON;
 230         bfin_write_SDH_PWR_CTL(pwr_ctl);
 231         return 0;
 232 }
 233
 234
 235 int bfin_mmc_init(bd_t *bis)
 236 {
 237         struct mmc *mmc = NULL;
 238
 239         mmc = malloc(sizeof(struct mmc));
 240
 241         if (!mmc)
 242                 return -ENOMEM;
 243         sprintf(mmc->name, "Blackfin SDH");
 244         mmc->send_cmd = bfin_sdh_request;
 245         mmc->set_ios = bfin_sdh_set_ios;
 246         mmc->init = bfin_sdh_init;
 247         mmc->host_caps = MMC_MODE_4BIT;
 248
 249         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 250         mmc->f_max = get_sclk();
 251         mmc->f_min = mmc->f_max >> 9;
 252         mmc->block_dev.part_type = PART_TYPE_DOS;
 253
 254         mmc_register(mmc);
 255
 256         return 0;
 257 }