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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/mmc/bfin_sdh.c
5670939e1e65dd6a1ca266d06c9948b3b2cb45f3
2 * Driver for Blackfin on-chip SDH controller
4 * Copyright (c) 2008-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
15 #include <asm/errno.h>
16 #include <asm/byteorder.h>
17 #include <asm/blackfin.h>
18 #include <asm/portmux.h>
19 #include <asm/mach-common/bits/sdh.h>
20 #include <asm/mach-common/bits/dma.h>
22 #if defined(__ADSPBF50x__) || defined(__ADSPBF51x__)
23 # define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
24 # define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
25 # define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
26 # define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
27 # define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
28 # define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
29 # define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
30 # define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
31 # define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
32 # define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
33 # define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
34 # define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
35 # define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL
36 # define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL
37 # define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
38 # define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
39 # define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
40 # define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
41 # define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
42 # define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
43 # define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
44 # define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
45 # define PORTMUX_PINS \
46 { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
47 #elif defined(__ADSPBF54x__)
48 # define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
49 # define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
50 # define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
51 # define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
52 # define PORTMUX_PINS \
53 { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
55 # error no support for this proc yet
59 sdh_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*mmc_cmd
)
61 unsigned int status
, timeout
;
62 int cmd
= mmc_cmd
->cmdidx
;
63 int flags
= mmc_cmd
->resp_type
;
64 int arg
= mmc_cmd
->cmdarg
;
68 sdh_cmd
= cmd
| CMD_E
;
69 if (flags
& MMC_RSP_PRESENT
)
71 if (flags
& MMC_RSP_136
)
74 bfin_write_SDH_ARGUMENT(arg
);
75 bfin_write_SDH_COMMAND(sdh_cmd
);
77 /* wait for a while */
80 if (++timeout
> 1000000) {
81 status
= CMD_TIME_OUT
;
85 status
= bfin_read_SDH_STATUS();
86 } while (!(status
& (CMD_SENT
| CMD_RESP_END
| CMD_TIME_OUT
|
89 if (flags
& MMC_RSP_PRESENT
) {
90 mmc_cmd
->response
[0] = bfin_read_SDH_RESPONSE0();
91 if (flags
& MMC_RSP_136
) {
92 mmc_cmd
->response
[1] = bfin_read_SDH_RESPONSE1();
93 mmc_cmd
->response
[2] = bfin_read_SDH_RESPONSE2();
94 mmc_cmd
->response
[3] = bfin_read_SDH_RESPONSE3();
98 if (status
& CMD_TIME_OUT
)
100 else if (status
& CMD_CRC_FAIL
&& flags
& MMC_RSP_CRC
)
105 bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT
| CMD_RESP_END_STAT
|
106 CMD_TIMEOUT_STAT
| CMD_CRC_FAIL_STAT
);
111 /* set data for single block transfer */
112 static int sdh_setup_data(struct mmc
*mmc
, struct mmc_data
*data
)
118 /* Don't support write yet. */
119 if (data
->flags
& MMC_DATA_WRITE
)
121 data_ctl
|= ((ffs(data
->blocksize
) - 1) << 4);
123 bfin_write_SDH_DATA_CTL(data_ctl
);
124 dma_cfg
= WDSIZE_32
| RESTART
| WNR
| DMAEN
;
126 bfin_write_SDH_DATA_TIMER(0xFFFF);
128 blackfin_dcache_flush_invalidate_range(data
->dest
,
129 data
->dest
+ data
->blocksize
);
131 bfin_write_DMA_START_ADDR(data
->dest
);
132 bfin_write_DMA_X_COUNT(data
->blocksize
/ 4);
133 bfin_write_DMA_X_MODIFY(4);
134 bfin_write_DMA_CONFIG(dma_cfg
);
135 bfin_write_SDH_DATA_LGTH(data
->blocksize
);
136 /* kick off transfer */
137 bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E
| DTX_E
);
143 static int bfin_sdh_request(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
144 struct mmc_data
*data
)
149 ret
= sdh_send_cmd(mmc
, cmd
);
151 printf("sending CMD%d failed\n", cmd
->cmdidx
);
155 ret
= sdh_setup_data(mmc
, data
);
158 status
= bfin_read_SDH_STATUS();
159 } while (!(status
& (DAT_BLK_END
| DAT_END
| DAT_TIME_OUT
| DAT_CRC_FAIL
| RX_OVERRUN
)));
161 if (status
& DAT_TIME_OUT
) {
162 bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT
);
164 } else if (status
& (DAT_CRC_FAIL
| RX_OVERRUN
)) {
165 bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT
| RX_OVERRUN_STAT
);
168 bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT
| DAT_END_STAT
);
171 printf("tranfering data failed\n");
178 static void sdh_set_clk(unsigned long clk
)
180 unsigned long sys_clk
;
181 unsigned long clk_div
;
184 clk_ctl
= bfin_read_SDH_CLK_CTL();
187 sys_clk
= get_sclk();
188 bfin_write_SDH_CLK_CTL(clk_ctl
& ~CLK_E
);
189 if (sys_clk
% (2 * clk
) == 0)
190 clk_div
= sys_clk
/ (2 * clk
) - 1;
192 clk_div
= sys_clk
/ (2 * clk
);
196 clk_ctl
|= (clk_div
& 0xff);
198 bfin_write_SDH_CLK_CTL(clk_ctl
);
200 bfin_write_SDH_CLK_CTL(clk_ctl
& ~CLK_E
);
203 static void bfin_sdh_set_ios(struct mmc
*mmc
)
208 if (mmc
->bus_width
== 4) {
209 cfg
= bfin_read_SDH_CFG();
212 bfin_write_SDH_CFG(cfg
);
215 bfin_write_SDH_CLK_CTL(clk_ctl
);
216 sdh_set_clk(mmc
->clock
);
219 static int bfin_sdh_init(struct mmc
*mmc
)
221 const unsigned short pins
[] = PORTMUX_PINS
;
224 /* Initialize sdh controller */
225 peripheral_request_list(pins
, "bfin_sdh");
226 #if defined(__ADSPBF54x__)
227 bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
229 bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN
);
230 /* Disable card detect pin */
231 bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
235 bfin_write_SDH_PWR_CTL(pwr_ctl
);
240 int bfin_mmc_init(bd_t
*bis
)
242 struct mmc
*mmc
= NULL
;
244 mmc
= malloc(sizeof(struct mmc
));
248 sprintf(mmc
->name
, "Blackfin SDH");
249 mmc
->send_cmd
= bfin_sdh_request
;
250 mmc
->set_ios
= bfin_sdh_set_ios
;
251 mmc
->init
= bfin_sdh_init
;
252 mmc
->host_caps
= MMC_MODE_4BIT
;
254 mmc
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
255 mmc
->f_max
= get_sclk();
256 mmc
->f_min
= mmc
->f_max
>> 9;
257 mmc
->block_dev
.part_type
= PART_TYPE_DOS
;