2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm-generic/errno.h>
15 #define PAGE_SIZE 4096
17 static int dwmci_wait_reset(struct dwmci_host
*host
, u32 value
)
19 unsigned long timeout
= 1000;
22 dwmci_writel(host
, DWMCI_CTRL
, value
);
25 ctrl
= dwmci_readl(host
, DWMCI_CTRL
);
26 if (!(ctrl
& DWMCI_RESET_ALL
))
32 static void dwmci_set_idma_desc(struct dwmci_idmac
*idmac
,
33 u32 desc0
, u32 desc1
, u32 desc2
)
35 struct dwmci_idmac
*desc
= idmac
;
40 desc
->next_addr
= (unsigned int)desc
+ sizeof(struct dwmci_idmac
);
43 static void dwmci_prepare_data(struct dwmci_host
*host
,
44 struct mmc_data
*data
, struct dwmci_idmac
*cur_idmac
)
47 unsigned int i
= 0, flags
, cnt
, blk_cnt
;
48 ulong data_start
, data_end
, start_addr
;
51 blk_cnt
= data
->blocks
;
53 dwmci_wait_reset(host
, DWMCI_CTRL_FIFO_RESET
);
55 data_start
= (ulong
)cur_idmac
;
56 dwmci_writel(host
, DWMCI_DBADDR
, (unsigned int)cur_idmac
);
58 if (data
->flags
== MMC_DATA_READ
)
59 start_addr
= (unsigned int)data
->dest
;
61 start_addr
= (unsigned int)data
->src
;
64 flags
= DWMCI_IDMAC_OWN
| DWMCI_IDMAC_CH
;
65 flags
|= (i
== 0) ? DWMCI_IDMAC_FS
: 0;
67 flags
|= DWMCI_IDMAC_LD
;
68 cnt
= data
->blocksize
* blk_cnt
;
70 cnt
= data
->blocksize
* 8;
72 dwmci_set_idma_desc(cur_idmac
, flags
, cnt
,
73 start_addr
+ (i
* PAGE_SIZE
));
82 data_end
= (ulong
)cur_idmac
;
83 flush_dcache_range(data_start
, data_end
+ ARCH_DMA_MINALIGN
);
85 ctrl
= dwmci_readl(host
, DWMCI_CTRL
);
86 ctrl
|= DWMCI_IDMAC_EN
| DWMCI_DMA_EN
;
87 dwmci_writel(host
, DWMCI_CTRL
, ctrl
);
89 ctrl
= dwmci_readl(host
, DWMCI_BMOD
);
90 ctrl
|= DWMCI_BMOD_IDMAC_FB
| DWMCI_BMOD_IDMAC_EN
;
91 dwmci_writel(host
, DWMCI_BMOD
, ctrl
);
93 dwmci_writel(host
, DWMCI_BLKSIZ
, data
->blocksize
);
94 dwmci_writel(host
, DWMCI_BYTCNT
, data
->blocksize
* data
->blocks
);
97 static int dwmci_set_transfer_mode(struct dwmci_host
*host
,
98 struct mmc_data
*data
)
102 mode
= DWMCI_CMD_DATA_EXP
;
103 if (data
->flags
& MMC_DATA_WRITE
)
104 mode
|= DWMCI_CMD_RW
;
109 static int dwmci_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
110 struct mmc_data
*data
)
112 struct dwmci_host
*host
= (struct dwmci_host
*)mmc
->priv
;
113 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac
, cur_idmac
,
114 data
? DIV_ROUND_UP(data
->blocks
, 8) : 0);
116 unsigned int timeout
= 100000;
119 ulong start
= get_timer(0);
121 while (dwmci_readl(host
, DWMCI_STATUS
) & DWMCI_BUSY
) {
122 if (get_timer(start
) > timeout
) {
123 printf("Timeout on data busy\n");
128 dwmci_writel(host
, DWMCI_RINTSTS
, DWMCI_INTMSK_ALL
);
131 dwmci_prepare_data(host
, data
, cur_idmac
);
133 dwmci_writel(host
, DWMCI_CMDARG
, cmd
->cmdarg
);
136 flags
= dwmci_set_transfer_mode(host
, data
);
138 if ((cmd
->resp_type
& MMC_RSP_136
) && (cmd
->resp_type
& MMC_RSP_BUSY
))
141 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
142 flags
|= DWMCI_CMD_ABORT_STOP
;
144 flags
|= DWMCI_CMD_PRV_DAT_WAIT
;
146 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
147 flags
|= DWMCI_CMD_RESP_EXP
;
148 if (cmd
->resp_type
& MMC_RSP_136
)
149 flags
|= DWMCI_CMD_RESP_LENGTH
;
152 if (cmd
->resp_type
& MMC_RSP_CRC
)
153 flags
|= DWMCI_CMD_CHECK_CRC
;
155 flags
|= (cmd
->cmdidx
| DWMCI_CMD_START
| DWMCI_CMD_USE_HOLD_REG
);
157 debug("Sending CMD%d\n",cmd
->cmdidx
);
159 dwmci_writel(host
, DWMCI_CMD
, flags
);
161 for (i
= 0; i
< retry
; i
++) {
162 mask
= dwmci_readl(host
, DWMCI_RINTSTS
);
163 if (mask
& DWMCI_INTMSK_CDONE
) {
165 dwmci_writel(host
, DWMCI_RINTSTS
, mask
);
173 if (mask
& DWMCI_INTMSK_RTO
) {
174 debug("Response Timeout..\n");
176 } else if (mask
& DWMCI_INTMSK_RE
) {
177 debug("Response Error..\n");
182 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
183 if (cmd
->resp_type
& MMC_RSP_136
) {
184 cmd
->response
[0] = dwmci_readl(host
, DWMCI_RESP3
);
185 cmd
->response
[1] = dwmci_readl(host
, DWMCI_RESP2
);
186 cmd
->response
[2] = dwmci_readl(host
, DWMCI_RESP1
);
187 cmd
->response
[3] = dwmci_readl(host
, DWMCI_RESP0
);
189 cmd
->response
[0] = dwmci_readl(host
, DWMCI_RESP0
);
195 mask
= dwmci_readl(host
, DWMCI_RINTSTS
);
196 if (mask
& (DWMCI_DATA_ERR
| DWMCI_DATA_TOUT
)) {
197 debug("DATA ERROR!\n");
200 } while (!(mask
& DWMCI_INTMSK_DTO
));
202 dwmci_writel(host
, DWMCI_RINTSTS
, mask
);
204 ctrl
= dwmci_readl(host
, DWMCI_CTRL
);
205 ctrl
&= ~(DWMCI_DMA_EN
);
206 dwmci_writel(host
, DWMCI_CTRL
, ctrl
);
214 static int dwmci_setup_bus(struct dwmci_host
*host
, u32 freq
)
220 if ((freq
== host
->clock
) || (freq
== 0))
223 * If host->mmc_clk didn't define,
224 * then assume that host->bus_hz is source clock value.
225 * host->bus_hz should be set from user.
228 sclk
= host
->mmc_clk(host
->dev_index
);
229 else if (host
->bus_hz
)
232 printf("Didn't get source clock value..\n");
236 div
= DIV_ROUND_UP(sclk
, 2 * freq
);
238 dwmci_writel(host
, DWMCI_CLKENA
, 0);
239 dwmci_writel(host
, DWMCI_CLKSRC
, 0);
241 dwmci_writel(host
, DWMCI_CLKDIV
, div
);
242 dwmci_writel(host
, DWMCI_CMD
, DWMCI_CMD_PRV_DAT_WAIT
|
243 DWMCI_CMD_UPD_CLK
| DWMCI_CMD_START
);
246 status
= dwmci_readl(host
, DWMCI_CMD
);
248 printf("TIMEOUT error!!\n");
251 } while (status
& DWMCI_CMD_START
);
253 dwmci_writel(host
, DWMCI_CLKENA
, DWMCI_CLKEN_ENABLE
|
254 DWMCI_CLKEN_LOW_PWR
);
256 dwmci_writel(host
, DWMCI_CMD
, DWMCI_CMD_PRV_DAT_WAIT
|
257 DWMCI_CMD_UPD_CLK
| DWMCI_CMD_START
);
261 status
= dwmci_readl(host
, DWMCI_CMD
);
263 printf("TIMEOUT error!!\n");
266 } while (status
& DWMCI_CMD_START
);
273 static void dwmci_set_ios(struct mmc
*mmc
)
275 struct dwmci_host
*host
= (struct dwmci_host
*)mmc
->priv
;
278 debug("Buswidth = %d, clock: %d\n",mmc
->bus_width
, mmc
->clock
);
280 dwmci_setup_bus(host
, mmc
->clock
);
281 switch (mmc
->bus_width
) {
283 ctype
= DWMCI_CTYPE_8BIT
;
286 ctype
= DWMCI_CTYPE_4BIT
;
289 ctype
= DWMCI_CTYPE_1BIT
;
293 dwmci_writel(host
, DWMCI_CTYPE
, ctype
);
299 static int dwmci_init(struct mmc
*mmc
)
301 struct dwmci_host
*host
= (struct dwmci_host
*)mmc
->priv
;
304 dwmci_writel(host
, DWMCI_PWREN
, 1);
306 if (!dwmci_wait_reset(host
, DWMCI_RESET_ALL
)) {
307 debug("%s[%d] Fail-reset!!\n",__func__
,__LINE__
);
311 /* Enumerate at 400KHz */
312 dwmci_setup_bus(host
, mmc
->f_min
);
314 dwmci_writel(host
, DWMCI_RINTSTS
, 0xFFFFFFFF);
315 dwmci_writel(host
, DWMCI_INTMASK
, 0);
317 dwmci_writel(host
, DWMCI_TMOUT
, 0xFFFFFFFF);
319 dwmci_writel(host
, DWMCI_IDINTEN
, 0);
320 dwmci_writel(host
, DWMCI_BMOD
, 1);
322 if (!host
->fifoth_val
) {
323 fifo_size
= dwmci_readl(host
, DWMCI_FIFOTH
);
324 fifo_size
= ((fifo_size
& RX_WMARK_MASK
) >> RX_WMARK_SHIFT
) + 1;
325 host
->fifoth_val
= MSIZE(0x2) | RX_WMARK(fifo_size
/ 2 - 1) |
326 TX_WMARK(fifo_size
/ 2);
328 dwmci_writel(host
, DWMCI_FIFOTH
, host
->fifoth_val
);
330 dwmci_writel(host
, DWMCI_CLKENA
, 0);
331 dwmci_writel(host
, DWMCI_CLKSRC
, 0);
336 int add_dwmci(struct dwmci_host
*host
, u32 max_clk
, u32 min_clk
)
341 mmc
= malloc(sizeof(struct mmc
));
343 printf("mmc malloc fail!\n");
350 sprintf(mmc
->name
, "%s", host
->name
);
351 mmc
->send_cmd
= dwmci_send_cmd
;
352 mmc
->set_ios
= dwmci_set_ios
;
353 mmc
->init
= dwmci_init
;
354 mmc
->f_min
= min_clk
;
355 mmc
->f_max
= max_clk
;
357 mmc
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
359 mmc
->host_caps
= host
->caps
;
361 if (host
->buswidth
== 8) {
362 mmc
->host_caps
|= MMC_MODE_8BIT
;
363 mmc
->host_caps
&= ~MMC_MODE_4BIT
;
365 mmc
->host_caps
|= MMC_MODE_4BIT
;
366 mmc
->host_caps
&= ~MMC_MODE_8BIT
;
368 mmc
->host_caps
|= MMC_MODE_HS
| MMC_MODE_HS_52MHz
| MMC_MODE_HC
;
370 err
= mmc_register(mmc
);