drivers/mmc/exynos_dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2012 SAMSUNG Electronics
   4  * Jaehoon Chung <jh80.chung@samsung.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dwmmc.h>
   9 #include <fdtdec.h>
  10 #include <asm/global_data.h>
  11 #include <linux/libfdt.h>
  12 #include <malloc.h>
  13 #include <errno.h>
  14 #include <asm/arch/dwmmc.h>
  15 #include <asm/arch/clk.h>
  16 #include <asm/arch/pinmux.h>
  17 #include <asm/arch/power.h>
  18 #include <asm/gpio.h>
  19 #include <linux/printk.h>
  20
  21 #define DWMMC_MAX_CH_NUM                4
  22 #define DWMMC_MAX_FREQ                  52000000
  23 #define DWMMC_MIN_FREQ                  400000
  24 #define DWMMC_MMC0_SDR_TIMING_VAL       0x03030001
  25 #define DWMMC_MMC2_SDR_TIMING_VAL       0x03020001
  26
  27 #ifdef CONFIG_DM_MMC
  28 #include <dm.h>
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 struct exynos_mmc_plat {
  32         struct mmc_config cfg;
  33         struct mmc mmc;
  34 };
  35 #endif
  36
  37 /* Exynos implmentation specific drver private data */
  38 struct dwmci_exynos_priv_data {
  39 #ifdef CONFIG_DM_MMC
  40         struct dwmci_host host;
  41 #endif
  42         u32 sdr_timing;
  43 };
  44
  45 /*
  46  * Function used as callback function to initialise the
  47  * CLKSEL register for every mmc channel.
  48  */
  49 static int exynos_dwmci_clksel(struct dwmci_host *host)
  50 {
  51 #ifdef CONFIG_DM_MMC
  52         struct dwmci_exynos_priv_data *priv =
  53                 container_of(host, struct dwmci_exynos_priv_data, host);
  54 #else
  55         struct dwmci_exynos_priv_data *priv = host->priv;
  56 #endif
  57         dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
  58
  59         return 0;
  60 }
  61
  62 unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
  63 {
  64         unsigned long sclk;
  65         int8_t clk_div;
  66
  67         /*
  68          * Since SDCLKIN is divided inside controller by the DIVRATIO
  69          * value set in the CLKSEL register, we need to use the same output
  70          * clock value to calculate the CLKDIV value.
  71          * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
  72          */
  73         clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
  74                         & DWMCI_DIVRATIO_MASK) + 1;
  75         sclk = get_mmc_clk(host->dev_index);
  76
  77         /*
  78          * Assume to know divider value.
  79          * When clock unit is broken, need to set "host->div"
  80          */
  81         return sclk / clk_div / (host->div + 1);
  82 }
  83
  84 static void exynos_dwmci_board_init(struct dwmci_host *host)
  85 {
  86         struct dwmci_exynos_priv_data *priv = host->priv;
  87
  88         if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
  89                 dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
  90                 dwmci_writel(host, EMMCP_SEND0, 0);
  91                 dwmci_writel(host, EMMCP_CTRL0,
  92                              MPSCTRL_SECURE_READ_BIT |
  93                              MPSCTRL_SECURE_WRITE_BIT |
  94                              MPSCTRL_NON_SECURE_READ_BIT |
  95                              MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
  96         }
  97
  98         /* Set to timing value at initial time */
  99         if (priv->sdr_timing)
 100                 exynos_dwmci_clksel(host);
 101 }
 102
 103 static int exynos_dwmci_core_init(struct dwmci_host *host)
 104 {
 105         unsigned int div;
 106         unsigned long freq, sclk;
 107
 108         if (host->bus_hz)
 109                 freq = host->bus_hz;
 110         else
 111                 freq = DWMMC_MAX_FREQ;
 112
 113         /* request mmc clock vlaue of 52MHz.  */
 114         sclk = get_mmc_clk(host->dev_index);
 115         div = DIV_ROUND_UP(sclk, freq);
 116         /* set the clock divisor for mmc */
 117         set_mmc_clk(host->dev_index, div);
 118
 119         host->name = "EXYNOS DWMMC";
 120 #ifdef CONFIG_EXYNOS5420
 121         host->quirks = DWMCI_QUIRK_DISABLE_SMU;
 122 #endif
 123         host->board_init = exynos_dwmci_board_init;
 124
 125         host->caps = MMC_MODE_DDR_52MHz;
 126         host->clksel = exynos_dwmci_clksel;
 127         host->get_mmc_clk = exynos_dwmci_get_clk;
 128
 129 #ifndef CONFIG_DM_MMC
 130         /* Add the mmc channel to be registered with mmc core */
 131         if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
 132                 printf("DWMMC%d registration failed\n", host->dev_index);
 133                 return -1;
 134         }
 135 #endif
 136
 137         return 0;
 138 }
 139
 140 static int do_dwmci_init(struct dwmci_host *host)
 141 {
 142         int flag, err;
 143
 144         flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
 145         err = exynos_pinmux_config(host->dev_id, flag);
 146         if (err) {
 147                 printf("DWMMC%d not configure\n", host->dev_index);
 148                 return err;
 149         }
 150
 151         return exynos_dwmci_core_init(host);
 152 }
 153
 154 static int exynos_dwmci_get_config(const void *blob, int node,
 155                                    struct dwmci_host *host,
 156                                    struct dwmci_exynos_priv_data *priv)
 157 {
 158         int err = 0;
 159         u32 base, timing[3];
 160
 161         /* Extract device id for each mmc channel */
 162         host->dev_id = pinmux_decode_periph_id(blob, node);
 163
 164         host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
 165         if (host->dev_index == host->dev_id)
 166                 host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
 167
 168         if (host->dev_index > 4) {
 169                 printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
 170                 return -EINVAL;
 171         }
 172
 173         /* Get the bus width from the device node (Default is 4bit buswidth) */
 174         host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4);
 175
 176         /* Set the base address from the device node */
 177         base = fdtdec_get_addr(blob, node, "reg");
 178         if (!base) {
 179                 printf("DWMMC%d: Can't get base address\n", host->dev_index);
 180                 return -EINVAL;
 181         }
 182         host->ioaddr = (void *)base;
 183
 184         /* Extract the timing info from the node */
 185         err =  fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
 186         if (err) {
 187                 printf("DWMMC%d: Can't get sdr-timings for devider\n",
 188                                 host->dev_index);
 189                 return -EINVAL;
 190         }
 191
 192         priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
 193                         DWMCI_SET_DRV_CLK(timing[1]) |
 194                         DWMCI_SET_DIV_RATIO(timing[2]));
 195
 196         /* sdr_timing didn't assigned anything, use the default value */
 197         if (!priv->sdr_timing) {
 198                 if (host->dev_index == 0)
 199                         priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
 200                 else if (host->dev_index == 2)
 201                         priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
 202         }
 203
 204         host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
 205         host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
 206         host->div = fdtdec_get_int(blob, node, "div", 0);
 207
 208         return 0;
 209 }
 210
 211 #ifdef CONFIG_DM_MMC
 212 static int exynos_dwmmc_probe(struct udevice *dev)
 213 {
 214         struct exynos_mmc_plat *plat = dev_get_plat(dev);
 215         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 216         struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
 217         struct dwmci_host *host = &priv->host;
 218         int err;
 219
 220         err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host,
 221                                       priv);
 222         if (err)
 223                 return err;
 224         err = do_dwmci_init(host);
 225         if (err)
 226                 return err;
 227
 228         dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
 229         host->mmc = &plat->mmc;
 230         host->mmc->priv = &priv->host;
 231         host->priv = dev;
 232         upriv->mmc = host->mmc;
 233
 234         return dwmci_probe(dev);
 235 }
 236
 237 static int exynos_dwmmc_bind(struct udevice *dev)
 238 {
 239         struct exynos_mmc_plat *plat = dev_get_plat(dev);
 240
 241         return dwmci_bind(dev, &plat->mmc, &plat->cfg);
 242 }
 243
 244 static const struct udevice_id exynos_dwmmc_ids[] = {
 245         { .compatible = "samsung,exynos4412-dw-mshc" },
 246         { .compatible = "samsung,exynos-dwmmc" },
 247         { }
 248 };
 249
 250 U_BOOT_DRIVER(exynos_dwmmc_drv) = {
 251         .name           = "exynos_dwmmc",
 252         .id             = UCLASS_MMC,
 253         .of_match       = exynos_dwmmc_ids,
 254         .bind           = exynos_dwmmc_bind,
 255         .ops            = &dm_dwmci_ops,
 256         .probe          = exynos_dwmmc_probe,
 257         .priv_auto      = sizeof(struct dwmci_exynos_priv_data),
 258         .plat_auto      = sizeof(struct exynos_mmc_plat),
 259 };
 260 #endif