2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/dwmmc.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch/power.h>
20 #define DWMMC_MAX_CH_NUM 4
21 #define DWMMC_MAX_FREQ 52000000
22 #define DWMMC_MIN_FREQ 400000
23 #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001
24 #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001
28 DECLARE_GLOBAL_DATA_PTR
;
30 struct exynos_mmc_plat
{
31 struct mmc_config cfg
;
36 /* Exynos implmentation specific drver private data */
37 struct dwmci_exynos_priv_data
{
39 struct dwmci_host host
;
45 * Function used as callback function to initialise the
46 * CLKSEL register for every mmc channel.
48 static void exynos_dwmci_clksel(struct dwmci_host
*host
)
50 struct dwmci_exynos_priv_data
*priv
= host
->priv
;
52 dwmci_writel(host
, DWMCI_CLKSEL
, priv
->sdr_timing
);
55 unsigned int exynos_dwmci_get_clk(struct dwmci_host
*host
, uint freq
)
61 * Since SDCLKIN is divided inside controller by the DIVRATIO
62 * value set in the CLKSEL register, we need to use the same output
63 * clock value to calculate the CLKDIV value.
64 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
66 clk_div
= ((dwmci_readl(host
, DWMCI_CLKSEL
) >> DWMCI_DIVRATIO_BIT
)
67 & DWMCI_DIVRATIO_MASK
) + 1;
68 sclk
= get_mmc_clk(host
->dev_index
);
71 * Assume to know divider value.
72 * When clock unit is broken, need to set "host->div"
74 return sclk
/ clk_div
/ (host
->div
+ 1);
77 static void exynos_dwmci_board_init(struct dwmci_host
*host
)
79 struct dwmci_exynos_priv_data
*priv
= host
->priv
;
81 if (host
->quirks
& DWMCI_QUIRK_DISABLE_SMU
) {
82 dwmci_writel(host
, EMMCP_MPSBEGIN0
, 0);
83 dwmci_writel(host
, EMMCP_SEND0
, 0);
84 dwmci_writel(host
, EMMCP_CTRL0
,
85 MPSCTRL_SECURE_READ_BIT
|
86 MPSCTRL_SECURE_WRITE_BIT
|
87 MPSCTRL_NON_SECURE_READ_BIT
|
88 MPSCTRL_NON_SECURE_WRITE_BIT
| MPSCTRL_VALID
);
91 /* Set to timing value at initial time */
93 exynos_dwmci_clksel(host
);
96 static int exynos_dwmci_core_init(struct dwmci_host
*host
)
99 unsigned long freq
, sclk
;
104 freq
= DWMMC_MAX_FREQ
;
106 /* request mmc clock vlaue of 52MHz. */
107 sclk
= get_mmc_clk(host
->dev_index
);
108 div
= DIV_ROUND_UP(sclk
, freq
);
109 /* set the clock divisor for mmc */
110 set_mmc_clk(host
->dev_index
, div
);
112 host
->name
= "EXYNOS DWMMC";
113 #ifdef CONFIG_EXYNOS5420
114 host
->quirks
= DWMCI_QUIRK_DISABLE_SMU
;
116 host
->board_init
= exynos_dwmci_board_init
;
118 host
->caps
= MMC_MODE_DDR_52MHz
;
119 host
->clksel
= exynos_dwmci_clksel
;
120 host
->get_mmc_clk
= exynos_dwmci_get_clk
;
122 #ifndef CONFIG_DM_MMC
123 /* Add the mmc channel to be registered with mmc core */
124 if (add_dwmci(host
, DWMMC_MAX_FREQ
, DWMMC_MIN_FREQ
)) {
125 printf("DWMMC%d registration failed\n", host
->dev_index
);
133 static struct dwmci_host dwmci_host
[DWMMC_MAX_CH_NUM
];
135 static int do_dwmci_init(struct dwmci_host
*host
)
139 flag
= host
->buswidth
== 8 ? PINMUX_FLAG_8BIT_MODE
: PINMUX_FLAG_NONE
;
140 err
= exynos_pinmux_config(host
->dev_id
, flag
);
142 printf("DWMMC%d not configure\n", host
->dev_index
);
146 return exynos_dwmci_core_init(host
);
149 static int exynos_dwmci_get_config(const void *blob
, int node
,
150 struct dwmci_host
*host
)
154 struct dwmci_exynos_priv_data
*priv
;
156 priv
= malloc(sizeof(struct dwmci_exynos_priv_data
));
158 error("dwmci_exynos_priv_data malloc fail!\n");
162 /* Extract device id for each mmc channel */
163 host
->dev_id
= pinmux_decode_periph_id(blob
, node
);
165 host
->dev_index
= fdtdec_get_int(blob
, node
, "index", host
->dev_id
);
166 if (host
->dev_index
== host
->dev_id
)
167 host
->dev_index
= host
->dev_id
- PERIPH_ID_SDMMC0
;
169 if (host
->dev_index
> 4) {
170 printf("DWMMC%d: Can't get the dev index\n", host
->dev_index
);
174 /* Get the bus width from the device node (Default is 4bit buswidth) */
175 host
->buswidth
= fdtdec_get_int(blob
, node
, "samsung,bus-width", 4);
177 /* Set the base address from the device node */
178 base
= fdtdec_get_addr(blob
, node
, "reg");
180 printf("DWMMC%d: Can't get base address\n", host
->dev_index
);
183 host
->ioaddr
= (void *)base
;
185 /* Extract the timing info from the node */
186 err
= fdtdec_get_int_array(blob
, node
, "samsung,timing", timing
, 3);
188 printf("DWMMC%d: Can't get sdr-timings for devider\n",
193 priv
->sdr_timing
= (DWMCI_SET_SAMPLE_CLK(timing
[0]) |
194 DWMCI_SET_DRV_CLK(timing
[1]) |
195 DWMCI_SET_DIV_RATIO(timing
[2]));
197 /* sdr_timing didn't assigned anything, use the default value */
198 if (!priv
->sdr_timing
) {
199 if (host
->dev_index
== 0)
200 priv
->sdr_timing
= DWMMC_MMC0_SDR_TIMING_VAL
;
201 else if (host
->dev_index
== 2)
202 priv
->sdr_timing
= DWMMC_MMC2_SDR_TIMING_VAL
;
205 host
->fifoth_val
= fdtdec_get_int(blob
, node
, "fifoth_val", 0);
206 host
->bus_hz
= fdtdec_get_int(blob
, node
, "bus_hz", 0);
207 host
->div
= fdtdec_get_int(blob
, node
, "div", 0);
214 static int exynos_dwmci_process_node(const void *blob
,
215 int node_list
[], int count
)
217 struct dwmci_host
*host
;
220 for (i
= 0; i
< count
; i
++) {
224 host
= &dwmci_host
[i
];
225 err
= exynos_dwmci_get_config(blob
, node
, host
);
227 printf("%s: failed to decode dev %d\n", __func__
, i
);
236 int exynos_dwmmc_init(const void *blob
)
238 int node_list
[DWMMC_MAX_CH_NUM
];
242 count
= fdtdec_find_aliases_for_id(blob
, "mmc",
243 COMPAT_SAMSUNG_EXYNOS_DWMMC
, node_list
,
246 /* For DWMMC always set boot device as mmc 0 */
247 if (count
>= 3 && get_boot_mode() == BOOT_MODE_SD
) {
248 boot_dev_node
= node_list
[2];
249 node_list
[2] = node_list
[0];
250 node_list
[0] = boot_dev_node
;
253 err
= exynos_dwmci_process_node(blob
, node_list
, count
);
259 static int exynos_dwmmc_probe(struct udevice
*dev
)
261 struct exynos_mmc_plat
*plat
= dev_get_platdata(dev
);
262 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
263 struct dwmci_exynos_priv_data
*priv
= dev_get_priv(dev
);
264 struct dwmci_host
*host
= &priv
->host
;
267 err
= exynos_dwmci_get_config(gd
->fdt_blob
, dev_of_offset(dev
), host
);
270 err
= do_dwmci_init(host
);
274 dwmci_setup_cfg(&plat
->cfg
, host
, DWMMC_MAX_FREQ
, DWMMC_MIN_FREQ
);
275 host
->mmc
= &plat
->mmc
;
276 host
->mmc
->priv
= &priv
->host
;
278 upriv
->mmc
= host
->mmc
;
280 return dwmci_probe(dev
);
283 static int exynos_dwmmc_bind(struct udevice
*dev
)
285 struct exynos_mmc_plat
*plat
= dev_get_platdata(dev
);
287 return dwmci_bind(dev
, &plat
->mmc
, &plat
->cfg
);
290 static const struct udevice_id exynos_dwmmc_ids
[] = {
291 { .compatible
= "samsung,exynos4412-dw-mshc" },
295 U_BOOT_DRIVER(exynos_dwmmc_drv
) = {
296 .name
= "exynos_dwmmc",
298 .of_match
= exynos_dwmmc_ids
,
299 .bind
= exynos_dwmmc_bind
,
300 .ops
= &dm_dwmci_ops
,
301 .probe
= exynos_dwmmc_probe
,
302 .priv_auto_alloc_size
= sizeof(struct dwmci_exynos_priv_data
),
303 .platdata_auto_alloc_size
= sizeof(struct exynos_mmc_plat
),