drivers/mmc/exynos_dw_mmc.c

   1 /*
   2  * (C) Copyright 2012 SAMSUNG Electronics
   3  * Jaehoon Chung <jh80.chung@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dwmmc.h>
  10 #include <fdtdec.h>
  11 #include <libfdt.h>
  12 #include <malloc.h>
  13 #include <asm/arch/dwmmc.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/pinmux.h>
  16
  17 #define DWMMC_MAX_CH_NUM                4
  18 #define DWMMC_MAX_FREQ                  52000000
  19 #define DWMMC_MIN_FREQ                  400000
  20 #define DWMMC_MMC0_CLKSEL_VAL           0x03030001
  21 #define DWMMC_MMC2_CLKSEL_VAL           0x03020001
  22
  23 /*
  24  * Function used as callback function to initialise the
  25  * CLKSEL register for every mmc channel.
  26  */
  27 static void exynos_dwmci_clksel(struct dwmci_host *host)
  28 {
  29         dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
  30 }
  31
  32 unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
  33 {
  34         unsigned long sclk;
  35         int8_t clk_div;
  36
  37         /*
  38          * Since SDCLKIN is divided inside controller by the DIVRATIO
  39          * value set in the CLKSEL register, we need to use the same output
  40          * clock value to calculate the CLKDIV value.
  41          * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
  42          */
  43         clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
  44                         & DWMCI_DIVRATIO_MASK) + 1;
  45         sclk = get_mmc_clk(host->dev_index);
  46
  47         return sclk / clk_div;
  48 }
  49
  50 static void exynos_dwmci_board_init(struct dwmci_host *host)
  51 {
  52         if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
  53                 dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
  54                 dwmci_writel(host, EMMCP_SEND0, 0);
  55                 dwmci_writel(host, EMMCP_CTRL0,
  56                              MPSCTRL_SECURE_READ_BIT |
  57                              MPSCTRL_SECURE_WRITE_BIT |
  58                              MPSCTRL_NON_SECURE_READ_BIT |
  59                              MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
  60         }
  61 }
  62
  63 /*
  64  * This function adds the mmc channel to be registered with mmc core.
  65  * index -      mmc channel number.
  66  * regbase -    register base address of mmc channel specified in 'index'.
  67  * bus_width -  operating bus width of mmc channel specified in 'index'.
  68  * clksel -     value to be written into CLKSEL register in case of FDT.
  69  *              NULL in case od non-FDT.
  70  */
  71 int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
  72 {
  73         struct dwmci_host *host = NULL;
  74         unsigned int div;
  75         unsigned long freq, sclk;
  76         host = malloc(sizeof(struct dwmci_host));
  77         if (!host) {
  78                 printf("dwmci_host malloc fail!\n");
  79                 return 1;
  80         }
  81         /* request mmc clock vlaue of 52MHz.  */
  82         freq = 52000000;
  83         sclk = get_mmc_clk(index);
  84         div = DIV_ROUND_UP(sclk, freq);
  85         /* set the clock divisor for mmc */
  86         set_mmc_clk(index, div);
  87
  88         host->name = "EXYNOS DWMMC";
  89         host->ioaddr = (void *)regbase;
  90         host->buswidth = bus_width;
  91 #ifdef CONFIG_EXYNOS5420
  92         host->quirks = DWMCI_QUIRK_DISABLE_SMU;
  93 #endif
  94         host->board_init = exynos_dwmci_board_init;
  95
  96         if (clksel) {
  97                 host->clksel_val = clksel;
  98         } else {
  99                 if (0 == index)
 100                         host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
 101                 if (2 == index)
 102                         host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
 103         }
 104
 105         host->clksel = exynos_dwmci_clksel;
 106         host->dev_index = index;
 107         host->get_mmc_clk = exynos_dwmci_get_clk;
 108         /* Add the mmc channel to be registered with mmc core */
 109         if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
 110                 debug("dwmmc%d registration failed\n", index);
 111                 return -1;
 112         }
 113         return 0;
 114 }
 115
 116 #ifdef CONFIG_OF_CONTROL
 117 int exynos_dwmmc_init(const void *blob)
 118 {
 119         int index, bus_width;
 120         int node_list[DWMMC_MAX_CH_NUM];
 121         int err = 0, dev_id, flag, count, i;
 122         u32 clksel_val, base, timing[3];
 123
 124         count = fdtdec_find_aliases_for_id(blob, "mmc",
 125                                 COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
 126                                 DWMMC_MAX_CH_NUM);
 127
 128         for (i = 0; i < count; i++) {
 129                 int node = node_list[i];
 130
 131                 if (node <= 0)
 132                         continue;
 133
 134                 /* Extract device id for each mmc channel */
 135                 dev_id = pinmux_decode_periph_id(blob, node);
 136
 137                 /* Get the bus width from the device node */
 138                 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
 139                 if (bus_width <= 0) {
 140                         debug("DWMMC: Can't get bus-width\n");
 141                         return -1;
 142                 }
 143                 if (8 == bus_width)
 144                         flag = PINMUX_FLAG_8BIT_MODE;
 145                 else
 146                         flag = PINMUX_FLAG_NONE;
 147
 148                 /* config pinmux for each mmc channel */
 149                 err = exynos_pinmux_config(dev_id, flag);
 150                 if (err) {
 151                         debug("DWMMC not configured\n");
 152                         return err;
 153                 }
 154
 155                 index = dev_id - PERIPH_ID_SDMMC0;
 156
 157                 /* Get the base address from the device node */
 158                 base = fdtdec_get_addr(blob, node, "reg");
 159                 if (!base) {
 160                         debug("DWMMC: Can't get base address\n");
 161                         return -1;
 162                 }
 163                 /* Extract the timing info from the node */
 164                 err = fdtdec_get_int_array(blob, node, "samsung,timing",
 165                                         timing, 3);
 166                 if (err) {
 167                         debug("Can't get sdr-timings for divider\n");
 168                         return -1;
 169                 }
 170
 171                 clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
 172                                 DWMCI_SET_DRV_CLK(timing[1]) |
 173                                 DWMCI_SET_DIV_RATIO(timing[2]));
 174                 /* Initialise each mmc channel */
 175                 err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
 176                 if (err)
 177                         debug("dwmmc Channel-%d init failed\n", index);
 178         }
 179         return 0;
 180 }
 181 #endif