drivers/mmc/exynos_dw_mmc.c

   1 /*
   2  * (C) Copyright 2012 SAMSUNG Electronics
   3  * Jaehoon Chung <jh80.chung@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dwmmc.h>
  10 #include <fdtdec.h>
  11 #include <libfdt.h>
  12 #include <malloc.h>
  13 #include <asm/arch/dwmmc.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/pinmux.h>
  16 #include <asm/arch/power.h>
  17 #include <asm/gpio.h>
  18 #include <asm-generic/errno.h>
  19
  20 #define DWMMC_MAX_CH_NUM                4
  21 #define DWMMC_MAX_FREQ                  52000000
  22 #define DWMMC_MIN_FREQ                  400000
  23 #define DWMMC_MMC0_SDR_TIMING_VAL       0x03030001
  24 #define DWMMC_MMC2_SDR_TIMING_VAL       0x03020001
  25
  26 /* Exynos implmentation specific drver private data */
  27 struct dwmci_exynos_priv_data {
  28         u32 sdr_timing;
  29 };
  30
  31 /*
  32  * Function used as callback function to initialise the
  33  * CLKSEL register for every mmc channel.
  34  */
  35 static void exynos_dwmci_clksel(struct dwmci_host *host)
  36 {
  37         struct dwmci_exynos_priv_data *priv = host->priv;
  38
  39         dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
  40 }
  41
  42 unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
  43 {
  44         unsigned long sclk;
  45         int8_t clk_div;
  46
  47         /*
  48          * Since SDCLKIN is divided inside controller by the DIVRATIO
  49          * value set in the CLKSEL register, we need to use the same output
  50          * clock value to calculate the CLKDIV value.
  51          * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
  52          */
  53         clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
  54                         & DWMCI_DIVRATIO_MASK) + 1;
  55         sclk = get_mmc_clk(host->dev_index);
  56
  57         /*
  58          * Assume to know divider value.
  59          * When clock unit is broken, need to set "host->div"
  60          */
  61         return sclk / clk_div / (host->div + 1);
  62 }
  63
  64 static void exynos_dwmci_board_init(struct dwmci_host *host)
  65 {
  66         struct dwmci_exynos_priv_data *priv = host->priv;
  67
  68         if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
  69                 dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
  70                 dwmci_writel(host, EMMCP_SEND0, 0);
  71                 dwmci_writel(host, EMMCP_CTRL0,
  72                              MPSCTRL_SECURE_READ_BIT |
  73                              MPSCTRL_SECURE_WRITE_BIT |
  74                              MPSCTRL_NON_SECURE_READ_BIT |
  75                              MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
  76         }
  77
  78         /* Set to timing value at initial time */
  79         if (priv->sdr_timing)
  80                 exynos_dwmci_clksel(host);
  81 }
  82
  83 static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
  84 {
  85         unsigned int div;
  86         unsigned long freq, sclk;
  87         struct dwmci_exynos_priv_data *priv = host->priv;
  88
  89         if (host->bus_hz)
  90                 freq = host->bus_hz;
  91         else
  92                 freq = DWMMC_MAX_FREQ;
  93
  94         /* request mmc clock vlaue of 52MHz.  */
  95         sclk = get_mmc_clk(index);
  96         div = DIV_ROUND_UP(sclk, freq);
  97         /* set the clock divisor for mmc */
  98         set_mmc_clk(index, div);
  99
 100         host->name = "EXYNOS DWMMC";
 101 #ifdef CONFIG_EXYNOS5420
 102         host->quirks = DWMCI_QUIRK_DISABLE_SMU;
 103 #endif
 104         host->board_init = exynos_dwmci_board_init;
 105
 106         if (!priv->sdr_timing) {
 107                 if (index == 0)
 108                         priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
 109                 else if (index == 2)
 110                         priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
 111         }
 112
 113         host->caps = MMC_MODE_DDR_52MHz;
 114         host->clksel = exynos_dwmci_clksel;
 115         host->dev_index = index;
 116         host->get_mmc_clk = exynos_dwmci_get_clk;
 117         /* Add the mmc channel to be registered with mmc core */
 118         if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
 119                 printf("DWMMC%d registration failed\n", index);
 120                 return -1;
 121         }
 122         return 0;
 123 }
 124
 125 #if CONFIG_IS_ENABLED(OF_CONTROL)
 126 static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
 127
 128 static int do_dwmci_init(struct dwmci_host *host)
 129 {
 130         int index, flag, err;
 131
 132         index = host->dev_index;
 133
 134         flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
 135         err = exynos_pinmux_config(host->dev_id, flag);
 136         if (err) {
 137                 printf("DWMMC%d not configure\n", index);
 138                 return err;
 139         }
 140
 141         return exynos_dwmci_core_init(host, index);
 142 }
 143
 144 static int exynos_dwmci_get_config(const void *blob, int node,
 145                                         struct dwmci_host *host)
 146 {
 147         int err = 0;
 148         u32 base, timing[3];
 149         struct dwmci_exynos_priv_data *priv;
 150
 151         priv = malloc(sizeof(struct dwmci_exynos_priv_data));
 152         if (!priv) {
 153                 error("dwmci_exynos_priv_data malloc fail!\n");
 154                 return -ENOMEM;
 155         }
 156
 157         /* Extract device id for each mmc channel */
 158         host->dev_id = pinmux_decode_periph_id(blob, node);
 159
 160         host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
 161         if (host->dev_index == host->dev_id)
 162                 host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
 163
 164         /* Get the bus width from the device node */
 165         host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
 166         if (host->buswidth <= 0) {
 167                 printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
 168                 return -EINVAL;
 169         }
 170
 171         /* Set the base address from the device node */
 172         base = fdtdec_get_addr(blob, node, "reg");
 173         if (!base) {
 174                 printf("DWMMC%d: Can't get base address\n", host->dev_index);
 175                 return -EINVAL;
 176         }
 177         host->ioaddr = (void *)base;
 178
 179         /* Extract the timing info from the node */
 180         err =  fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
 181         if (err) {
 182                 printf("DWMMC%d: Can't get sdr-timings for devider\n",
 183                                 host->dev_index);
 184                 return -EINVAL;
 185         }
 186
 187         priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
 188                         DWMCI_SET_DRV_CLK(timing[1]) |
 189                         DWMCI_SET_DIV_RATIO(timing[2]));
 190
 191         /* sdr_timing didn't assigned anything, use the default value */
 192         if (!priv->sdr_timing) {
 193                 if (host->dev_index == 0)
 194                         priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
 195                 else if (host->dev_index == 2)
 196                         priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
 197         }
 198
 199         host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
 200         host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
 201         host->div = fdtdec_get_int(blob, node, "div", 0);
 202
 203         host->priv = priv;
 204
 205         return 0;
 206 }
 207
 208 static int exynos_dwmci_process_node(const void *blob,
 209                                         int node_list[], int count)
 210 {
 211         struct dwmci_host *host;
 212         int i, node, err;
 213
 214         for (i = 0; i < count; i++) {
 215                 node = node_list[i];
 216                 if (node <= 0)
 217                         continue;
 218                 host = &dwmci_host[i];
 219                 err = exynos_dwmci_get_config(blob, node, host);
 220                 if (err) {
 221                         printf("%s: failed to decode dev %d\n", __func__, i);
 222                         return err;
 223                 }
 224
 225                 do_dwmci_init(host);
 226         }
 227         return 0;
 228 }
 229
 230 int exynos_dwmmc_init(const void *blob)
 231 {
 232         int compat_id;
 233         int node_list[DWMMC_MAX_CH_NUM];
 234         int boot_dev_node;
 235         int err = 0, count;
 236
 237         compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;
 238
 239         count = fdtdec_find_aliases_for_id(blob, "mmc",
 240                                 compat_id, node_list, DWMMC_MAX_CH_NUM);
 241
 242         /* For DWMMC always set boot device as mmc 0 */
 243         if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) {
 244                 boot_dev_node = node_list[2];
 245                 node_list[2] = node_list[0];
 246                 node_list[0] = boot_dev_node;
 247         }
 248
 249         err = exynos_dwmci_process_node(blob, node_list, count);
 250
 251         return err;
 252 }
 253 #endif