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[thirdparty/u-boot.git] / drivers / mmc / fsl_esdhc.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
5 * Andy Fleming
6 *
7 * Based vaguely on the pxa mmc code:
8 * (C) Copyright 2003
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
10 */
11
12 #include <config.h>
13 #include <common.h>
14 #include <command.h>
15 #include <cpu_func.h>
16 #include <errno.h>
17 #include <hwconfig.h>
18 #include <mmc.h>
19 #include <part.h>
20 #include <malloc.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
23 #include <asm/io.h>
24 #include <dm.h>
25 #include <dm/device_compat.h>
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 struct fsl_esdhc {
30 uint dsaddr; /* SDMA system address register */
31 uint blkattr; /* Block attributes register */
32 uint cmdarg; /* Command argument register */
33 uint xfertyp; /* Transfer type register */
34 uint cmdrsp0; /* Command response 0 register */
35 uint cmdrsp1; /* Command response 1 register */
36 uint cmdrsp2; /* Command response 2 register */
37 uint cmdrsp3; /* Command response 3 register */
38 uint datport; /* Buffer data port register */
39 uint prsstat; /* Present state register */
40 uint proctl; /* Protocol control register */
41 uint sysctl; /* System Control Register */
42 uint irqstat; /* Interrupt status register */
43 uint irqstaten; /* Interrupt status enable register */
44 uint irqsigen; /* Interrupt signal enable register */
45 uint autoc12err; /* Auto CMD error status register */
46 uint hostcapblt; /* Host controller capabilities register */
47 uint wml; /* Watermark level register */
48 char reserved1[8]; /* reserved */
49 uint fevt; /* Force event register */
50 uint admaes; /* ADMA error status register */
51 uint adsaddr; /* ADMA system address register */
52 char reserved2[160];
53 uint hostver; /* Host controller version register */
54 char reserved3[4]; /* reserved */
55 uint dmaerraddr; /* DMA error address register */
56 char reserved4[4]; /* reserved */
57 uint dmaerrattr; /* DMA error attribute register */
58 char reserved5[4]; /* reserved */
59 uint hostcapblt2; /* Host controller capabilities register 2 */
60 char reserved6[756]; /* reserved */
61 uint esdhcctl; /* eSDHC control register */
62 };
63
64 struct fsl_esdhc_plat {
65 struct mmc_config cfg;
66 struct mmc mmc;
67 };
68
69 /**
70 * struct fsl_esdhc_priv
71 *
72 * @esdhc_regs: registers of the sdhc controller
73 * @sdhc_clk: Current clk of the sdhc controller
74 * @bus_width: bus width, 1bit, 4bit or 8bit
75 * @cfg: mmc config
76 * @mmc: mmc
77 * Following is used when Driver Model is enabled for MMC
78 * @dev: pointer for the device
79 * @cd_gpio: gpio for card detection
80 * @wp_gpio: gpio for write protection
81 */
82 struct fsl_esdhc_priv {
83 struct fsl_esdhc *esdhc_regs;
84 unsigned int sdhc_clk;
85 bool is_sdhc_per_clk;
86 unsigned int clock;
87 #if !CONFIG_IS_ENABLED(DM_MMC)
88 struct mmc *mmc;
89 #endif
90 struct udevice *dev;
91 };
92
93 /* Return the XFERTYP flags for a given command and data packet */
94 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
95 {
96 uint xfertyp = 0;
97
98 if (data) {
99 xfertyp |= XFERTYP_DPSEL;
100 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
101 xfertyp |= XFERTYP_DMAEN;
102 #endif
103 if (data->blocks > 1) {
104 xfertyp |= XFERTYP_MSBSEL;
105 xfertyp |= XFERTYP_BCEN;
106 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
107 xfertyp |= XFERTYP_AC12EN;
108 #endif
109 }
110
111 if (data->flags & MMC_DATA_READ)
112 xfertyp |= XFERTYP_DTDSEL;
113 }
114
115 if (cmd->resp_type & MMC_RSP_CRC)
116 xfertyp |= XFERTYP_CCCEN;
117 if (cmd->resp_type & MMC_RSP_OPCODE)
118 xfertyp |= XFERTYP_CICEN;
119 if (cmd->resp_type & MMC_RSP_136)
120 xfertyp |= XFERTYP_RSPTYP_136;
121 else if (cmd->resp_type & MMC_RSP_BUSY)
122 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
123 else if (cmd->resp_type & MMC_RSP_PRESENT)
124 xfertyp |= XFERTYP_RSPTYP_48;
125
126 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
127 xfertyp |= XFERTYP_CMDTYP_ABORT;
128
129 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
130 }
131
132 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
133 /*
134 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
135 */
136 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
137 struct mmc_data *data)
138 {
139 struct fsl_esdhc *regs = priv->esdhc_regs;
140 uint blocks;
141 char *buffer;
142 uint databuf;
143 uint size;
144 uint irqstat;
145 ulong start;
146
147 if (data->flags & MMC_DATA_READ) {
148 blocks = data->blocks;
149 buffer = data->dest;
150 while (blocks) {
151 start = get_timer(0);
152 size = data->blocksize;
153 irqstat = esdhc_read32(&regs->irqstat);
154 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
155 if (get_timer(start) > PIO_TIMEOUT) {
156 printf("\nData Read Failed in PIO Mode.");
157 return;
158 }
159 }
160 while (size && (!(irqstat & IRQSTAT_TC))) {
161 udelay(100); /* Wait before last byte transfer complete */
162 irqstat = esdhc_read32(&regs->irqstat);
163 databuf = in_le32(&regs->datport);
164 *((uint *)buffer) = databuf;
165 buffer += 4;
166 size -= 4;
167 }
168 blocks--;
169 }
170 } else {
171 blocks = data->blocks;
172 buffer = (char *)data->src;
173 while (blocks) {
174 start = get_timer(0);
175 size = data->blocksize;
176 irqstat = esdhc_read32(&regs->irqstat);
177 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
178 if (get_timer(start) > PIO_TIMEOUT) {
179 printf("\nData Write Failed in PIO Mode.");
180 return;
181 }
182 }
183 while (size && (!(irqstat & IRQSTAT_TC))) {
184 udelay(100); /* Wait before last byte transfer complete */
185 databuf = *((uint *)buffer);
186 buffer += 4;
187 size -= 4;
188 irqstat = esdhc_read32(&regs->irqstat);
189 out_le32(&regs->datport, databuf);
190 }
191 blocks--;
192 }
193 }
194 }
195 #endif
196
197 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
198 struct mmc_data *data)
199 {
200 int timeout;
201 struct fsl_esdhc *regs = priv->esdhc_regs;
202 #if defined(CONFIG_FSL_LAYERSCAPE)
203 dma_addr_t addr;
204 #endif
205 uint wml_value;
206
207 wml_value = data->blocksize/4;
208
209 if (data->flags & MMC_DATA_READ) {
210 if (wml_value > WML_RD_WML_MAX)
211 wml_value = WML_RD_WML_MAX_VAL;
212
213 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
214 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
215 #if defined(CONFIG_FSL_LAYERSCAPE)
216 addr = virt_to_phys((void *)(data->dest));
217 if (upper_32_bits(addr))
218 printf("Error found for upper 32 bits\n");
219 else
220 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
221 #else
222 esdhc_write32(&regs->dsaddr, (u32)data->dest);
223 #endif
224 #endif
225 } else {
226 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
227 flush_dcache_range((ulong)data->src,
228 (ulong)data->src+data->blocks
229 *data->blocksize);
230 #endif
231 if (wml_value > WML_WR_WML_MAX)
232 wml_value = WML_WR_WML_MAX_VAL;
233
234 if (!(esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL)) {
235 printf("Can not write to locked SD card.\n");
236 return -EINVAL;
237 }
238
239 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
240 wml_value << 16);
241 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
242 #if defined(CONFIG_FSL_LAYERSCAPE)
243 addr = virt_to_phys((void *)(data->src));
244 if (upper_32_bits(addr))
245 printf("Error found for upper 32 bits\n");
246 else
247 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
248 #else
249 esdhc_write32(&regs->dsaddr, (u32)data->src);
250 #endif
251 #endif
252 }
253
254 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
255
256 /* Calculate the timeout period for data transactions */
257 /*
258 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
259 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
260 * So, Number of SD Clock cycles for 0.25sec should be minimum
261 * (SD Clock/sec * 0.25 sec) SD Clock cycles
262 * = (mmc->clock * 1/4) SD Clock cycles
263 * As 1) >= 2)
264 * => (2^(timeout+13)) >= mmc->clock * 1/4
265 * Taking log2 both the sides
266 * => timeout + 13 >= log2(mmc->clock/4)
267 * Rounding up to next power of 2
268 * => timeout + 13 = log2(mmc->clock/4) + 1
269 * => timeout + 13 = fls(mmc->clock/4)
270 *
271 * However, the MMC spec "It is strongly recommended for hosts to
272 * implement more than 500ms timeout value even if the card
273 * indicates the 250ms maximum busy length." Even the previous
274 * value of 300ms is known to be insufficient for some cards.
275 * So, we use
276 * => timeout + 13 = fls(mmc->clock/2)
277 */
278 timeout = fls(mmc->clock/2);
279 timeout -= 13;
280
281 if (timeout > 14)
282 timeout = 14;
283
284 if (timeout < 0)
285 timeout = 0;
286
287 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
288 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
289 timeout++;
290 #endif
291
292 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
293 timeout = 0xE;
294 #endif
295 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
296
297 return 0;
298 }
299
300 static void check_and_invalidate_dcache_range
301 (struct mmc_cmd *cmd,
302 struct mmc_data *data) {
303 unsigned start = 0;
304 unsigned end = 0;
305 unsigned size = roundup(ARCH_DMA_MINALIGN,
306 data->blocks*data->blocksize);
307 #if defined(CONFIG_FSL_LAYERSCAPE)
308 dma_addr_t addr;
309
310 addr = virt_to_phys((void *)(data->dest));
311 if (upper_32_bits(addr))
312 printf("Error found for upper 32 bits\n");
313 else
314 start = lower_32_bits(addr);
315 #else
316 start = (unsigned)data->dest;
317 #endif
318 end = start + size;
319 invalidate_dcache_range(start, end);
320 }
321
322 /*
323 * Sends a command out on the bus. Takes the mmc pointer,
324 * a command pointer, and an optional data pointer.
325 */
326 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
327 struct mmc_cmd *cmd, struct mmc_data *data)
328 {
329 int err = 0;
330 uint xfertyp;
331 uint irqstat;
332 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
333 struct fsl_esdhc *regs = priv->esdhc_regs;
334 unsigned long start;
335
336 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
337 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
338 return 0;
339 #endif
340
341 esdhc_write32(&regs->irqstat, -1);
342
343 sync();
344
345 /* Wait for the bus to be idle */
346 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
347 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
348 ;
349
350 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
351 ;
352
353 /* Wait at least 8 SD clock cycles before the next command */
354 /*
355 * Note: This is way more than 8 cycles, but 1ms seems to
356 * resolve timing issues with some cards
357 */
358 udelay(1000);
359
360 /* Set up for a data transfer if we have one */
361 if (data) {
362 err = esdhc_setup_data(priv, mmc, data);
363 if(err)
364 return err;
365
366 if (data->flags & MMC_DATA_READ)
367 check_and_invalidate_dcache_range(cmd, data);
368 }
369
370 /* Figure out the transfer arguments */
371 xfertyp = esdhc_xfertyp(cmd, data);
372
373 /* Mask all irqs */
374 esdhc_write32(&regs->irqsigen, 0);
375
376 /* Send the command */
377 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
378 esdhc_write32(&regs->xfertyp, xfertyp);
379
380 /* Wait for the command to complete */
381 start = get_timer(0);
382 while (!(esdhc_read32(&regs->irqstat) & flags)) {
383 if (get_timer(start) > 1000) {
384 err = -ETIMEDOUT;
385 goto out;
386 }
387 }
388
389 irqstat = esdhc_read32(&regs->irqstat);
390
391 if (irqstat & CMD_ERR) {
392 err = -ECOMM;
393 goto out;
394 }
395
396 if (irqstat & IRQSTAT_CTOE) {
397 err = -ETIMEDOUT;
398 goto out;
399 }
400
401 /* Workaround for ESDHC errata ENGcm03648 */
402 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
403 int timeout = 6000;
404
405 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
406 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
407 PRSSTAT_DAT0)) {
408 udelay(100);
409 timeout--;
410 }
411
412 if (timeout <= 0) {
413 printf("Timeout waiting for DAT0 to go high!\n");
414 err = -ETIMEDOUT;
415 goto out;
416 }
417 }
418
419 /* Copy the response to the response buffer */
420 if (cmd->resp_type & MMC_RSP_136) {
421 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
422
423 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
424 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
425 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
426 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
427 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
428 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
429 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
430 cmd->response[3] = (cmdrsp0 << 8);
431 } else
432 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
433
434 /* Wait until all of the blocks are transferred */
435 if (data) {
436 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
437 esdhc_pio_read_write(priv, data);
438 #else
439 do {
440 irqstat = esdhc_read32(&regs->irqstat);
441
442 if (irqstat & IRQSTAT_DTOE) {
443 err = -ETIMEDOUT;
444 goto out;
445 }
446
447 if (irqstat & DATA_ERR) {
448 err = -ECOMM;
449 goto out;
450 }
451 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
452
453 /*
454 * Need invalidate the dcache here again to avoid any
455 * cache-fill during the DMA operations such as the
456 * speculative pre-fetching etc.
457 */
458 if (data->flags & MMC_DATA_READ) {
459 check_and_invalidate_dcache_range(cmd, data);
460 }
461 #endif
462 }
463
464 out:
465 /* Reset CMD and DATA portions on error */
466 if (err) {
467 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
468 SYSCTL_RSTC);
469 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
470 ;
471
472 if (data) {
473 esdhc_write32(&regs->sysctl,
474 esdhc_read32(&regs->sysctl) |
475 SYSCTL_RSTD);
476 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
477 ;
478 }
479 }
480
481 esdhc_write32(&regs->irqstat, -1);
482
483 return err;
484 }
485
486 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
487 {
488 struct fsl_esdhc *regs = priv->esdhc_regs;
489 int div = 1;
490 int pre_div = 2;
491 unsigned int sdhc_clk = priv->sdhc_clk;
492 u32 time_out;
493 u32 value;
494 uint clk;
495
496 if (clock < mmc->cfg->f_min)
497 clock = mmc->cfg->f_min;
498
499 while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
500 pre_div *= 2;
501
502 while (sdhc_clk / (div * pre_div) > clock && div < 16)
503 div++;
504
505 pre_div >>= 1;
506 div -= 1;
507
508 clk = (pre_div << 8) | (div << 4);
509
510 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
511
512 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
513
514 time_out = 20;
515 value = PRSSTAT_SDSTB;
516 while (!(esdhc_read32(&regs->prsstat) & value)) {
517 if (time_out == 0) {
518 printf("fsl_esdhc: Internal clock never stabilised.\n");
519 break;
520 }
521 time_out--;
522 mdelay(1);
523 }
524
525 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
526 }
527
528 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
529 {
530 struct fsl_esdhc *regs = priv->esdhc_regs;
531 u32 value;
532 u32 time_out;
533
534 value = esdhc_read32(&regs->sysctl);
535
536 if (enable)
537 value |= SYSCTL_CKEN;
538 else
539 value &= ~SYSCTL_CKEN;
540
541 esdhc_write32(&regs->sysctl, value);
542
543 time_out = 20;
544 value = PRSSTAT_SDSTB;
545 while (!(esdhc_read32(&regs->prsstat) & value)) {
546 if (time_out == 0) {
547 printf("fsl_esdhc: Internal clock never stabilised.\n");
548 break;
549 }
550 time_out--;
551 mdelay(1);
552 }
553 }
554
555 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
556 {
557 struct fsl_esdhc *regs = priv->esdhc_regs;
558
559 if (priv->is_sdhc_per_clk) {
560 /* Select to use peripheral clock */
561 esdhc_clock_control(priv, false);
562 esdhc_setbits32(&regs->esdhcctl, ESDHCCTL_PCS);
563 esdhc_clock_control(priv, true);
564 }
565
566 /* Set the clock speed */
567 if (priv->clock != mmc->clock)
568 set_sysctl(priv, mmc, mmc->clock);
569
570 /* Set the bus width */
571 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
572
573 if (mmc->bus_width == 4)
574 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
575 else if (mmc->bus_width == 8)
576 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
577
578 return 0;
579 }
580
581 static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs)
582 {
583 #ifdef CONFIG_ARCH_MPC830X
584 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
585 sysconf83xx_t *sysconf = &immr->sysconf;
586
587 setbits_be32(&sysconf->sdhccr, 0x02000000);
588 #else
589 esdhc_write32(&regs->esdhcctl, 0x00000040);
590 #endif
591 }
592
593 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
594 {
595 struct fsl_esdhc *regs = priv->esdhc_regs;
596 ulong start;
597
598 /* Reset the entire host controller */
599 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
600
601 /* Wait until the controller is available */
602 start = get_timer(0);
603 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
604 if (get_timer(start) > 1000)
605 return -ETIMEDOUT;
606 }
607
608 esdhc_enable_cache_snooping(regs);
609
610 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
611
612 /* Set the initial clock speed */
613 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
614
615 /* Disable the BRR and BWR bits in IRQSTAT */
616 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
617
618 /* Put the PROCTL reg back to the default */
619 esdhc_write32(&regs->proctl, PROCTL_INIT);
620
621 /* Set timout to the maximum value */
622 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
623
624 return 0;
625 }
626
627 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
628 {
629 struct fsl_esdhc *regs = priv->esdhc_regs;
630 int timeout = 1000;
631
632 #ifdef CONFIG_ESDHC_DETECT_QUIRK
633 if (CONFIG_ESDHC_DETECT_QUIRK)
634 return 1;
635 #endif
636 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
637 udelay(1000);
638
639 return timeout > 0;
640 }
641
642 static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
643 struct mmc_config *cfg)
644 {
645 struct fsl_esdhc *regs = priv->esdhc_regs;
646 u32 caps;
647
648 caps = esdhc_read32(&regs->hostcapblt);
649 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
650 caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
651 #endif
652 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
653 caps |= HOSTCAPBLT_VS33;
654 #endif
655 if (caps & HOSTCAPBLT_VS18)
656 cfg->voltages |= MMC_VDD_165_195;
657 if (caps & HOSTCAPBLT_VS30)
658 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
659 if (caps & HOSTCAPBLT_VS33)
660 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
661
662 cfg->name = "FSL_SDHC";
663
664 if (caps & HOSTCAPBLT_HSS)
665 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
666
667 cfg->f_min = 400000;
668 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
669 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
670 }
671
672 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
673 void mmc_adapter_card_type_ident(void)
674 {
675 u8 card_id;
676 u8 value;
677
678 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
679 gd->arch.sdhc_adapter = card_id;
680
681 switch (card_id) {
682 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
683 value = QIXIS_READ(brdcfg[5]);
684 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
685 QIXIS_WRITE(brdcfg[5], value);
686 break;
687 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
688 value = QIXIS_READ(pwr_ctl[1]);
689 value |= QIXIS_EVDD_BY_SDHC_VS;
690 QIXIS_WRITE(pwr_ctl[1], value);
691 break;
692 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
693 value = QIXIS_READ(brdcfg[5]);
694 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
695 QIXIS_WRITE(brdcfg[5], value);
696 break;
697 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
698 break;
699 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
700 break;
701 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
702 break;
703 case QIXIS_ESDHC_NO_ADAPTER:
704 break;
705 default:
706 break;
707 }
708 }
709 #endif
710
711 #ifdef CONFIG_OF_LIBFDT
712 __weak int esdhc_status_fixup(void *blob, const char *compat)
713 {
714 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
715 if (!hwconfig("esdhc")) {
716 do_fixup_by_compat(blob, compat, "status", "disabled",
717 sizeof("disabled"), 1);
718 return 1;
719 }
720 #endif
721 return 0;
722 }
723
724 void fdt_fixup_esdhc(void *blob, bd_t *bd)
725 {
726 const char *compat = "fsl,esdhc";
727
728 if (esdhc_status_fixup(blob, compat))
729 return;
730
731 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
732 gd->arch.sdhc_clk, 1);
733 }
734 #endif
735
736 #if !CONFIG_IS_ENABLED(DM_MMC)
737 static int esdhc_getcd(struct mmc *mmc)
738 {
739 struct fsl_esdhc_priv *priv = mmc->priv;
740
741 return esdhc_getcd_common(priv);
742 }
743
744 static int esdhc_init(struct mmc *mmc)
745 {
746 struct fsl_esdhc_priv *priv = mmc->priv;
747
748 return esdhc_init_common(priv, mmc);
749 }
750
751 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
752 struct mmc_data *data)
753 {
754 struct fsl_esdhc_priv *priv = mmc->priv;
755
756 return esdhc_send_cmd_common(priv, mmc, cmd, data);
757 }
758
759 static int esdhc_set_ios(struct mmc *mmc)
760 {
761 struct fsl_esdhc_priv *priv = mmc->priv;
762
763 return esdhc_set_ios_common(priv, mmc);
764 }
765
766 static const struct mmc_ops esdhc_ops = {
767 .getcd = esdhc_getcd,
768 .init = esdhc_init,
769 .send_cmd = esdhc_send_cmd,
770 .set_ios = esdhc_set_ios,
771 };
772
773 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
774 {
775 struct fsl_esdhc_plat *plat;
776 struct fsl_esdhc_priv *priv;
777 struct mmc_config *mmc_cfg;
778 struct mmc *mmc;
779
780 if (!cfg)
781 return -EINVAL;
782
783 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
784 if (!priv)
785 return -ENOMEM;
786 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
787 if (!plat) {
788 free(priv);
789 return -ENOMEM;
790 }
791
792 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
793 priv->sdhc_clk = cfg->sdhc_clk;
794 if (gd->arch.sdhc_per_clk)
795 priv->is_sdhc_per_clk = true;
796
797 mmc_cfg = &plat->cfg;
798
799 if (cfg->max_bus_width == 8) {
800 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
801 MMC_MODE_8BIT;
802 } else if (cfg->max_bus_width == 4) {
803 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
804 } else if (cfg->max_bus_width == 1) {
805 mmc_cfg->host_caps |= MMC_MODE_1BIT;
806 } else {
807 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
808 MMC_MODE_8BIT;
809 printf("No max bus width provided. Assume 8-bit supported.\n");
810 }
811
812 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
813 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
814 mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
815 #endif
816 mmc_cfg->ops = &esdhc_ops;
817
818 fsl_esdhc_get_cfg_common(priv, mmc_cfg);
819
820 mmc = mmc_create(mmc_cfg, priv);
821 if (!mmc)
822 return -EIO;
823
824 priv->mmc = mmc;
825 return 0;
826 }
827
828 int fsl_esdhc_mmc_init(bd_t *bis)
829 {
830 struct fsl_esdhc_cfg *cfg;
831
832 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
833 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
834 /* Prefer peripheral clock which provides higher frequency. */
835 if (gd->arch.sdhc_per_clk)
836 cfg->sdhc_clk = gd->arch.sdhc_per_clk;
837 else
838 cfg->sdhc_clk = gd->arch.sdhc_clk;
839 return fsl_esdhc_initialize(bis, cfg);
840 }
841 #else /* DM_MMC */
842 static int fsl_esdhc_probe(struct udevice *dev)
843 {
844 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
845 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
846 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
847 fdt_addr_t addr;
848 struct mmc *mmc;
849
850 addr = dev_read_addr(dev);
851 if (addr == FDT_ADDR_T_NONE)
852 return -EINVAL;
853 #ifdef CONFIG_PPC
854 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
855 #else
856 priv->esdhc_regs = (struct fsl_esdhc *)addr;
857 #endif
858 priv->dev = dev;
859
860 if (gd->arch.sdhc_per_clk) {
861 priv->sdhc_clk = gd->arch.sdhc_per_clk;
862 priv->is_sdhc_per_clk = true;
863 } else {
864 priv->sdhc_clk = gd->arch.sdhc_clk;
865 }
866
867 if (priv->sdhc_clk <= 0) {
868 dev_err(dev, "Unable to get clk for %s\n", dev->name);
869 return -EINVAL;
870 }
871
872 fsl_esdhc_get_cfg_common(priv, &plat->cfg);
873
874 mmc_of_parse(dev, &plat->cfg);
875
876 mmc = &plat->mmc;
877 mmc->cfg = &plat->cfg;
878 mmc->dev = dev;
879
880 upriv->mmc = mmc;
881
882 return esdhc_init_common(priv, mmc);
883 }
884
885 static int fsl_esdhc_get_cd(struct udevice *dev)
886 {
887 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
888 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
889
890 if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
891 return 1;
892
893 return esdhc_getcd_common(priv);
894 }
895
896 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
897 struct mmc_data *data)
898 {
899 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
900 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
901
902 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
903 }
904
905 static int fsl_esdhc_set_ios(struct udevice *dev)
906 {
907 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
908 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
909
910 return esdhc_set_ios_common(priv, &plat->mmc);
911 }
912
913 static const struct dm_mmc_ops fsl_esdhc_ops = {
914 .get_cd = fsl_esdhc_get_cd,
915 .send_cmd = fsl_esdhc_send_cmd,
916 .set_ios = fsl_esdhc_set_ios,
917 #ifdef MMC_SUPPORTS_TUNING
918 .execute_tuning = fsl_esdhc_execute_tuning,
919 #endif
920 };
921
922 static const struct udevice_id fsl_esdhc_ids[] = {
923 { .compatible = "fsl,esdhc", },
924 { /* sentinel */ }
925 };
926
927 static int fsl_esdhc_bind(struct udevice *dev)
928 {
929 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
930
931 return mmc_bind(dev, &plat->mmc, &plat->cfg);
932 }
933
934 U_BOOT_DRIVER(fsl_esdhc) = {
935 .name = "fsl-esdhc-mmc",
936 .id = UCLASS_MMC,
937 .of_match = fsl_esdhc_ids,
938 .ops = &fsl_esdhc_ops,
939 .bind = fsl_esdhc_bind,
940 .probe = fsl_esdhc_probe,
941 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
942 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
943 };
944 #endif
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