drivers/mmc/fsl_esdhc.c

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based vaguely on the pxa mmc code:
   6  * (C) Copyright 2003
   7  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <command.h>
  15 #include <hwconfig.h>
  16 #include <mmc.h>
  17 #include <part.h>
  18 #include <malloc.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <fdt_support.h>
  22 #include <asm/io.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define SDHCI_IRQ_EN_BITS               (IRQSTATEN_CC | IRQSTATEN_TC | \
  27                                 IRQSTATEN_CINT | \
  28                                 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  29                                 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  30                                 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  31                                 IRQSTATEN_DINT)
  32
  33 struct fsl_esdhc {
  34         uint    dsaddr;         /* SDMA system address register */
  35         uint    blkattr;        /* Block attributes register */
  36         uint    cmdarg;         /* Command argument register */
  37         uint    xfertyp;        /* Transfer type register */
  38         uint    cmdrsp0;        /* Command response 0 register */
  39         uint    cmdrsp1;        /* Command response 1 register */
  40         uint    cmdrsp2;        /* Command response 2 register */
  41         uint    cmdrsp3;        /* Command response 3 register */
  42         uint    datport;        /* Buffer data port register */
  43         uint    prsstat;        /* Present state register */
  44         uint    proctl;         /* Protocol control register */
  45         uint    sysctl;         /* System Control Register */
  46         uint    irqstat;        /* Interrupt status register */
  47         uint    irqstaten;      /* Interrupt status enable register */
  48         uint    irqsigen;       /* Interrupt signal enable register */
  49         uint    autoc12err;     /* Auto CMD error status register */
  50         uint    hostcapblt;     /* Host controller capabilities register */
  51         uint    wml;            /* Watermark level register */
  52         uint    mixctrl;        /* For USDHC */
  53         char    reserved1[4];   /* reserved */
  54         uint    fevt;           /* Force event register */
  55         uint    admaes;         /* ADMA error status register */
  56         uint    adsaddr;        /* ADMA system address register */
  57         char    reserved2[160]; /* reserved */
  58         uint    hostver;        /* Host controller version register */
  59         char    reserved3[4];   /* reserved */
  60         uint    dmaerraddr;     /* DMA error address register */
  61         char    reserved4[4];   /* reserved */
  62         uint    dmaerrattr;     /* DMA error attribute register */
  63         char    reserved5[4];   /* reserved */
  64         uint    hostcapblt2;    /* Host controller capabilities register 2 */
  65         char    reserved6[8];   /* reserved */
  66         uint    tcr;            /* Tuning control register */
  67         char    reserved7[28];  /* reserved */
  68         uint    sddirctl;       /* SD direction control register */
  69         char    reserved8[712]; /* reserved */
  70         uint    scr;            /* eSDHC control register */
  71 };
  72
  73 /* Return the XFERTYP flags for a given command and data packet */
  74 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  75 {
  76         uint xfertyp = 0;
  77
  78         if (data) {
  79                 xfertyp |= XFERTYP_DPSEL;
  80 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  81                 xfertyp |= XFERTYP_DMAEN;
  82 #endif
  83                 if (data->blocks > 1) {
  84                         xfertyp |= XFERTYP_MSBSEL;
  85                         xfertyp |= XFERTYP_BCEN;
  86 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  87                         xfertyp |= XFERTYP_AC12EN;
  88 #endif
  89                 }
  90
  91                 if (data->flags & MMC_DATA_READ)
  92                         xfertyp |= XFERTYP_DTDSEL;
  93         }
  94
  95         if (cmd->resp_type & MMC_RSP_CRC)
  96                 xfertyp |= XFERTYP_CCCEN;
  97         if (cmd->resp_type & MMC_RSP_OPCODE)
  98                 xfertyp |= XFERTYP_CICEN;
  99         if (cmd->resp_type & MMC_RSP_136)
 100                 xfertyp |= XFERTYP_RSPTYP_136;
 101         else if (cmd->resp_type & MMC_RSP_BUSY)
 102                 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
 103         else if (cmd->resp_type & MMC_RSP_PRESENT)
 104                 xfertyp |= XFERTYP_RSPTYP_48;
 105
 106 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102XA)
 107         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 108                 xfertyp |= XFERTYP_CMDTYP_ABORT;
 109 #endif
 110         return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 111 }
 112
 113 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 114 /*
 115  * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
 116  */
 117 static void
 118 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
 119 {
 120         struct fsl_esdhc_cfg *cfg = mmc->priv;
 121         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 122         uint blocks;
 123         char *buffer;
 124         uint databuf;
 125         uint size;
 126         uint irqstat;
 127         uint timeout;
 128
 129         if (data->flags & MMC_DATA_READ) {
 130                 blocks = data->blocks;
 131                 buffer = data->dest;
 132                 while (blocks) {
 133                         timeout = PIO_TIMEOUT;
 134                         size = data->blocksize;
 135                         irqstat = esdhc_read32(&regs->irqstat);
 136                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
 137                                 && --timeout);
 138                         if (timeout <= 0) {
 139                                 printf("\nData Read Failed in PIO Mode.");
 140                                 return;
 141                         }
 142                         while (size && (!(irqstat & IRQSTAT_TC))) {
 143                                 udelay(100); /* Wait before last byte transfer complete */
 144                                 irqstat = esdhc_read32(&regs->irqstat);
 145                                 databuf = in_le32(&regs->datport);
 146                                 *((uint *)buffer) = databuf;
 147                                 buffer += 4;
 148                                 size -= 4;
 149                         }
 150                         blocks--;
 151                 }
 152         } else {
 153                 blocks = data->blocks;
 154                 buffer = (char *)data->src;
 155                 while (blocks) {
 156                         timeout = PIO_TIMEOUT;
 157                         size = data->blocksize;
 158                         irqstat = esdhc_read32(&regs->irqstat);
 159                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
 160                                 && --timeout);
 161                         if (timeout <= 0) {
 162                                 printf("\nData Write Failed in PIO Mode.");
 163                                 return;
 164                         }
 165                         while (size && (!(irqstat & IRQSTAT_TC))) {
 166                                 udelay(100); /* Wait before last byte transfer complete */
 167                                 databuf = *((uint *)buffer);
 168                                 buffer += 4;
 169                                 size -= 4;
 170                                 irqstat = esdhc_read32(&regs->irqstat);
 171                                 out_le32(&regs->datport, databuf);
 172                         }
 173                         blocks--;
 174                 }
 175         }
 176 }
 177 #endif
 178
 179 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 180 {
 181         int timeout;
 182         struct fsl_esdhc_cfg *cfg = mmc->priv;
 183         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 184
 185         uint wml_value;
 186
 187         wml_value = data->blocksize/4;
 188
 189         if (data->flags & MMC_DATA_READ) {
 190                 if (wml_value > WML_RD_WML_MAX)
 191                         wml_value = WML_RD_WML_MAX_VAL;
 192
 193                 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 194 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 195                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 196 #endif
 197         } else {
 198 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 199                 flush_dcache_range((ulong)data->src,
 200                                    (ulong)data->src+data->blocks
 201                                          *data->blocksize);
 202 #endif
 203                 if (wml_value > WML_WR_WML_MAX)
 204                         wml_value = WML_WR_WML_MAX_VAL;
 205                 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
 206                         printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
 207                         return TIMEOUT;
 208                 }
 209
 210                 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 211                                         wml_value << 16);
 212 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 213                 esdhc_write32(&regs->dsaddr, (u32)data->src);
 214 #endif
 215         }
 216
 217         esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 218
 219         /* Calculate the timeout period for data transactions */
 220         /*
 221          * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
 222          * 2)Timeout period should be minimum 0.250sec as per SD Card spec
 223          *  So, Number of SD Clock cycles for 0.25sec should be minimum
 224          *              (SD Clock/sec * 0.25 sec) SD Clock cycles
 225          *              = (mmc->clock * 1/4) SD Clock cycles
 226          * As 1) >=  2)
 227          * => (2^(timeout+13)) >= mmc->clock * 1/4
 228          * Taking log2 both the sides
 229          * => timeout + 13 >= log2(mmc->clock/4)
 230          * Rounding up to next power of 2
 231          * => timeout + 13 = log2(mmc->clock/4) + 1
 232          * => timeout + 13 = fls(mmc->clock/4)
 233          */
 234         timeout = fls(mmc->clock/4);
 235         timeout -= 13;
 236
 237         if (timeout > 14)
 238                 timeout = 14;
 239
 240         if (timeout < 0)
 241                 timeout = 0;
 242
 243 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 244         if ((timeout == 4) || (timeout == 8) || (timeout == 12))
 245                 timeout++;
 246 #endif
 247
 248 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 249         timeout = 0xE;
 250 #endif
 251         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 252
 253         return 0;
 254 }
 255
 256 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 257 static void check_and_invalidate_dcache_range
 258         (struct mmc_cmd *cmd,
 259          struct mmc_data *data) {
 260         unsigned start = (unsigned)data->dest ;
 261         unsigned size = roundup(ARCH_DMA_MINALIGN,
 262                                 data->blocks*data->blocksize);
 263         unsigned end = start+size ;
 264         invalidate_dcache_range(start, end);
 265 }
 266 #endif
 267
 268 /*
 269  * Sends a command out on the bus.  Takes the mmc pointer,
 270  * a command pointer, and an optional data pointer.
 271  */
 272 static int
 273 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 274 {
 275         int     err = 0;
 276         uint    xfertyp;
 277         uint    irqstat;
 278         struct fsl_esdhc_cfg *cfg = mmc->priv;
 279         volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 280
 281 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 282         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 283                 return 0;
 284 #endif
 285
 286         esdhc_write32(&regs->irqstat, -1);
 287
 288         sync();
 289
 290         /* Wait for the bus to be idle */
 291         while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
 292                         (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
 293                 ;
 294
 295         while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
 296                 ;
 297
 298         /* Wait at least 8 SD clock cycles before the next command */
 299         /*
 300          * Note: This is way more than 8 cycles, but 1ms seems to
 301          * resolve timing issues with some cards
 302          */
 303         udelay(1000);
 304
 305         /* Set up for a data transfer if we have one */
 306         if (data) {
 307                 err = esdhc_setup_data(mmc, data);
 308                 if(err)
 309                         return err;
 310         }
 311
 312         /* Figure out the transfer arguments */
 313         xfertyp = esdhc_xfertyp(cmd, data);
 314
 315         /* Mask all irqs */
 316         esdhc_write32(&regs->irqsigen, 0);
 317
 318         /* Send the command */
 319         esdhc_write32(&regs->cmdarg, cmd->cmdarg);
 320 #if defined(CONFIG_FSL_USDHC)
 321         esdhc_write32(&regs->mixctrl,
 322         (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
 323         esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 324 #else
 325         esdhc_write32(&regs->xfertyp, xfertyp);
 326 #endif
 327
 328         /* Wait for the command to complete */
 329         while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
 330                 ;
 331
 332         irqstat = esdhc_read32(&regs->irqstat);
 333
 334         if (irqstat & CMD_ERR) {
 335                 err = COMM_ERR;
 336                 goto out;
 337         }
 338
 339         if (irqstat & IRQSTAT_CTOE) {
 340                 err = TIMEOUT;
 341                 goto out;
 342         }
 343
 344         /* Workaround for ESDHC errata ENGcm03648 */
 345         if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
 346                 int timeout = 2500;
 347
 348                 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
 349                 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
 350                                         PRSSTAT_DAT0)) {
 351                         udelay(100);
 352                         timeout--;
 353                 }
 354
 355                 if (timeout <= 0) {
 356                         printf("Timeout waiting for DAT0 to go high!\n");
 357                         err = TIMEOUT;
 358                         goto out;
 359                 }
 360         }
 361
 362         /* Copy the response to the response buffer */
 363         if (cmd->resp_type & MMC_RSP_136) {
 364                 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
 365
 366                 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
 367                 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
 368                 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
 369                 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
 370                 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
 371                 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
 372                 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
 373                 cmd->response[3] = (cmdrsp0 << 8);
 374         } else
 375                 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
 376
 377         /* Wait until all of the blocks are transferred */
 378         if (data) {
 379 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 380                 esdhc_pio_read_write(mmc, data);
 381 #else
 382                 do {
 383                         irqstat = esdhc_read32(&regs->irqstat);
 384
 385                         if (irqstat & IRQSTAT_DTOE) {
 386                                 err = TIMEOUT;
 387                                 goto out;
 388                         }
 389
 390                         if (irqstat & DATA_ERR) {
 391                                 err = COMM_ERR;
 392                                 goto out;
 393                         }
 394                 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 395
 396                 if (data->flags & MMC_DATA_READ)
 397                         check_and_invalidate_dcache_range(cmd, data);
 398 #endif
 399         }
 400
 401 out:
 402         /* Reset CMD and DATA portions on error */
 403         if (err) {
 404                 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
 405                               SYSCTL_RSTC);
 406                 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
 407                         ;
 408
 409                 if (data) {
 410                         esdhc_write32(&regs->sysctl,
 411                                       esdhc_read32(&regs->sysctl) |
 412                                       SYSCTL_RSTD);
 413                         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
 414                                 ;
 415                 }
 416         }
 417
 418         esdhc_write32(&regs->irqstat, -1);
 419
 420         return err;
 421 }
 422
 423 static void set_sysctl(struct mmc *mmc, uint clock)
 424 {
 425         int div, pre_div;
 426         struct fsl_esdhc_cfg *cfg = mmc->priv;
 427         volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 428         int sdhc_clk = cfg->sdhc_clk;
 429         uint clk;
 430
 431         if (clock < mmc->cfg->f_min)
 432                 clock = mmc->cfg->f_min;
 433
 434         if (sdhc_clk / 16 > clock) {
 435                 for (pre_div = 2; pre_div < 256; pre_div *= 2)
 436                         if ((sdhc_clk / pre_div) <= (clock * 16))
 437                                 break;
 438         } else
 439                 pre_div = 2;
 440
 441         for (div = 1; div <= 16; div++)
 442                 if ((sdhc_clk / (div * pre_div)) <= clock)
 443                         break;
 444
 445         pre_div >>= 1;
 446         div -= 1;
 447
 448         clk = (pre_div << 8) | (div << 4);
 449
 450         esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
 451
 452         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 453
 454         udelay(10000);
 455
 456         clk = SYSCTL_PEREN | SYSCTL_CKEN;
 457
 458         esdhc_setbits32(&regs->sysctl, clk);
 459 }
 460
 461 static void esdhc_set_ios(struct mmc *mmc)
 462 {
 463         struct fsl_esdhc_cfg *cfg = mmc->priv;
 464         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 465
 466         /* Set the clock speed */
 467         set_sysctl(mmc, mmc->clock);
 468
 469         /* Set the bus width */
 470         esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
 471
 472         if (mmc->bus_width == 4)
 473                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
 474         else if (mmc->bus_width == 8)
 475                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
 476
 477 }
 478
 479 static int esdhc_init(struct mmc *mmc)
 480 {
 481         struct fsl_esdhc_cfg *cfg = mmc->priv;
 482         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 483         int timeout = 1000;
 484
 485         /* Reset the entire host controller */
 486         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 487
 488         /* Wait until the controller is available */
 489         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 490                 udelay(1000);
 491
 492 #ifndef ARCH_MXC
 493         /* Enable cache snooping */
 494         esdhc_write32(&regs->scr, 0x00000040);
 495 #endif
 496
 497         esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 498
 499         /* Set the initial clock speed */
 500         mmc_set_clock(mmc, 400000);
 501
 502         /* Disable the BRR and BWR bits in IRQSTAT */
 503         esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
 504
 505         /* Put the PROCTL reg back to the default */
 506         esdhc_write32(&regs->proctl, PROCTL_INIT);
 507
 508         /* Set timout to the maximum value */
 509         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 510
 511         return 0;
 512 }
 513
 514 static int esdhc_getcd(struct mmc *mmc)
 515 {
 516         struct fsl_esdhc_cfg *cfg = mmc->priv;
 517         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 518         int timeout = 1000;
 519
 520 #ifdef CONFIG_ESDHC_DETECT_QUIRK
 521         if (CONFIG_ESDHC_DETECT_QUIRK)
 522                 return 1;
 523 #endif
 524         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
 525                 udelay(1000);
 526
 527         return timeout > 0;
 528 }
 529
 530 static void esdhc_reset(struct fsl_esdhc *regs)
 531 {
 532         unsigned long timeout = 100; /* wait max 100 ms */
 533
 534         /* reset the controller */
 535         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 536
 537         /* hardware clears the bit when it is done */
 538         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 539                 udelay(1000);
 540         if (!timeout)
 541                 printf("MMC/SD: Reset never completed.\n");
 542 }
 543
 544 static const struct mmc_ops esdhc_ops = {
 545         .send_cmd       = esdhc_send_cmd,
 546         .set_ios        = esdhc_set_ios,
 547         .init           = esdhc_init,
 548         .getcd          = esdhc_getcd,
 549 };
 550
 551 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 552 {
 553         struct fsl_esdhc *regs;
 554         struct mmc *mmc;
 555         u32 caps, voltage_caps;
 556
 557         if (!cfg)
 558                 return -1;
 559
 560         regs = (struct fsl_esdhc *)cfg->esdhc_base;
 561
 562         /* First reset the eSDHC controller */
 563         esdhc_reset(regs);
 564
 565         esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 566                                 | SYSCTL_IPGEN | SYSCTL_CKEN);
 567
 568         writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
 569         memset(&cfg->cfg, 0, sizeof(cfg->cfg));
 570
 571         voltage_caps = 0;
 572         caps = esdhc_read32(&regs->hostcapblt);
 573
 574 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 575         caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
 576                         ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
 577 #endif
 578
 579 /* T4240 host controller capabilities register should have VS33 bit */
 580 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 581         caps = caps | ESDHC_HOSTCAPBLT_VS33;
 582 #endif
 583
 584         if (caps & ESDHC_HOSTCAPBLT_VS18)
 585                 voltage_caps |= MMC_VDD_165_195;
 586         if (caps & ESDHC_HOSTCAPBLT_VS30)
 587                 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
 588         if (caps & ESDHC_HOSTCAPBLT_VS33)
 589                 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
 590
 591         cfg->cfg.name = "FSL_SDHC";
 592         cfg->cfg.ops = &esdhc_ops;
 593 #ifdef CONFIG_SYS_SD_VOLTAGE
 594         cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
 595 #else
 596         cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 597 #endif
 598         if ((cfg->cfg.voltages & voltage_caps) == 0) {
 599                 printf("voltage not supported by controller\n");
 600                 return -1;
 601         }
 602
 603         cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
 604
 605         if (cfg->max_bus_width > 0) {
 606                 if (cfg->max_bus_width < 8)
 607                         cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
 608                 if (cfg->max_bus_width < 4)
 609                         cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
 610         }
 611
 612         if (caps & ESDHC_HOSTCAPBLT_HSS)
 613                 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 614
 615 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
 616         if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
 617                 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
 618 #endif
 619
 620         cfg->cfg.f_min = 400000;
 621         cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
 622
 623         cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 624
 625         mmc = mmc_create(&cfg->cfg, cfg);
 626         if (mmc == NULL)
 627                 return -1;
 628
 629         return 0;
 630 }
 631
 632 int fsl_esdhc_mmc_init(bd_t *bis)
 633 {
 634         struct fsl_esdhc_cfg *cfg;
 635
 636         cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
 637         cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
 638         cfg->sdhc_clk = gd->arch.sdhc_clk;
 639         return fsl_esdhc_initialize(bis, cfg);
 640 }
 641
 642 #ifdef CONFIG_OF_LIBFDT
 643 void fdt_fixup_esdhc(void *blob, bd_t *bd)
 644 {
 645         const char *compat = "fsl,esdhc";
 646
 647 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
 648         if (!hwconfig("esdhc")) {
 649                 do_fixup_by_compat(blob, compat, "status", "disabled",
 650                                 8 + 1, 1);
 651                 return;
 652         }
 653 #endif
 654
 655         do_fixup_by_compat_u32(blob, compat, "clock-frequency",
 656                                gd->arch.sdhc_clk, 1);
 657
 658         do_fixup_by_compat(blob, compat, "status", "okay",
 659                            4 + 1, 1);
 660 }
 661 #endif