drivers/mmc/fsl_esdhc.c

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based vaguely on the pxa mmc code:
   6  * (C) Copyright 2003
   7  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <command.h>
  15 #include <hwconfig.h>
  16 #include <mmc.h>
  17 #include <part.h>
  18 #include <malloc.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <fdt_support.h>
  22 #include <asm/io.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 struct fsl_esdhc {
  27         uint    dsaddr;
  28         uint    blkattr;
  29         uint    cmdarg;
  30         uint    xfertyp;
  31         uint    cmdrsp0;
  32         uint    cmdrsp1;
  33         uint    cmdrsp2;
  34         uint    cmdrsp3;
  35         uint    datport;
  36         uint    prsstat;
  37         uint    proctl;
  38         uint    sysctl;
  39         uint    irqstat;
  40         uint    irqstaten;
  41         uint    irqsigen;
  42         uint    autoc12err;
  43         uint    hostcapblt;
  44         uint    wml;
  45         uint    mixctrl;
  46         char    reserved1[4];
  47         uint    fevt;
  48         char    reserved2[168];
  49         uint    hostver;
  50         char    reserved3[780];
  51         uint    scr;
  52 };
  53
  54 /* Return the XFERTYP flags for a given command and data packet */
  55 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  56 {
  57         uint xfertyp = 0;
  58
  59         if (data) {
  60                 xfertyp |= XFERTYP_DPSEL;
  61 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  62                 xfertyp |= XFERTYP_DMAEN;
  63 #endif
  64                 if (data->blocks > 1) {
  65                         xfertyp |= XFERTYP_MSBSEL;
  66                         xfertyp |= XFERTYP_BCEN;
  67 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  68                         xfertyp |= XFERTYP_AC12EN;
  69 #endif
  70                 }
  71
  72                 if (data->flags & MMC_DATA_READ)
  73                         xfertyp |= XFERTYP_DTDSEL;
  74         }
  75
  76         if (cmd->resp_type & MMC_RSP_CRC)
  77                 xfertyp |= XFERTYP_CCCEN;
  78         if (cmd->resp_type & MMC_RSP_OPCODE)
  79                 xfertyp |= XFERTYP_CICEN;
  80         if (cmd->resp_type & MMC_RSP_136)
  81                 xfertyp |= XFERTYP_RSPTYP_136;
  82         else if (cmd->resp_type & MMC_RSP_BUSY)
  83                 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
  84         else if (cmd->resp_type & MMC_RSP_PRESENT)
  85                 xfertyp |= XFERTYP_RSPTYP_48;
  86
  87 #if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS)
  88         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  89                 xfertyp |= XFERTYP_CMDTYP_ABORT;
  90 #endif
  91         return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
  92 }
  93
  94 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  95 /*
  96  * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
  97  */
  98 static void
  99 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
 100 {
 101         struct fsl_esdhc_cfg *cfg = mmc->priv;
 102         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 103         uint blocks;
 104         char *buffer;
 105         uint databuf;
 106         uint size;
 107         uint irqstat;
 108         uint timeout;
 109
 110         if (data->flags & MMC_DATA_READ) {
 111                 blocks = data->blocks;
 112                 buffer = data->dest;
 113                 while (blocks) {
 114                         timeout = PIO_TIMEOUT;
 115                         size = data->blocksize;
 116                         irqstat = esdhc_read32(&regs->irqstat);
 117                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
 118                                 && --timeout);
 119                         if (timeout <= 0) {
 120                                 printf("\nData Read Failed in PIO Mode.");
 121                                 return;
 122                         }
 123                         while (size && (!(irqstat & IRQSTAT_TC))) {
 124                                 udelay(100); /* Wait before last byte transfer complete */
 125                                 irqstat = esdhc_read32(&regs->irqstat);
 126                                 databuf = in_le32(&regs->datport);
 127                                 *((uint *)buffer) = databuf;
 128                                 buffer += 4;
 129                                 size -= 4;
 130                         }
 131                         blocks--;
 132                 }
 133         } else {
 134                 blocks = data->blocks;
 135                 buffer = (char *)data->src;
 136                 while (blocks) {
 137                         timeout = PIO_TIMEOUT;
 138                         size = data->blocksize;
 139                         irqstat = esdhc_read32(&regs->irqstat);
 140                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
 141                                 && --timeout);
 142                         if (timeout <= 0) {
 143                                 printf("\nData Write Failed in PIO Mode.");
 144                                 return;
 145                         }
 146                         while (size && (!(irqstat & IRQSTAT_TC))) {
 147                                 udelay(100); /* Wait before last byte transfer complete */
 148                                 databuf = *((uint *)buffer);
 149                                 buffer += 4;
 150                                 size -= 4;
 151                                 irqstat = esdhc_read32(&regs->irqstat);
 152                                 out_le32(&regs->datport, databuf);
 153                         }
 154                         blocks--;
 155                 }
 156         }
 157 }
 158 #endif
 159
 160 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 161 {
 162         int timeout;
 163         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 164         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 165 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 166         uint wml_value;
 167
 168         wml_value = data->blocksize/4;
 169
 170         if (data->flags & MMC_DATA_READ) {
 171                 if (wml_value > WML_RD_WML_MAX)
 172                         wml_value = WML_RD_WML_MAX_VAL;
 173
 174                 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 175                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 176         } else {
 177                 flush_dcache_range((ulong)data->src,
 178                                    (ulong)data->src+data->blocks
 179                                          *data->blocksize);
 180
 181                 if (wml_value > WML_WR_WML_MAX)
 182                         wml_value = WML_WR_WML_MAX_VAL;
 183                 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
 184                         printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
 185                         return TIMEOUT;
 186                 }
 187
 188                 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 189                                         wml_value << 16);
 190                 esdhc_write32(&regs->dsaddr, (u32)data->src);
 191         }
 192 #else   /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
 193         if (!(data->flags & MMC_DATA_READ)) {
 194                 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
 195                         printf("\nThe SD card is locked. "
 196                                 "Can not write to a locked card.\n\n");
 197                         return TIMEOUT;
 198                 }
 199                 esdhc_write32(&regs->dsaddr, (u32)data->src);
 200         } else
 201                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 202 #endif  /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
 203
 204         esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 205
 206         /* Calculate the timeout period for data transactions */
 207         /*
 208          * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
 209          * 2)Timeout period should be minimum 0.250sec as per SD Card spec
 210          *  So, Number of SD Clock cycles for 0.25sec should be minimum
 211          *              (SD Clock/sec * 0.25 sec) SD Clock cycles
 212          *              = (mmc->tran_speed * 1/4) SD Clock cycles
 213          * As 1) >=  2)
 214          * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
 215          * Taking log2 both the sides
 216          * => timeout + 13 >= log2(mmc->tran_speed/4)
 217          * Rounding up to next power of 2
 218          * => timeout + 13 = log2(mmc->tran_speed/4) + 1
 219          * => timeout + 13 = fls(mmc->tran_speed/4)
 220          */
 221         timeout = fls(mmc->tran_speed/4);
 222         timeout -= 13;
 223
 224         if (timeout > 14)
 225                 timeout = 14;
 226
 227         if (timeout < 0)
 228                 timeout = 0;
 229
 230 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 231         if ((timeout == 4) || (timeout == 8) || (timeout == 12))
 232                 timeout++;
 233 #endif
 234
 235         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 236
 237         return 0;
 238 }
 239
 240 static void check_and_invalidate_dcache_range
 241         (struct mmc_cmd *cmd,
 242          struct mmc_data *data) {
 243         unsigned start = (unsigned)data->dest ;
 244         unsigned size = roundup(ARCH_DMA_MINALIGN,
 245                                 data->blocks*data->blocksize);
 246         unsigned end = start+size ;
 247         invalidate_dcache_range(start, end);
 248 }
 249 /*
 250  * Sends a command out on the bus.  Takes the mmc pointer,
 251  * a command pointer, and an optional data pointer.
 252  */
 253 static int
 254 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 255 {
 256         uint    xfertyp;
 257         uint    irqstat;
 258         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 259         volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 260
 261 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 262         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 263                 return 0;
 264 #endif
 265
 266         esdhc_write32(&regs->irqstat, -1);
 267
 268         sync();
 269
 270         /* Wait for the bus to be idle */
 271         while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
 272                         (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
 273                 ;
 274
 275         while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
 276                 ;
 277
 278         /* Wait at least 8 SD clock cycles before the next command */
 279         /*
 280          * Note: This is way more than 8 cycles, but 1ms seems to
 281          * resolve timing issues with some cards
 282          */
 283         udelay(1000);
 284
 285         /* Set up for a data transfer if we have one */
 286         if (data) {
 287                 int err;
 288
 289                 err = esdhc_setup_data(mmc, data);
 290                 if(err)
 291                         return err;
 292         }
 293
 294         /* Figure out the transfer arguments */
 295         xfertyp = esdhc_xfertyp(cmd, data);
 296
 297         /* Mask all irqs */
 298         esdhc_write32(&regs->irqsigen, 0);
 299
 300         /* Send the command */
 301         esdhc_write32(&regs->cmdarg, cmd->cmdarg);
 302 #if defined(CONFIG_FSL_USDHC)
 303         esdhc_write32(&regs->mixctrl,
 304         (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
 305         esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 306 #else
 307         esdhc_write32(&regs->xfertyp, xfertyp);
 308 #endif
 309
 310         /* Wait for the command to complete */
 311         while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
 312                 ;
 313
 314         irqstat = esdhc_read32(&regs->irqstat);
 315
 316         /* Reset CMD and DATA portions on error */
 317         if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
 318                 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
 319                               SYSCTL_RSTC);
 320                 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
 321                         ;
 322
 323                 if (data) {
 324                         esdhc_write32(&regs->sysctl,
 325                                       esdhc_read32(&regs->sysctl) |
 326                                       SYSCTL_RSTD);
 327                         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
 328                                 ;
 329                 }
 330         }
 331
 332         if (irqstat & CMD_ERR)
 333                 return COMM_ERR;
 334
 335         if (irqstat & IRQSTAT_CTOE)
 336                 return TIMEOUT;
 337
 338         /* Workaround for ESDHC errata ENGcm03648 */
 339         if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
 340                 int timeout = 2500;
 341
 342                 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
 343                 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
 344                                         PRSSTAT_DAT0)) {
 345                         udelay(100);
 346                         timeout--;
 347                 }
 348
 349                 if (timeout <= 0) {
 350                         printf("Timeout waiting for DAT0 to go high!\n");
 351                         return TIMEOUT;
 352                 }
 353         }
 354
 355         /* Copy the response to the response buffer */
 356         if (cmd->resp_type & MMC_RSP_136) {
 357                 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
 358
 359                 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
 360                 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
 361                 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
 362                 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
 363                 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
 364                 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
 365                 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
 366                 cmd->response[3] = (cmdrsp0 << 8);
 367         } else
 368                 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
 369
 370         /* Wait until all of the blocks are transferred */
 371         if (data) {
 372 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 373                 esdhc_pio_read_write(mmc, data);
 374 #else
 375                 do {
 376                         irqstat = esdhc_read32(&regs->irqstat);
 377
 378                         if (irqstat & IRQSTAT_DTOE)
 379                                 return TIMEOUT;
 380
 381                         if (irqstat & DATA_ERR)
 382                                 return COMM_ERR;
 383                 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 384 #endif
 385                 if (data->flags & MMC_DATA_READ)
 386                         check_and_invalidate_dcache_range(cmd, data);
 387         }
 388
 389         esdhc_write32(&regs->irqstat, -1);
 390
 391         return 0;
 392 }
 393
 394 static void set_sysctl(struct mmc *mmc, uint clock)
 395 {
 396         int div, pre_div;
 397         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 398         volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 399         int sdhc_clk = cfg->sdhc_clk;
 400         uint clk;
 401
 402         if (clock < mmc->f_min)
 403                 clock = mmc->f_min;
 404
 405         if (sdhc_clk / 16 > clock) {
 406                 for (pre_div = 2; pre_div < 256; pre_div *= 2)
 407                         if ((sdhc_clk / pre_div) <= (clock * 16))
 408                                 break;
 409         } else
 410                 pre_div = 2;
 411
 412         for (div = 1; div <= 16; div++)
 413                 if ((sdhc_clk / (div * pre_div)) <= clock)
 414                         break;
 415
 416         pre_div >>= 1;
 417         div -= 1;
 418
 419         clk = (pre_div << 8) | (div << 4);
 420
 421         esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
 422
 423         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 424
 425         udelay(10000);
 426
 427         clk = SYSCTL_PEREN | SYSCTL_CKEN;
 428
 429         esdhc_setbits32(&regs->sysctl, clk);
 430 }
 431
 432 static void esdhc_set_ios(struct mmc *mmc)
 433 {
 434         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 435         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 436
 437         /* Set the clock speed */
 438         set_sysctl(mmc, mmc->clock);
 439
 440         /* Set the bus width */
 441         esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
 442
 443         if (mmc->bus_width == 4)
 444                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
 445         else if (mmc->bus_width == 8)
 446                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
 447
 448 }
 449
 450 static int esdhc_init(struct mmc *mmc)
 451 {
 452         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 453         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 454         int timeout = 1000;
 455
 456         /* Reset the entire host controller */
 457         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 458
 459         /* Wait until the controller is available */
 460         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 461                 udelay(1000);
 462
 463 #ifndef ARCH_MXC
 464         /* Enable cache snooping */
 465         esdhc_write32(&regs->scr, 0x00000040);
 466 #endif
 467
 468         esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 469
 470         /* Set the initial clock speed */
 471         mmc_set_clock(mmc, 400000);
 472
 473         /* Disable the BRR and BWR bits in IRQSTAT */
 474         esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
 475
 476         /* Put the PROCTL reg back to the default */
 477         esdhc_write32(&regs->proctl, PROCTL_INIT);
 478
 479         /* Set timout to the maximum value */
 480         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 481
 482         return 0;
 483 }
 484
 485 static int esdhc_getcd(struct mmc *mmc)
 486 {
 487         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 488         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 489         int timeout = 1000;
 490
 491         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
 492                 udelay(1000);
 493
 494         return timeout > 0;
 495 }
 496
 497 static void esdhc_reset(struct fsl_esdhc *regs)
 498 {
 499         unsigned long timeout = 100; /* wait max 100 ms */
 500
 501         /* reset the controller */
 502         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 503
 504         /* hardware clears the bit when it is done */
 505         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 506                 udelay(1000);
 507         if (!timeout)
 508                 printf("MMC/SD: Reset never completed.\n");
 509 }
 510
 511 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 512 {
 513         struct fsl_esdhc *regs;
 514         struct mmc *mmc;
 515         u32 caps, voltage_caps;
 516
 517         if (!cfg)
 518                 return -1;
 519
 520         mmc = malloc(sizeof(struct mmc));
 521         if (!mmc)
 522                 return -ENOMEM;
 523
 524         sprintf(mmc->name, "FSL_SDHC");
 525         regs = (struct fsl_esdhc *)cfg->esdhc_base;
 526
 527         /* First reset the eSDHC controller */
 528         esdhc_reset(regs);
 529
 530         esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 531                                 | SYSCTL_IPGEN | SYSCTL_CKEN);
 532
 533         mmc->priv = cfg;
 534         mmc->send_cmd = esdhc_send_cmd;
 535         mmc->set_ios = esdhc_set_ios;
 536         mmc->init = esdhc_init;
 537         mmc->getcd = esdhc_getcd;
 538         mmc->getwp = NULL;
 539
 540         voltage_caps = 0;
 541         caps = regs->hostcapblt;
 542
 543 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 544         caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
 545                         ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
 546 #endif
 547         if (caps & ESDHC_HOSTCAPBLT_VS18)
 548                 voltage_caps |= MMC_VDD_165_195;
 549         if (caps & ESDHC_HOSTCAPBLT_VS30)
 550                 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
 551         if (caps & ESDHC_HOSTCAPBLT_VS33)
 552                 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
 553
 554 #ifdef CONFIG_SYS_SD_VOLTAGE
 555         mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
 556 #else
 557         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 558 #endif
 559         if ((mmc->voltages & voltage_caps) == 0) {
 560                 printf("voltage not supported by controller\n");
 561                 return -1;
 562         }
 563
 564         mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
 565
 566         if (cfg->max_bus_width > 0) {
 567                 if (cfg->max_bus_width < 8)
 568                         mmc->host_caps &= ~MMC_MODE_8BIT;
 569                 if (cfg->max_bus_width < 4)
 570                         mmc->host_caps &= ~MMC_MODE_4BIT;
 571         }
 572
 573         if (caps & ESDHC_HOSTCAPBLT_HSS)
 574                 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 575
 576         mmc->f_min = 400000;
 577         mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
 578
 579         mmc->b_max = 0;
 580         mmc_register(mmc);
 581
 582         return 0;
 583 }
 584
 585 int fsl_esdhc_mmc_init(bd_t *bis)
 586 {
 587         struct fsl_esdhc_cfg *cfg;
 588
 589         cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
 590         cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
 591         cfg->sdhc_clk = gd->arch.sdhc_clk;
 592         return fsl_esdhc_initialize(bis, cfg);
 593 }
 594
 595 #ifdef CONFIG_OF_LIBFDT
 596 void fdt_fixup_esdhc(void *blob, bd_t *bd)
 597 {
 598         const char *compat = "fsl,esdhc";
 599
 600 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
 601         if (!hwconfig("esdhc")) {
 602                 do_fixup_by_compat(blob, compat, "status", "disabled",
 603                                 8 + 1, 1);
 604                 return;
 605         }
 606 #endif
 607
 608         do_fixup_by_compat_u32(blob, compat, "clock-frequency",
 609                                gd->arch.sdhc_clk, 1);
 610
 611         do_fixup_by_compat(blob, compat, "status", "okay",
 612                            4 + 1, 1);
 613 }
 614 #endif