drivers/mmc/fsl_esdhc.c

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based vaguely on the pxa mmc code:
   6  * (C) Copyright 2003
   7  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <command.h>
  15 #include <hwconfig.h>
  16 #include <mmc.h>
  17 #include <part.h>
  18 #include <malloc.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <fdt_support.h>
  22 #include <asm/io.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define SDHCI_IRQ_EN_BITS               (IRQSTATEN_CC | IRQSTATEN_TC | \
  27                                 IRQSTATEN_CINT | \
  28                                 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  29                                 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  30                                 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  31                                 IRQSTATEN_DINT)
  32
  33 struct fsl_esdhc {
  34         uint    dsaddr;         /* SDMA system address register */
  35         uint    blkattr;        /* Block attributes register */
  36         uint    cmdarg;         /* Command argument register */
  37         uint    xfertyp;        /* Transfer type register */
  38         uint    cmdrsp0;        /* Command response 0 register */
  39         uint    cmdrsp1;        /* Command response 1 register */
  40         uint    cmdrsp2;        /* Command response 2 register */
  41         uint    cmdrsp3;        /* Command response 3 register */
  42         uint    datport;        /* Buffer data port register */
  43         uint    prsstat;        /* Present state register */
  44         uint    proctl;         /* Protocol control register */
  45         uint    sysctl;         /* System Control Register */
  46         uint    irqstat;        /* Interrupt status register */
  47         uint    irqstaten;      /* Interrupt status enable register */
  48         uint    irqsigen;       /* Interrupt signal enable register */
  49         uint    autoc12err;     /* Auto CMD error status register */
  50         uint    hostcapblt;     /* Host controller capabilities register */
  51         uint    wml;            /* Watermark level register */
  52         uint    mixctrl;        /* For USDHC */
  53         char    reserved1[4];   /* reserved */
  54         uint    fevt;           /* Force event register */
  55         uint    admaes;         /* ADMA error status register */
  56         uint    adsaddr;        /* ADMA system address register */
  57         char    reserved2[100]; /* reserved */
  58         uint    vendorspec;     /* Vendor Specific register */
  59         char    reserved3[59];  /* reserved */
  60         uint    hostver;        /* Host controller version register */
  61         char    reserved4[4];   /* reserved */
  62         uint    dmaerraddr;     /* DMA error address register */
  63         char    reserved5[4];   /* reserved */
  64         uint    dmaerrattr;     /* DMA error attribute register */
  65         char    reserved6[4];   /* reserved */
  66         uint    hostcapblt2;    /* Host controller capabilities register 2 */
  67         char    reserved7[8];   /* reserved */
  68         uint    tcr;            /* Tuning control register */
  69         char    reserved8[28];  /* reserved */
  70         uint    sddirctl;       /* SD direction control register */
  71         char    reserved9[712]; /* reserved */
  72         uint    scr;            /* eSDHC control register */
  73 };
  74
  75 /* Return the XFERTYP flags for a given command and data packet */
  76 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  77 {
  78         uint xfertyp = 0;
  79
  80         if (data) {
  81                 xfertyp |= XFERTYP_DPSEL;
  82 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  83                 xfertyp |= XFERTYP_DMAEN;
  84 #endif
  85                 if (data->blocks > 1) {
  86                         xfertyp |= XFERTYP_MSBSEL;
  87                         xfertyp |= XFERTYP_BCEN;
  88 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  89                         xfertyp |= XFERTYP_AC12EN;
  90 #endif
  91                 }
  92
  93                 if (data->flags & MMC_DATA_READ)
  94                         xfertyp |= XFERTYP_DTDSEL;
  95         }
  96
  97         if (cmd->resp_type & MMC_RSP_CRC)
  98                 xfertyp |= XFERTYP_CCCEN;
  99         if (cmd->resp_type & MMC_RSP_OPCODE)
 100                 xfertyp |= XFERTYP_CICEN;
 101         if (cmd->resp_type & MMC_RSP_136)
 102                 xfertyp |= XFERTYP_RSPTYP_136;
 103         else if (cmd->resp_type & MMC_RSP_BUSY)
 104                 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
 105         else if (cmd->resp_type & MMC_RSP_PRESENT)
 106                 xfertyp |= XFERTYP_RSPTYP_48;
 107
 108 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102XA)
 109         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 110                 xfertyp |= XFERTYP_CMDTYP_ABORT;
 111 #endif
 112         return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 113 }
 114
 115 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 116 /*
 117  * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
 118  */
 119 static void
 120 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
 121 {
 122         struct fsl_esdhc_cfg *cfg = mmc->priv;
 123         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 124         uint blocks;
 125         char *buffer;
 126         uint databuf;
 127         uint size;
 128         uint irqstat;
 129         uint timeout;
 130
 131         if (data->flags & MMC_DATA_READ) {
 132                 blocks = data->blocks;
 133                 buffer = data->dest;
 134                 while (blocks) {
 135                         timeout = PIO_TIMEOUT;
 136                         size = data->blocksize;
 137                         irqstat = esdhc_read32(&regs->irqstat);
 138                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
 139                                 && --timeout);
 140                         if (timeout <= 0) {
 141                                 printf("\nData Read Failed in PIO Mode.");
 142                                 return;
 143                         }
 144                         while (size && (!(irqstat & IRQSTAT_TC))) {
 145                                 udelay(100); /* Wait before last byte transfer complete */
 146                                 irqstat = esdhc_read32(&regs->irqstat);
 147                                 databuf = in_le32(&regs->datport);
 148                                 *((uint *)buffer) = databuf;
 149                                 buffer += 4;
 150                                 size -= 4;
 151                         }
 152                         blocks--;
 153                 }
 154         } else {
 155                 blocks = data->blocks;
 156                 buffer = (char *)data->src;
 157                 while (blocks) {
 158                         timeout = PIO_TIMEOUT;
 159                         size = data->blocksize;
 160                         irqstat = esdhc_read32(&regs->irqstat);
 161                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
 162                                 && --timeout);
 163                         if (timeout <= 0) {
 164                                 printf("\nData Write Failed in PIO Mode.");
 165                                 return;
 166                         }
 167                         while (size && (!(irqstat & IRQSTAT_TC))) {
 168                                 udelay(100); /* Wait before last byte transfer complete */
 169                                 databuf = *((uint *)buffer);
 170                                 buffer += 4;
 171                                 size -= 4;
 172                                 irqstat = esdhc_read32(&regs->irqstat);
 173                                 out_le32(&regs->datport, databuf);
 174                         }
 175                         blocks--;
 176                 }
 177         }
 178 }
 179 #endif
 180
 181 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 182 {
 183         int timeout;
 184         struct fsl_esdhc_cfg *cfg = mmc->priv;
 185         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 186
 187         uint wml_value;
 188
 189         wml_value = data->blocksize/4;
 190
 191         if (data->flags & MMC_DATA_READ) {
 192                 if (wml_value > WML_RD_WML_MAX)
 193                         wml_value = WML_RD_WML_MAX_VAL;
 194
 195                 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 196 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 197                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 198 #endif
 199         } else {
 200 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 201                 flush_dcache_range((ulong)data->src,
 202                                    (ulong)data->src+data->blocks
 203                                          *data->blocksize);
 204 #endif
 205                 if (wml_value > WML_WR_WML_MAX)
 206                         wml_value = WML_WR_WML_MAX_VAL;
 207                 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
 208                         printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
 209                         return TIMEOUT;
 210                 }
 211
 212                 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 213                                         wml_value << 16);
 214 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 215                 esdhc_write32(&regs->dsaddr, (u32)data->src);
 216 #endif
 217         }
 218
 219         esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 220
 221         /* Calculate the timeout period for data transactions */
 222         /*
 223          * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
 224          * 2)Timeout period should be minimum 0.250sec as per SD Card spec
 225          *  So, Number of SD Clock cycles for 0.25sec should be minimum
 226          *              (SD Clock/sec * 0.25 sec) SD Clock cycles
 227          *              = (mmc->clock * 1/4) SD Clock cycles
 228          * As 1) >=  2)
 229          * => (2^(timeout+13)) >= mmc->clock * 1/4
 230          * Taking log2 both the sides
 231          * => timeout + 13 >= log2(mmc->clock/4)
 232          * Rounding up to next power of 2
 233          * => timeout + 13 = log2(mmc->clock/4) + 1
 234          * => timeout + 13 = fls(mmc->clock/4)
 235          */
 236         timeout = fls(mmc->clock/4);
 237         timeout -= 13;
 238
 239         if (timeout > 14)
 240                 timeout = 14;
 241
 242         if (timeout < 0)
 243                 timeout = 0;
 244
 245 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 246         if ((timeout == 4) || (timeout == 8) || (timeout == 12))
 247                 timeout++;
 248 #endif
 249
 250 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 251         timeout = 0xE;
 252 #endif
 253         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 254
 255         return 0;
 256 }
 257
 258 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 259 static void check_and_invalidate_dcache_range
 260         (struct mmc_cmd *cmd,
 261          struct mmc_data *data) {
 262         unsigned start = (unsigned)data->dest ;
 263         unsigned size = roundup(ARCH_DMA_MINALIGN,
 264                                 data->blocks*data->blocksize);
 265         unsigned end = start+size ;
 266         invalidate_dcache_range(start, end);
 267 }
 268 #endif
 269
 270 /*
 271  * Sends a command out on the bus.  Takes the mmc pointer,
 272  * a command pointer, and an optional data pointer.
 273  */
 274 static int
 275 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 276 {
 277         int     err = 0;
 278         uint    xfertyp;
 279         uint    irqstat;
 280         struct fsl_esdhc_cfg *cfg = mmc->priv;
 281         volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 282
 283 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 284         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 285                 return 0;
 286 #endif
 287
 288         esdhc_write32(&regs->irqstat, -1);
 289
 290         sync();
 291
 292         /* Wait for the bus to be idle */
 293         while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
 294                         (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
 295                 ;
 296
 297         while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
 298                 ;
 299
 300         /* Wait at least 8 SD clock cycles before the next command */
 301         /*
 302          * Note: This is way more than 8 cycles, but 1ms seems to
 303          * resolve timing issues with some cards
 304          */
 305         udelay(1000);
 306
 307         /* Set up for a data transfer if we have one */
 308         if (data) {
 309                 err = esdhc_setup_data(mmc, data);
 310                 if(err)
 311                         return err;
 312         }
 313
 314         /* Figure out the transfer arguments */
 315         xfertyp = esdhc_xfertyp(cmd, data);
 316
 317         /* Mask all irqs */
 318         esdhc_write32(&regs->irqsigen, 0);
 319
 320         /* Send the command */
 321         esdhc_write32(&regs->cmdarg, cmd->cmdarg);
 322 #if defined(CONFIG_FSL_USDHC)
 323         esdhc_write32(&regs->mixctrl,
 324         (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
 325                         | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
 326         esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 327 #else
 328         esdhc_write32(&regs->xfertyp, xfertyp);
 329 #endif
 330
 331         /* Wait for the command to complete */
 332         while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
 333                 ;
 334
 335         irqstat = esdhc_read32(&regs->irqstat);
 336
 337         if (irqstat & CMD_ERR) {
 338                 err = COMM_ERR;
 339                 goto out;
 340         }
 341
 342         if (irqstat & IRQSTAT_CTOE) {
 343                 err = TIMEOUT;
 344                 goto out;
 345         }
 346
 347         /* Switch voltage to 1.8V if CMD11 succeeded */
 348         if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
 349                 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 350
 351                 printf("Run CMD11 1.8V switch\n");
 352                 /* Sleep for 5 ms - max time for card to switch to 1.8V */
 353                 udelay(5000);
 354         }
 355
 356         /* Workaround for ESDHC errata ENGcm03648 */
 357         if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
 358                 int timeout = 2500;
 359
 360                 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
 361                 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
 362                                         PRSSTAT_DAT0)) {
 363                         udelay(100);
 364                         timeout--;
 365                 }
 366
 367                 if (timeout <= 0) {
 368                         printf("Timeout waiting for DAT0 to go high!\n");
 369                         err = TIMEOUT;
 370                         goto out;
 371                 }
 372         }
 373
 374         /* Copy the response to the response buffer */
 375         if (cmd->resp_type & MMC_RSP_136) {
 376                 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
 377
 378                 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
 379                 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
 380                 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
 381                 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
 382                 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
 383                 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
 384                 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
 385                 cmd->response[3] = (cmdrsp0 << 8);
 386         } else
 387                 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
 388
 389         /* Wait until all of the blocks are transferred */
 390         if (data) {
 391 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 392                 esdhc_pio_read_write(mmc, data);
 393 #else
 394                 do {
 395                         irqstat = esdhc_read32(&regs->irqstat);
 396
 397                         if (irqstat & IRQSTAT_DTOE) {
 398                                 err = TIMEOUT;
 399                                 goto out;
 400                         }
 401
 402                         if (irqstat & DATA_ERR) {
 403                                 err = COMM_ERR;
 404                                 goto out;
 405                         }
 406                 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 407
 408                 if (data->flags & MMC_DATA_READ)
 409                         check_and_invalidate_dcache_range(cmd, data);
 410 #endif
 411         }
 412
 413 out:
 414         /* Reset CMD and DATA portions on error */
 415         if (err) {
 416                 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
 417                               SYSCTL_RSTC);
 418                 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
 419                         ;
 420
 421                 if (data) {
 422                         esdhc_write32(&regs->sysctl,
 423                                       esdhc_read32(&regs->sysctl) |
 424                                       SYSCTL_RSTD);
 425                         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
 426                                 ;
 427                 }
 428
 429                 /* If this was CMD11, then notify that power cycle is needed */
 430                 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
 431                         printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
 432         }
 433
 434         esdhc_write32(&regs->irqstat, -1);
 435
 436         return err;
 437 }
 438
 439 static void set_sysctl(struct mmc *mmc, uint clock)
 440 {
 441         int div, pre_div;
 442         struct fsl_esdhc_cfg *cfg = mmc->priv;
 443         volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 444         int sdhc_clk = cfg->sdhc_clk;
 445         uint clk;
 446
 447         if (clock < mmc->cfg->f_min)
 448                 clock = mmc->cfg->f_min;
 449
 450         if (sdhc_clk / 16 > clock) {
 451                 for (pre_div = 2; pre_div < 256; pre_div *= 2)
 452                         if ((sdhc_clk / pre_div) <= (clock * 16))
 453                                 break;
 454         } else
 455                 pre_div = 2;
 456
 457         for (div = 1; div <= 16; div++)
 458                 if ((sdhc_clk / (div * pre_div)) <= clock)
 459                         break;
 460
 461         pre_div >>= mmc->ddr_mode ? 2 : 1;
 462         div -= 1;
 463
 464         clk = (pre_div << 8) | (div << 4);
 465
 466         esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
 467
 468         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 469
 470         udelay(10000);
 471
 472         clk = SYSCTL_PEREN | SYSCTL_CKEN;
 473
 474         esdhc_setbits32(&regs->sysctl, clk);
 475 }
 476
 477 static void esdhc_set_ios(struct mmc *mmc)
 478 {
 479         struct fsl_esdhc_cfg *cfg = mmc->priv;
 480         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 481
 482         /* Set the clock speed */
 483         set_sysctl(mmc, mmc->clock);
 484
 485         /* Set the bus width */
 486         esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
 487
 488         if (mmc->bus_width == 4)
 489                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
 490         else if (mmc->bus_width == 8)
 491                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
 492
 493 }
 494
 495 static int esdhc_init(struct mmc *mmc)
 496 {
 497         struct fsl_esdhc_cfg *cfg = mmc->priv;
 498         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 499         int timeout = 1000;
 500
 501         /* Reset the entire host controller */
 502         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 503
 504         /* Wait until the controller is available */
 505         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 506                 udelay(1000);
 507
 508 #ifndef ARCH_MXC
 509         /* Enable cache snooping */
 510         esdhc_write32(&regs->scr, 0x00000040);
 511 #endif
 512
 513         esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 514
 515         /* Set the initial clock speed */
 516         mmc_set_clock(mmc, 400000);
 517
 518         /* Disable the BRR and BWR bits in IRQSTAT */
 519         esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
 520
 521         /* Put the PROCTL reg back to the default */
 522         esdhc_write32(&regs->proctl, PROCTL_INIT);
 523
 524         /* Set timout to the maximum value */
 525         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 526
 527 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
 528         esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 529 #endif
 530
 531         return 0;
 532 }
 533
 534 static int esdhc_getcd(struct mmc *mmc)
 535 {
 536         struct fsl_esdhc_cfg *cfg = mmc->priv;
 537         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 538         int timeout = 1000;
 539
 540 #ifdef CONFIG_ESDHC_DETECT_QUIRK
 541         if (CONFIG_ESDHC_DETECT_QUIRK)
 542                 return 1;
 543 #endif
 544         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
 545                 udelay(1000);
 546
 547         return timeout > 0;
 548 }
 549
 550 static void esdhc_reset(struct fsl_esdhc *regs)
 551 {
 552         unsigned long timeout = 100; /* wait max 100 ms */
 553
 554         /* reset the controller */
 555         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 556
 557         /* hardware clears the bit when it is done */
 558         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 559                 udelay(1000);
 560         if (!timeout)
 561                 printf("MMC/SD: Reset never completed.\n");
 562 }
 563
 564 static const struct mmc_ops esdhc_ops = {
 565         .send_cmd       = esdhc_send_cmd,
 566         .set_ios        = esdhc_set_ios,
 567         .init           = esdhc_init,
 568         .getcd          = esdhc_getcd,
 569 };
 570
 571 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 572 {
 573         struct fsl_esdhc *regs;
 574         struct mmc *mmc;
 575         u32 caps, voltage_caps;
 576
 577         if (!cfg)
 578                 return -1;
 579
 580         regs = (struct fsl_esdhc *)cfg->esdhc_base;
 581
 582         /* First reset the eSDHC controller */
 583         esdhc_reset(regs);
 584
 585         esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 586                                 | SYSCTL_IPGEN | SYSCTL_CKEN);
 587
 588         writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
 589         memset(&cfg->cfg, 0, sizeof(cfg->cfg));
 590
 591         voltage_caps = 0;
 592         caps = esdhc_read32(&regs->hostcapblt);
 593
 594 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 595         caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
 596                         ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
 597 #endif
 598
 599 /* T4240 host controller capabilities register should have VS33 bit */
 600 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 601         caps = caps | ESDHC_HOSTCAPBLT_VS33;
 602 #endif
 603
 604         if (caps & ESDHC_HOSTCAPBLT_VS18)
 605                 voltage_caps |= MMC_VDD_165_195;
 606         if (caps & ESDHC_HOSTCAPBLT_VS30)
 607                 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
 608         if (caps & ESDHC_HOSTCAPBLT_VS33)
 609                 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
 610
 611         cfg->cfg.name = "FSL_SDHC";
 612         cfg->cfg.ops = &esdhc_ops;
 613 #ifdef CONFIG_SYS_SD_VOLTAGE
 614         cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
 615 #else
 616         cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 617 #endif
 618         if ((cfg->cfg.voltages & voltage_caps) == 0) {
 619                 printf("voltage not supported by controller\n");
 620                 return -1;
 621         }
 622
 623         cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
 624 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 625         cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
 626 #endif
 627
 628         if (cfg->max_bus_width > 0) {
 629                 if (cfg->max_bus_width < 8)
 630                         cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
 631                 if (cfg->max_bus_width < 4)
 632                         cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
 633         }
 634
 635         if (caps & ESDHC_HOSTCAPBLT_HSS)
 636                 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 637
 638 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
 639         if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
 640                 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
 641 #endif
 642
 643         cfg->cfg.f_min = 400000;
 644         cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
 645
 646         cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 647
 648         mmc = mmc_create(&cfg->cfg, cfg);
 649         if (mmc == NULL)
 650                 return -1;
 651
 652         return 0;
 653 }
 654
 655 int fsl_esdhc_mmc_init(bd_t *bis)
 656 {
 657         struct fsl_esdhc_cfg *cfg;
 658
 659         cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
 660         cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
 661         cfg->sdhc_clk = gd->arch.sdhc_clk;
 662         return fsl_esdhc_initialize(bis, cfg);
 663 }
 664
 665 #ifdef CONFIG_OF_LIBFDT
 666 void fdt_fixup_esdhc(void *blob, bd_t *bd)
 667 {
 668         const char *compat = "fsl,esdhc";
 669
 670 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
 671         if (!hwconfig("esdhc")) {
 672                 do_fixup_by_compat(blob, compat, "status", "disabled",
 673                                 8 + 1, 1);
 674                 return;
 675         }
 676 #endif
 677
 678         do_fixup_by_compat_u32(blob, compat, "clock-frequency",
 679                                gd->arch.sdhc_clk, 1);
 680
 681         do_fixup_by_compat(blob, compat, "status", "okay",
 682                            4 + 1, 1);
 683 }
 684 #endif