drivers/mmc/fsl_esdhc.c

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based vaguely on the pxa mmc code:
   6  * (C) Copyright 2003
   7  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <command.h>
  15 #include <errno.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <part.h>
  19 #include <power/regulator.h>
  20 #include <malloc.h>
  21 #include <fsl_esdhc.h>
  22 #include <fdt_support.h>
  23 #include <asm/io.h>
  24 #include <dm.h>
  25 #include <asm-generic/gpio.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define SDHCI_IRQ_EN_BITS               (IRQSTATEN_CC | IRQSTATEN_TC | \
  30                                 IRQSTATEN_CINT | \
  31                                 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  32                                 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  33                                 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  34                                 IRQSTATEN_DINT)
  35
  36 struct fsl_esdhc {
  37         uint    dsaddr;         /* SDMA system address register */
  38         uint    blkattr;        /* Block attributes register */
  39         uint    cmdarg;         /* Command argument register */
  40         uint    xfertyp;        /* Transfer type register */
  41         uint    cmdrsp0;        /* Command response 0 register */
  42         uint    cmdrsp1;        /* Command response 1 register */
  43         uint    cmdrsp2;        /* Command response 2 register */
  44         uint    cmdrsp3;        /* Command response 3 register */
  45         uint    datport;        /* Buffer data port register */
  46         uint    prsstat;        /* Present state register */
  47         uint    proctl;         /* Protocol control register */
  48         uint    sysctl;         /* System Control Register */
  49         uint    irqstat;        /* Interrupt status register */
  50         uint    irqstaten;      /* Interrupt status enable register */
  51         uint    irqsigen;       /* Interrupt signal enable register */
  52         uint    autoc12err;     /* Auto CMD error status register */
  53         uint    hostcapblt;     /* Host controller capabilities register */
  54         uint    wml;            /* Watermark level register */
  55         uint    mixctrl;        /* For USDHC */
  56         char    reserved1[4];   /* reserved */
  57         uint    fevt;           /* Force event register */
  58         uint    admaes;         /* ADMA error status register */
  59         uint    adsaddr;        /* ADMA system address register */
  60         char    reserved2[4];
  61         uint    dllctrl;
  62         uint    dllstat;
  63         uint    clktunectrlstatus;
  64         char    reserved3[84];
  65         uint    vendorspec;
  66         uint    mmcboot;
  67         uint    vendorspec2;
  68         char    reserved4[48];
  69         uint    hostver;        /* Host controller version register */
  70         char    reserved5[4];   /* reserved */
  71         uint    dmaerraddr;     /* DMA error address register */
  72         char    reserved6[4];   /* reserved */
  73         uint    dmaerrattr;     /* DMA error attribute register */
  74         char    reserved7[4];   /* reserved */
  75         uint    hostcapblt2;    /* Host controller capabilities register 2 */
  76         char    reserved8[8];   /* reserved */
  77         uint    tcr;            /* Tuning control register */
  78         char    reserved9[28];  /* reserved */
  79         uint    sddirctl;       /* SD direction control register */
  80         char    reserved10[712];/* reserved */
  81         uint    scr;            /* eSDHC control register */
  82 };
  83
  84 struct fsl_esdhc_plat {
  85         struct mmc_config cfg;
  86         struct mmc mmc;
  87 };
  88
  89 /**
  90  * struct fsl_esdhc_priv
  91  *
  92  * @esdhc_regs: registers of the sdhc controller
  93  * @sdhc_clk: Current clk of the sdhc controller
  94  * @bus_width: bus width, 1bit, 4bit or 8bit
  95  * @cfg: mmc config
  96  * @mmc: mmc
  97  * Following is used when Driver Model is enabled for MMC
  98  * @dev: pointer for the device
  99  * @non_removable: 0: removable; 1: non-removable
 100  * @wp_enable: 1: enable checking wp; 0: no check
 101  * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
 102  * @cd_gpio: gpio for card detection
 103  * @wp_gpio: gpio for write protection
 104  */
 105 struct fsl_esdhc_priv {
 106         struct fsl_esdhc *esdhc_regs;
 107         unsigned int sdhc_clk;
 108         unsigned int bus_width;
 109 #if !CONFIG_IS_ENABLED(BLK)
 110         struct mmc *mmc;
 111 #endif
 112         struct udevice *dev;
 113         int non_removable;
 114         int wp_enable;
 115         int vs18_enable;
 116 #ifdef CONFIG_DM_GPIO
 117         struct gpio_desc cd_gpio;
 118         struct gpio_desc wp_gpio;
 119 #endif
 120 };
 121
 122 /* Return the XFERTYP flags for a given command and data packet */
 123 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 124 {
 125         uint xfertyp = 0;
 126
 127         if (data) {
 128                 xfertyp |= XFERTYP_DPSEL;
 129 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 130                 xfertyp |= XFERTYP_DMAEN;
 131 #endif
 132                 if (data->blocks > 1) {
 133                         xfertyp |= XFERTYP_MSBSEL;
 134                         xfertyp |= XFERTYP_BCEN;
 135 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 136                         xfertyp |= XFERTYP_AC12EN;
 137 #endif
 138                 }
 139
 140                 if (data->flags & MMC_DATA_READ)
 141                         xfertyp |= XFERTYP_DTDSEL;
 142         }
 143
 144         if (cmd->resp_type & MMC_RSP_CRC)
 145                 xfertyp |= XFERTYP_CCCEN;
 146         if (cmd->resp_type & MMC_RSP_OPCODE)
 147                 xfertyp |= XFERTYP_CICEN;
 148         if (cmd->resp_type & MMC_RSP_136)
 149                 xfertyp |= XFERTYP_RSPTYP_136;
 150         else if (cmd->resp_type & MMC_RSP_BUSY)
 151                 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
 152         else if (cmd->resp_type & MMC_RSP_PRESENT)
 153                 xfertyp |= XFERTYP_RSPTYP_48;
 154
 155         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 156                 xfertyp |= XFERTYP_CMDTYP_ABORT;
 157
 158         return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 159 }
 160
 161 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 162 /*
 163  * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
 164  */
 165 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
 166                                  struct mmc_data *data)
 167 {
 168         struct fsl_esdhc *regs = priv->esdhc_regs;
 169         uint blocks;
 170         char *buffer;
 171         uint databuf;
 172         uint size;
 173         uint irqstat;
 174         ulong start;
 175
 176         if (data->flags & MMC_DATA_READ) {
 177                 blocks = data->blocks;
 178                 buffer = data->dest;
 179                 while (blocks) {
 180                         start = get_timer(0);
 181                         size = data->blocksize;
 182                         irqstat = esdhc_read32(&regs->irqstat);
 183                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
 184                                 if (get_timer(start) > PIO_TIMEOUT) {
 185                                         printf("\nData Read Failed in PIO Mode.");
 186                                         return;
 187                                 }
 188                         }
 189                         while (size && (!(irqstat & IRQSTAT_TC))) {
 190                                 udelay(100); /* Wait before last byte transfer complete */
 191                                 irqstat = esdhc_read32(&regs->irqstat);
 192                                 databuf = in_le32(&regs->datport);
 193                                 *((uint *)buffer) = databuf;
 194                                 buffer += 4;
 195                                 size -= 4;
 196                         }
 197                         blocks--;
 198                 }
 199         } else {
 200                 blocks = data->blocks;
 201                 buffer = (char *)data->src;
 202                 while (blocks) {
 203                         start = get_timer(0);
 204                         size = data->blocksize;
 205                         irqstat = esdhc_read32(&regs->irqstat);
 206                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
 207                                 if (get_timer(start) > PIO_TIMEOUT) {
 208                                         printf("\nData Write Failed in PIO Mode.");
 209                                         return;
 210                                 }
 211                         }
 212                         while (size && (!(irqstat & IRQSTAT_TC))) {
 213                                 udelay(100); /* Wait before last byte transfer complete */
 214                                 databuf = *((uint *)buffer);
 215                                 buffer += 4;
 216                                 size -= 4;
 217                                 irqstat = esdhc_read32(&regs->irqstat);
 218                                 out_le32(&regs->datport, databuf);
 219                         }
 220                         blocks--;
 221                 }
 222         }
 223 }
 224 #endif
 225
 226 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 227                             struct mmc_data *data)
 228 {
 229         int timeout;
 230         struct fsl_esdhc *regs = priv->esdhc_regs;
 231 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
 232         dma_addr_t addr;
 233 #endif
 234         uint wml_value;
 235
 236         wml_value = data->blocksize/4;
 237
 238         if (data->flags & MMC_DATA_READ) {
 239                 if (wml_value > WML_RD_WML_MAX)
 240                         wml_value = WML_RD_WML_MAX_VAL;
 241
 242                 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 243 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 244 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
 245                 addr = virt_to_phys((void *)(data->dest));
 246                 if (upper_32_bits(addr))
 247                         printf("Error found for upper 32 bits\n");
 248                 else
 249                         esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
 250 #else
 251                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 252 #endif
 253 #endif
 254         } else {
 255 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 256                 flush_dcache_range((ulong)data->src,
 257                                    (ulong)data->src+data->blocks
 258                                          *data->blocksize);
 259 #endif
 260                 if (wml_value > WML_WR_WML_MAX)
 261                         wml_value = WML_WR_WML_MAX_VAL;
 262                 if (priv->wp_enable) {
 263                         if ((esdhc_read32(&regs->prsstat) &
 264                             PRSSTAT_WPSPL) == 0) {
 265                                 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
 266                                 return -ETIMEDOUT;
 267                         }
 268                 }
 269
 270                 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 271                                         wml_value << 16);
 272 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 273 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
 274                 addr = virt_to_phys((void *)(data->src));
 275                 if (upper_32_bits(addr))
 276                         printf("Error found for upper 32 bits\n");
 277                 else
 278                         esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
 279 #else
 280                 esdhc_write32(&regs->dsaddr, (u32)data->src);
 281 #endif
 282 #endif
 283         }
 284
 285         esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 286
 287         /* Calculate the timeout period for data transactions */
 288         /*
 289          * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
 290          * 2)Timeout period should be minimum 0.250sec as per SD Card spec
 291          *  So, Number of SD Clock cycles for 0.25sec should be minimum
 292          *              (SD Clock/sec * 0.25 sec) SD Clock cycles
 293          *              = (mmc->clock * 1/4) SD Clock cycles
 294          * As 1) >=  2)
 295          * => (2^(timeout+13)) >= mmc->clock * 1/4
 296          * Taking log2 both the sides
 297          * => timeout + 13 >= log2(mmc->clock/4)
 298          * Rounding up to next power of 2
 299          * => timeout + 13 = log2(mmc->clock/4) + 1
 300          * => timeout + 13 = fls(mmc->clock/4)
 301          *
 302          * However, the MMC spec "It is strongly recommended for hosts to
 303          * implement more than 500ms timeout value even if the card
 304          * indicates the 250ms maximum busy length."  Even the previous
 305          * value of 300ms is known to be insufficient for some cards.
 306          * So, we use
 307          * => timeout + 13 = fls(mmc->clock/2)
 308          */
 309         timeout = fls(mmc->clock/2);
 310         timeout -= 13;
 311
 312         if (timeout > 14)
 313                 timeout = 14;
 314
 315         if (timeout < 0)
 316                 timeout = 0;
 317
 318 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 319         if ((timeout == 4) || (timeout == 8) || (timeout == 12))
 320                 timeout++;
 321 #endif
 322
 323 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 324         timeout = 0xE;
 325 #endif
 326         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 327
 328         return 0;
 329 }
 330
 331 static void check_and_invalidate_dcache_range
 332         (struct mmc_cmd *cmd,
 333          struct mmc_data *data) {
 334         unsigned start = 0;
 335         unsigned end = 0;
 336         unsigned size = roundup(ARCH_DMA_MINALIGN,
 337                                 data->blocks*data->blocksize);
 338 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
 339         dma_addr_t addr;
 340
 341         addr = virt_to_phys((void *)(data->dest));
 342         if (upper_32_bits(addr))
 343                 printf("Error found for upper 32 bits\n");
 344         else
 345                 start = lower_32_bits(addr);
 346 #else
 347         start = (unsigned)data->dest;
 348 #endif
 349         end = start + size;
 350         invalidate_dcache_range(start, end);
 351 }
 352
 353 /*
 354  * Sends a command out on the bus.  Takes the mmc pointer,
 355  * a command pointer, and an optional data pointer.
 356  */
 357 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 358                                  struct mmc_cmd *cmd, struct mmc_data *data)
 359 {
 360         int     err = 0;
 361         uint    xfertyp;
 362         uint    irqstat;
 363         struct fsl_esdhc *regs = priv->esdhc_regs;
 364
 365 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 366         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 367                 return 0;
 368 #endif
 369
 370         esdhc_write32(&regs->irqstat, -1);
 371
 372         sync();
 373
 374         /* Wait for the bus to be idle */
 375         while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
 376                         (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
 377                 ;
 378
 379         while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
 380                 ;
 381
 382         /* Wait at least 8 SD clock cycles before the next command */
 383         /*
 384          * Note: This is way more than 8 cycles, but 1ms seems to
 385          * resolve timing issues with some cards
 386          */
 387         udelay(1000);
 388
 389         /* Set up for a data transfer if we have one */
 390         if (data) {
 391                 err = esdhc_setup_data(priv, mmc, data);
 392                 if(err)
 393                         return err;
 394
 395                 if (data->flags & MMC_DATA_READ)
 396                         check_and_invalidate_dcache_range(cmd, data);
 397         }
 398
 399         /* Figure out the transfer arguments */
 400         xfertyp = esdhc_xfertyp(cmd, data);
 401
 402         /* Mask all irqs */
 403         esdhc_write32(&regs->irqsigen, 0);
 404
 405         /* Send the command */
 406         esdhc_write32(&regs->cmdarg, cmd->cmdarg);
 407 #if defined(CONFIG_FSL_USDHC)
 408         esdhc_write32(&regs->mixctrl,
 409         (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
 410                         | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
 411         esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 412 #else
 413         esdhc_write32(&regs->xfertyp, xfertyp);
 414 #endif
 415
 416         /* Wait for the command to complete */
 417         while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
 418                 ;
 419
 420         irqstat = esdhc_read32(&regs->irqstat);
 421
 422         if (irqstat & CMD_ERR) {
 423                 err = -ECOMM;
 424                 goto out;
 425         }
 426
 427         if (irqstat & IRQSTAT_CTOE) {
 428                 err = -ETIMEDOUT;
 429                 goto out;
 430         }
 431
 432         /* Switch voltage to 1.8V if CMD11 succeeded */
 433         if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
 434                 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 435
 436                 printf("Run CMD11 1.8V switch\n");
 437                 /* Sleep for 5 ms - max time for card to switch to 1.8V */
 438                 udelay(5000);
 439         }
 440
 441         /* Workaround for ESDHC errata ENGcm03648 */
 442         if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
 443                 int timeout = 6000;
 444
 445                 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
 446                 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
 447                                         PRSSTAT_DAT0)) {
 448                         udelay(100);
 449                         timeout--;
 450                 }
 451
 452                 if (timeout <= 0) {
 453                         printf("Timeout waiting for DAT0 to go high!\n");
 454                         err = -ETIMEDOUT;
 455                         goto out;
 456                 }
 457         }
 458
 459         /* Copy the response to the response buffer */
 460         if (cmd->resp_type & MMC_RSP_136) {
 461                 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
 462
 463                 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
 464                 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
 465                 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
 466                 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
 467                 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
 468                 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
 469                 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
 470                 cmd->response[3] = (cmdrsp0 << 8);
 471         } else
 472                 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
 473
 474         /* Wait until all of the blocks are transferred */
 475         if (data) {
 476 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 477                 esdhc_pio_read_write(priv, data);
 478 #else
 479                 do {
 480                         irqstat = esdhc_read32(&regs->irqstat);
 481
 482                         if (irqstat & IRQSTAT_DTOE) {
 483                                 err = -ETIMEDOUT;
 484                                 goto out;
 485                         }
 486
 487                         if (irqstat & DATA_ERR) {
 488                                 err = -ECOMM;
 489                                 goto out;
 490                         }
 491                 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 492
 493                 /*
 494                  * Need invalidate the dcache here again to avoid any
 495                  * cache-fill during the DMA operations such as the
 496                  * speculative pre-fetching etc.
 497                  */
 498                 if (data->flags & MMC_DATA_READ)
 499                         check_and_invalidate_dcache_range(cmd, data);
 500 #endif
 501         }
 502
 503 out:
 504         /* Reset CMD and DATA portions on error */
 505         if (err) {
 506                 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
 507                               SYSCTL_RSTC);
 508                 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
 509                         ;
 510
 511                 if (data) {
 512                         esdhc_write32(&regs->sysctl,
 513                                       esdhc_read32(&regs->sysctl) |
 514                                       SYSCTL_RSTD);
 515                         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
 516                                 ;
 517                 }
 518
 519                 /* If this was CMD11, then notify that power cycle is needed */
 520                 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
 521                         printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
 522         }
 523
 524         esdhc_write32(&regs->irqstat, -1);
 525
 526         return err;
 527 }
 528
 529 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
 530 {
 531         int div = 1;
 532 #ifdef ARCH_MXC
 533         int pre_div = 1;
 534 #else
 535         int pre_div = 2;
 536 #endif
 537         int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
 538         struct fsl_esdhc *regs = priv->esdhc_regs;
 539         int sdhc_clk = priv->sdhc_clk;
 540         uint clk;
 541
 542         if (clock < mmc->cfg->f_min)
 543                 clock = mmc->cfg->f_min;
 544
 545         while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
 546                 pre_div *= 2;
 547
 548         while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
 549                 div++;
 550
 551         pre_div >>= 1;
 552         div -= 1;
 553
 554         clk = (pre_div << 8) | (div << 4);
 555
 556 #ifdef CONFIG_FSL_USDHC
 557         esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
 558 #else
 559         esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
 560 #endif
 561
 562         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 563
 564         udelay(10000);
 565
 566 #ifdef CONFIG_FSL_USDHC
 567         esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
 568 #else
 569         esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
 570 #endif
 571
 572 }
 573
 574 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 575 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
 576 {
 577         struct fsl_esdhc *regs = priv->esdhc_regs;
 578         u32 value;
 579         u32 time_out;
 580
 581         value = esdhc_read32(&regs->sysctl);
 582
 583         if (enable)
 584                 value |= SYSCTL_CKEN;
 585         else
 586                 value &= ~SYSCTL_CKEN;
 587
 588         esdhc_write32(&regs->sysctl, value);
 589
 590         time_out = 20;
 591         value = PRSSTAT_SDSTB;
 592         while (!(esdhc_read32(&regs->prsstat) & value)) {
 593                 if (time_out == 0) {
 594                         printf("fsl_esdhc: Internal clock never stabilised.\n");
 595                         break;
 596                 }
 597                 time_out--;
 598                 mdelay(1);
 599         }
 600 }
 601 #endif
 602
 603 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 604 {
 605         struct fsl_esdhc *regs = priv->esdhc_regs;
 606
 607 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 608         /* Select to use peripheral clock */
 609         esdhc_clock_control(priv, false);
 610         esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
 611         esdhc_clock_control(priv, true);
 612 #endif
 613         /* Set the clock speed */
 614         set_sysctl(priv, mmc, mmc->clock);
 615
 616         /* Set the bus width */
 617         esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
 618
 619         if (mmc->bus_width == 4)
 620                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
 621         else if (mmc->bus_width == 8)
 622                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
 623
 624         return 0;
 625 }
 626
 627 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 628 {
 629         struct fsl_esdhc *regs = priv->esdhc_regs;
 630         ulong start;
 631
 632         /* Reset the entire host controller */
 633         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 634
 635         /* Wait until the controller is available */
 636         start = get_timer(0);
 637         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
 638                 if (get_timer(start) > 1000)
 639                         return -ETIMEDOUT;
 640         }
 641
 642 #if defined(CONFIG_FSL_USDHC)
 643         /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
 644         esdhc_write32(&regs->mmcboot, 0x0);
 645         /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
 646         esdhc_write32(&regs->mixctrl, 0x0);
 647         esdhc_write32(&regs->clktunectrlstatus, 0x0);
 648
 649         /* Put VEND_SPEC to default value */
 650         if (priv->vs18_enable)
 651                 esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
 652                               ESDHC_VENDORSPEC_VSELECT));
 653         else
 654                 esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
 655
 656         /* Disable DLL_CTRL delay line */
 657         esdhc_write32(&regs->dllctrl, 0x0);
 658 #endif
 659
 660 #ifndef ARCH_MXC
 661         /* Enable cache snooping */
 662         esdhc_write32(&regs->scr, 0x00000040);
 663 #endif
 664
 665 #ifndef CONFIG_FSL_USDHC
 666         esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 667 #else
 668         esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
 669 #endif
 670
 671         /* Set the initial clock speed */
 672         mmc_set_clock(mmc, 400000, false);
 673
 674         /* Disable the BRR and BWR bits in IRQSTAT */
 675         esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
 676
 677         /* Put the PROCTL reg back to the default */
 678         esdhc_write32(&regs->proctl, PROCTL_INIT);
 679
 680         /* Set timout to the maximum value */
 681         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 682
 683         return 0;
 684 }
 685
 686 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
 687 {
 688         struct fsl_esdhc *regs = priv->esdhc_regs;
 689         int timeout = 1000;
 690
 691 #ifdef CONFIG_ESDHC_DETECT_QUIRK
 692         if (CONFIG_ESDHC_DETECT_QUIRK)
 693                 return 1;
 694 #endif
 695
 696 #if CONFIG_IS_ENABLED(DM_MMC)
 697         if (priv->non_removable)
 698                 return 1;
 699 #ifdef CONFIG_DM_GPIO
 700         if (dm_gpio_is_valid(&priv->cd_gpio))
 701                 return dm_gpio_get_value(&priv->cd_gpio);
 702 #endif
 703 #endif
 704
 705         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
 706                 udelay(1000);
 707
 708         return timeout > 0;
 709 }
 710
 711 static int esdhc_reset(struct fsl_esdhc *regs)
 712 {
 713         ulong start;
 714
 715         /* reset the controller */
 716         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 717
 718         /* hardware clears the bit when it is done */
 719         start = get_timer(0);
 720         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
 721                 if (get_timer(start) > 100) {
 722                         printf("MMC/SD: Reset never completed.\n");
 723                         return -ETIMEDOUT;
 724                 }
 725         }
 726
 727         return 0;
 728 }
 729
 730 #if !CONFIG_IS_ENABLED(DM_MMC)
 731 static int esdhc_getcd(struct mmc *mmc)
 732 {
 733         struct fsl_esdhc_priv *priv = mmc->priv;
 734
 735         return esdhc_getcd_common(priv);
 736 }
 737
 738 static int esdhc_init(struct mmc *mmc)
 739 {
 740         struct fsl_esdhc_priv *priv = mmc->priv;
 741
 742         return esdhc_init_common(priv, mmc);
 743 }
 744
 745 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 746                           struct mmc_data *data)
 747 {
 748         struct fsl_esdhc_priv *priv = mmc->priv;
 749
 750         return esdhc_send_cmd_common(priv, mmc, cmd, data);
 751 }
 752
 753 static int esdhc_set_ios(struct mmc *mmc)
 754 {
 755         struct fsl_esdhc_priv *priv = mmc->priv;
 756
 757         return esdhc_set_ios_common(priv, mmc);
 758 }
 759
 760 static const struct mmc_ops esdhc_ops = {
 761         .getcd          = esdhc_getcd,
 762         .init           = esdhc_init,
 763         .send_cmd       = esdhc_send_cmd,
 764         .set_ios        = esdhc_set_ios,
 765 };
 766 #endif
 767
 768 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
 769                           struct fsl_esdhc_plat *plat)
 770 {
 771         struct mmc_config *cfg;
 772         struct fsl_esdhc *regs;
 773         u32 caps, voltage_caps;
 774         int ret;
 775
 776         if (!priv)
 777                 return -EINVAL;
 778
 779         regs = priv->esdhc_regs;
 780
 781         /* First reset the eSDHC controller */
 782         ret = esdhc_reset(regs);
 783         if (ret)
 784                 return ret;
 785
 786 #ifndef CONFIG_FSL_USDHC
 787         esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 788                                 | SYSCTL_IPGEN | SYSCTL_CKEN);
 789 #else
 790         esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
 791                         VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
 792 #endif
 793
 794         if (priv->vs18_enable)
 795                 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 796
 797         writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
 798         cfg = &plat->cfg;
 799 #ifndef CONFIG_DM_MMC
 800         memset(cfg, '\0', sizeof(*cfg));
 801 #endif
 802
 803         voltage_caps = 0;
 804         caps = esdhc_read32(&regs->hostcapblt);
 805
 806 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 807         caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
 808                         ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
 809 #endif
 810
 811 /* T4240 host controller capabilities register should have VS33 bit */
 812 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 813         caps = caps | ESDHC_HOSTCAPBLT_VS33;
 814 #endif
 815
 816         if (caps & ESDHC_HOSTCAPBLT_VS18)
 817                 voltage_caps |= MMC_VDD_165_195;
 818         if (caps & ESDHC_HOSTCAPBLT_VS30)
 819                 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
 820         if (caps & ESDHC_HOSTCAPBLT_VS33)
 821                 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
 822
 823         cfg->name = "FSL_SDHC";
 824 #if !CONFIG_IS_ENABLED(DM_MMC)
 825         cfg->ops = &esdhc_ops;
 826 #endif
 827 #ifdef CONFIG_SYS_SD_VOLTAGE
 828         cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
 829 #else
 830         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 831 #endif
 832         if ((cfg->voltages & voltage_caps) == 0) {
 833                 printf("voltage not supported by controller\n");
 834                 return -1;
 835         }
 836
 837         if (priv->bus_width == 8)
 838                 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 839         else if (priv->bus_width == 4)
 840                 cfg->host_caps = MMC_MODE_4BIT;
 841
 842         cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 843 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 844         cfg->host_caps |= MMC_MODE_DDR_52MHz;
 845 #endif
 846
 847         if (priv->bus_width > 0) {
 848                 if (priv->bus_width < 8)
 849                         cfg->host_caps &= ~MMC_MODE_8BIT;
 850                 if (priv->bus_width < 4)
 851                         cfg->host_caps &= ~MMC_MODE_4BIT;
 852         }
 853
 854         if (caps & ESDHC_HOSTCAPBLT_HSS)
 855                 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 856
 857 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
 858         if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
 859                 cfg->host_caps &= ~MMC_MODE_8BIT;
 860 #endif
 861
 862         cfg->f_min = 400000;
 863         cfg->f_max = min(priv->sdhc_clk, (u32)52000000);
 864
 865         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 866
 867         return 0;
 868 }
 869
 870 #if !CONFIG_IS_ENABLED(DM_MMC)
 871 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
 872                                  struct fsl_esdhc_priv *priv)
 873 {
 874         if (!cfg || !priv)
 875                 return -EINVAL;
 876
 877         priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
 878         priv->bus_width = cfg->max_bus_width;
 879         priv->sdhc_clk = cfg->sdhc_clk;
 880         priv->wp_enable  = cfg->wp_enable;
 881         priv->vs18_enable  = cfg->vs18_enable;
 882
 883         return 0;
 884 };
 885
 886 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 887 {
 888         struct fsl_esdhc_plat *plat;
 889         struct fsl_esdhc_priv *priv;
 890         struct mmc *mmc;
 891         int ret;
 892
 893         if (!cfg)
 894                 return -EINVAL;
 895
 896         priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
 897         if (!priv)
 898                 return -ENOMEM;
 899         plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
 900         if (!plat) {
 901                 free(priv);
 902                 return -ENOMEM;
 903         }
 904
 905         ret = fsl_esdhc_cfg_to_priv(cfg, priv);
 906         if (ret) {
 907                 debug("%s xlate failure\n", __func__);
 908                 free(plat);
 909                 free(priv);
 910                 return ret;
 911         }
 912
 913         ret = fsl_esdhc_init(priv, plat);
 914         if (ret) {
 915                 debug("%s init failure\n", __func__);
 916                 free(plat);
 917                 free(priv);
 918                 return ret;
 919         }
 920
 921         mmc = mmc_create(&plat->cfg, priv);
 922         if (!mmc)
 923                 return -EIO;
 924
 925         priv->mmc = mmc;
 926
 927         return 0;
 928 }
 929
 930 int fsl_esdhc_mmc_init(bd_t *bis)
 931 {
 932         struct fsl_esdhc_cfg *cfg;
 933
 934         cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
 935         cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
 936         cfg->sdhc_clk = gd->arch.sdhc_clk;
 937         return fsl_esdhc_initialize(bis, cfg);
 938 }
 939 #endif
 940
 941 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
 942 void mmc_adapter_card_type_ident(void)
 943 {
 944         u8 card_id;
 945         u8 value;
 946
 947         card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
 948         gd->arch.sdhc_adapter = card_id;
 949
 950         switch (card_id) {
 951         case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
 952                 value = QIXIS_READ(brdcfg[5]);
 953                 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
 954                 QIXIS_WRITE(brdcfg[5], value);
 955                 break;
 956         case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
 957                 value = QIXIS_READ(pwr_ctl[1]);
 958                 value |= QIXIS_EVDD_BY_SDHC_VS;
 959                 QIXIS_WRITE(pwr_ctl[1], value);
 960                 break;
 961         case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
 962                 value = QIXIS_READ(brdcfg[5]);
 963                 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
 964                 QIXIS_WRITE(brdcfg[5], value);
 965                 break;
 966         case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
 967                 break;
 968         case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
 969                 break;
 970         case QIXIS_ESDHC_ADAPTER_TYPE_SD:
 971                 break;
 972         case QIXIS_ESDHC_NO_ADAPTER:
 973                 break;
 974         default:
 975                 break;
 976         }
 977 }
 978 #endif
 979
 980 #ifdef CONFIG_OF_LIBFDT
 981 __weak int esdhc_status_fixup(void *blob, const char *compat)
 982 {
 983 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
 984         if (!hwconfig("esdhc")) {
 985                 do_fixup_by_compat(blob, compat, "status", "disabled",
 986                                 sizeof("disabled"), 1);
 987                 return 1;
 988         }
 989 #endif
 990         return 0;
 991 }
 992
 993 void fdt_fixup_esdhc(void *blob, bd_t *bd)
 994 {
 995         const char *compat = "fsl,esdhc";
 996
 997         if (esdhc_status_fixup(blob, compat))
 998                 return;
 999
1000 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1001         do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1002                                gd->arch.sdhc_clk, 1);
1003 #else
1004         do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1005                                gd->arch.sdhc_clk, 1);
1006 #endif
1007 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1008         do_fixup_by_compat_u32(blob, compat, "adapter-type",
1009                                (u32)(gd->arch.sdhc_adapter), 1);
1010 #endif
1011 }
1012 #endif
1013
1014 #if CONFIG_IS_ENABLED(DM_MMC)
1015 #include <asm/arch/clock.h>
1016 __weak void init_clk_usdhc(u32 index)
1017 {
1018 }
1019
1020 static int fsl_esdhc_probe(struct udevice *dev)
1021 {
1022         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1023         struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1024         struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1025 #ifdef CONFIG_DM_REGULATOR
1026         struct udevice *vqmmc_dev;
1027 #endif
1028         fdt_addr_t addr;
1029         unsigned int val;
1030         struct mmc *mmc;
1031         int ret;
1032
1033         addr = dev_read_addr(dev);
1034         if (addr == FDT_ADDR_T_NONE)
1035                 return -EINVAL;
1036
1037         priv->esdhc_regs = (struct fsl_esdhc *)addr;
1038         priv->dev = dev;
1039
1040         val = dev_read_u32_default(dev, "bus-width", -1);
1041         if (val == 8)
1042                 priv->bus_width = 8;
1043         else if (val == 4)
1044                 priv->bus_width = 4;
1045         else
1046                 priv->bus_width = 1;
1047
1048         if (dev_read_bool(dev, "non-removable")) {
1049                 priv->non_removable = 1;
1050          } else {
1051                 priv->non_removable = 0;
1052 #ifdef CONFIG_DM_GPIO
1053                 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1054                                      GPIOD_IS_IN);
1055 #endif
1056         }
1057
1058         priv->wp_enable = 1;
1059
1060 #ifdef CONFIG_DM_GPIO
1061         ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1062                                    GPIOD_IS_IN);
1063         if (ret)
1064                 priv->wp_enable = 0;
1065 #endif
1066
1067         priv->vs18_enable = 0;
1068
1069 #ifdef CONFIG_DM_REGULATOR
1070         /*
1071          * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1072          * otherwise, emmc will work abnormally.
1073          */
1074         ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1075         if (ret) {
1076                 dev_dbg(dev, "no vqmmc-supply\n");
1077         } else {
1078                 ret = regulator_set_enable(vqmmc_dev, true);
1079                 if (ret) {
1080                         dev_err(dev, "fail to enable vqmmc-supply\n");
1081                         return ret;
1082                 }
1083
1084                 if (regulator_get_value(vqmmc_dev) == 1800000)
1085                         priv->vs18_enable = 1;
1086         }
1087 #endif
1088
1089         /*
1090          * TODO:
1091          * Because lack of clk driver, if SDHC clk is not enabled,
1092          * need to enable it first before this driver is invoked.
1093          *
1094          * we use MXC_ESDHC_CLK to get clk freq.
1095          * If one would like to make this function work,
1096          * the aliases should be provided in dts as this:
1097          *
1098          *  aliases {
1099          *      mmc0 = &usdhc1;
1100          *      mmc1 = &usdhc2;
1101          *      mmc2 = &usdhc3;
1102          *      mmc3 = &usdhc4;
1103          *      };
1104          * Then if your board only supports mmc2 and mmc3, but we can
1105          * correctly get the seq as 2 and 3, then let mxc_get_clock
1106          * work as expected.
1107          */
1108
1109         init_clk_usdhc(dev->seq);
1110
1111         priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1112         if (priv->sdhc_clk <= 0) {
1113                 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1114                 return -EINVAL;
1115         }
1116
1117         ret = fsl_esdhc_init(priv, plat);
1118         if (ret) {
1119                 dev_err(dev, "fsl_esdhc_init failure\n");
1120                 return ret;
1121         }
1122
1123         mmc = &plat->mmc;
1124         mmc->cfg = &plat->cfg;
1125         mmc->dev = dev;
1126         upriv->mmc = mmc;
1127
1128         return esdhc_init_common(priv, mmc);
1129 }
1130
1131 #if CONFIG_IS_ENABLED(DM_MMC)
1132 static int fsl_esdhc_get_cd(struct udevice *dev)
1133 {
1134         struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1135
1136         return true;
1137         return esdhc_getcd_common(priv);
1138 }
1139
1140 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1141                               struct mmc_data *data)
1142 {
1143         struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1144         struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1145
1146         return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1147 }
1148
1149 static int fsl_esdhc_set_ios(struct udevice *dev)
1150 {
1151         struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1152         struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1153
1154         return esdhc_set_ios_common(priv, &plat->mmc);
1155 }
1156
1157 static const struct dm_mmc_ops fsl_esdhc_ops = {
1158         .get_cd         = fsl_esdhc_get_cd,
1159         .send_cmd       = fsl_esdhc_send_cmd,
1160         .set_ios        = fsl_esdhc_set_ios,
1161 };
1162 #endif
1163
1164 static const struct udevice_id fsl_esdhc_ids[] = {
1165         { .compatible = "fsl,imx6ul-usdhc", },
1166         { .compatible = "fsl,imx6sx-usdhc", },
1167         { .compatible = "fsl,imx6sl-usdhc", },
1168         { .compatible = "fsl,imx6q-usdhc", },
1169         { .compatible = "fsl,imx7d-usdhc", },
1170         { .compatible = "fsl,imx7ulp-usdhc", },
1171         { .compatible = "fsl,esdhc", },
1172         { /* sentinel */ }
1173 };
1174
1175 #if CONFIG_IS_ENABLED(BLK)
1176 static int fsl_esdhc_bind(struct udevice *dev)
1177 {
1178         struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1179
1180         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1181 }
1182 #endif
1183
1184 U_BOOT_DRIVER(fsl_esdhc) = {
1185         .name   = "fsl-esdhc-mmc",
1186         .id     = UCLASS_MMC,
1187         .of_match = fsl_esdhc_ids,
1188         .ops    = &fsl_esdhc_ops,
1189 #if CONFIG_IS_ENABLED(BLK)
1190         .bind   = fsl_esdhc_bind,
1191 #endif
1192         .probe  = fsl_esdhc_probe,
1193         .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1194         .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
1195 };
1196 #endif