2 * Faraday MMC/SD Host Controller
4 * (C) Copyright 2010 Faraday Technology
5 * Dante Su <dantesu@faraday-tech.com>
7 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/errno.h>
17 #include <asm/byteorder.h>
18 #include <faraday/ftsdc010.h>
20 #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
21 #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
23 struct ftsdc010_chip
{
25 uint32_t wprot
; /* write protected (locked) */
26 uint32_t rate
; /* actual SD clock in Hz */
27 uint32_t sclk
; /* FTSDC010 source clock in Hz */
28 uint32_t fifo
; /* fifo depth in bytes */
30 struct mmc_config cfg
; /* mmc configuration */
33 static inline int ftsdc010_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*mmc_cmd
)
35 struct ftsdc010_chip
*chip
= mmc
->priv
;
36 struct ftsdc010_mmc __iomem
*regs
= chip
->regs
;
39 uint32_t cmd
= FTSDC010_CMD_IDX(mmc_cmd
->cmdidx
);
40 uint32_t arg
= mmc_cmd
->cmdarg
;
41 uint32_t flags
= mmc_cmd
->resp_type
;
43 cmd
|= FTSDC010_CMD_CMD_EN
;
46 cmd
|= FTSDC010_CMD_APP_CMD
;
50 if (flags
& MMC_RSP_PRESENT
)
51 cmd
|= FTSDC010_CMD_NEED_RSP
;
53 if (flags
& MMC_RSP_136
)
54 cmd
|= FTSDC010_CMD_LONG_RSP
;
56 writel(FTSDC010_STATUS_RSP_MASK
| FTSDC010_STATUS_CMD_SEND
,
58 writel(arg
, ®s
->argu
);
59 writel(cmd
, ®s
->cmd
);
61 if (!(flags
& (MMC_RSP_PRESENT
| MMC_RSP_136
))) {
62 for (ts
= get_timer(0); get_timer(ts
) < CFG_CMD_TIMEOUT
; ) {
63 if (readl(®s
->status
) & FTSDC010_STATUS_CMD_SEND
) {
64 writel(FTSDC010_STATUS_CMD_SEND
, ®s
->clr
);
71 for (ts
= get_timer(0); get_timer(ts
) < CFG_CMD_TIMEOUT
; ) {
72 st
= readl(®s
->status
);
73 writel(st
& FTSDC010_STATUS_RSP_MASK
, ®s
->clr
);
74 if (st
& FTSDC010_STATUS_RSP_MASK
)
77 if (st
& FTSDC010_STATUS_RSP_CRC_OK
) {
78 if (flags
& MMC_RSP_136
) {
79 mmc_cmd
->response
[0] = readl(®s
->rsp3
);
80 mmc_cmd
->response
[1] = readl(®s
->rsp2
);
81 mmc_cmd
->response
[2] = readl(®s
->rsp1
);
82 mmc_cmd
->response
[3] = readl(®s
->rsp0
);
84 mmc_cmd
->response
[0] = readl(®s
->rsp0
);
88 debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
94 debug("ftsdc010: cmd timeout (op code=%d)\n",
96 } else if (mmc_cmd
->cmdidx
== MMC_CMD_APP_CMD
) {
103 static void ftsdc010_clkset(struct mmc
*mmc
, uint32_t rate
)
105 struct ftsdc010_chip
*chip
= mmc
->priv
;
106 struct ftsdc010_mmc __iomem
*regs
= chip
->regs
;
109 for (div
= 0; div
< 0x7f; ++div
) {
110 if (rate
>= chip
->sclk
/ (2 * (div
+ 1)))
113 chip
->rate
= chip
->sclk
/ (2 * (div
+ 1));
115 writel(FTSDC010_CCR_CLK_DIV(div
), ®s
->ccr
);
118 setbits_le32(®s
->ccr
, FTSDC010_CCR_CLK_SD
);
120 if (chip
->rate
> 25000000)
121 setbits_le32(®s
->ccr
, FTSDC010_CCR_CLK_HISPD
);
123 clrbits_le32(®s
->ccr
, FTSDC010_CCR_CLK_HISPD
);
127 static int ftsdc010_wait(struct ftsdc010_mmc __iomem
*regs
, uint32_t mask
)
129 int ret
= -ETIMEDOUT
;
132 for (ts
= get_timer(0); get_timer(ts
) < CFG_CMD_TIMEOUT
; ) {
133 st
= readl(®s
->status
);
136 writel(st
& mask
, ®s
->clr
);
142 debug("ftsdc010: wait st(0x%x) timeout\n", mask
);
151 static int ftsdc010_request(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
152 struct mmc_data
*data
)
154 int ret
= -EOPNOTSUPP
;
156 struct ftsdc010_chip
*chip
= mmc
->priv
;
157 struct ftsdc010_mmc __iomem
*regs
= chip
->regs
;
159 if (data
&& (data
->flags
& MMC_DATA_WRITE
) && chip
->wprot
) {
160 printf("ftsdc010: the card is write protected!\n");
167 len
= data
->blocksize
* data
->blocks
;
169 /* 1. data disable + fifo reset */
171 #ifdef CONFIG_FTSDC010_SDIO
172 dcr
|= FTSDC010_DCR_FIFO_RST
;
174 writel(dcr
, ®s
->dcr
);
176 /* 2. clear status register */
177 writel(FTSDC010_STATUS_DATA_MASK
| FTSDC010_STATUS_FIFO_URUN
178 | FTSDC010_STATUS_FIFO_ORUN
, ®s
->clr
);
180 /* 3. data timeout (1 sec) */
181 writel(chip
->rate
, ®s
->dtr
);
183 /* 4. data length (bytes) */
184 writel(len
, ®s
->dlr
);
187 dcr
= (ffs(data
->blocksize
) - 1) | FTSDC010_DCR_DATA_EN
;
188 if (data
->flags
& MMC_DATA_WRITE
)
189 dcr
|= FTSDC010_DCR_DATA_WRITE
;
190 writel(dcr
, ®s
->dcr
);
193 ret
= ftsdc010_send_cmd(mmc
, cmd
);
195 printf("ftsdc010: CMD%d failed\n", cmd
->cmdidx
);
202 if (data
->flags
& MMC_DATA_WRITE
) {
203 const uint8_t *buf
= (const uint8_t *)data
->src
;
208 /* wait for tx ready */
209 ret
= ftsdc010_wait(regs
, FTSDC010_STATUS_FIFO_URUN
);
213 /* write bytes to ftsdc010 */
214 for (wlen
= 0; wlen
< len
&& wlen
< chip
->fifo
; ) {
215 writel(*(uint32_t *)buf
, ®s
->dwr
);
224 uint8_t *buf
= (uint8_t *)data
->dest
;
229 /* wait for rx ready */
230 ret
= ftsdc010_wait(regs
, FTSDC010_STATUS_FIFO_ORUN
);
234 /* fetch bytes from ftsdc010 */
235 for (rlen
= 0; rlen
< len
&& rlen
< chip
->fifo
; ) {
236 *(uint32_t *)buf
= readl(®s
->dwr
);
247 ret
= ftsdc010_wait(regs
,
248 FTSDC010_STATUS_DATA_END
| FTSDC010_STATUS_DATA_ERROR
);
254 static int ftsdc010_set_ios(struct mmc
*mmc
)
256 struct ftsdc010_chip
*chip
= mmc
->priv
;
257 struct ftsdc010_mmc __iomem
*regs
= chip
->regs
;
259 ftsdc010_clkset(mmc
, mmc
->clock
);
261 clrbits_le32(®s
->bwr
, FTSDC010_BWR_MODE_MASK
);
262 switch (mmc
->bus_width
) {
264 setbits_le32(®s
->bwr
, FTSDC010_BWR_MODE_4BIT
);
267 setbits_le32(®s
->bwr
, FTSDC010_BWR_MODE_8BIT
);
270 setbits_le32(®s
->bwr
, FTSDC010_BWR_MODE_1BIT
);
277 static int ftsdc010_init(struct mmc
*mmc
)
279 struct ftsdc010_chip
*chip
= mmc
->priv
;
280 struct ftsdc010_mmc __iomem
*regs
= chip
->regs
;
283 if (readl(®s
->status
) & FTSDC010_STATUS_CARD_DETECT
)
286 if (readl(®s
->status
) & FTSDC010_STATUS_WRITE_PROT
) {
287 printf("ftsdc010: write protected\n");
291 chip
->fifo
= (readl(®s
->feature
) & 0xff) << 2;
294 writel(FTSDC010_CMD_SDC_RST
, ®s
->cmd
);
295 for (ts
= get_timer(0); get_timer(ts
) < CFG_RST_TIMEOUT
; ) {
296 if (readl(®s
->cmd
) & FTSDC010_CMD_SDC_RST
)
300 if (readl(®s
->cmd
) & FTSDC010_CMD_SDC_RST
) {
301 printf("ftsdc010: reset failed\n");
305 /* 2. enter low speed mode (400k card detection) */
306 ftsdc010_clkset(mmc
, 400000);
308 /* 3. interrupt disabled */
309 writel(0, ®s
->int_mask
);
314 static const struct mmc_ops ftsdc010_ops
= {
315 .send_cmd
= ftsdc010_request
,
316 .set_ios
= ftsdc010_set_ios
,
317 .init
= ftsdc010_init
,
320 int ftsdc010_mmc_init(int devid
)
323 struct ftsdc010_chip
*chip
;
324 struct ftsdc010_mmc __iomem
*regs
;
325 #ifdef CONFIG_FTSDC010_BASE_LIST
326 uint32_t base_list
[] = CONFIG_FTSDC010_BASE_LIST
;
328 if (devid
< 0 || devid
>= ARRAY_SIZE(base_list
))
330 regs
= (void __iomem
*)base_list
[devid
];
332 regs
= (void __iomem
*)(CONFIG_FTSDC010_BASE
+ (devid
<< 20));
335 chip
= malloc(sizeof(struct ftsdc010_chip
));
338 memset(chip
, 0, sizeof(struct ftsdc010_chip
));
341 #ifdef CONFIG_SYS_CLK_FREQ
342 chip
->sclk
= CONFIG_SYS_CLK_FREQ
;
344 chip
->sclk
= clk_get_rate("SDC");
347 chip
->cfg
.name
= "ftsdc010";
348 chip
->cfg
.ops
= &ftsdc010_ops
;
349 chip
->cfg
.host_caps
= MMC_MODE_HS
| MMC_MODE_HS_52MHz
;
350 switch (readl(®s
->bwr
) & FTSDC010_BWR_CAPS_MASK
) {
351 case FTSDC010_BWR_CAPS_4BIT
:
352 chip
->cfg
.host_caps
|= MMC_MODE_4BIT
;
354 case FTSDC010_BWR_CAPS_8BIT
:
355 chip
->cfg
.host_caps
|= MMC_MODE_4BIT
| MMC_MODE_8BIT
;
361 chip
->cfg
.voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
362 chip
->cfg
.f_max
= chip
->sclk
/ 2;
363 chip
->cfg
.f_min
= chip
->sclk
/ 0x100;
365 chip
->cfg
.part_type
= PART_TYPE_DOS
;
366 chip
->cfg
.b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
368 mmc
= mmc_create(&chip
->cfg
, chip
);