3 * Rob Emanuele <rob@emanuele.us>
4 * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
7 * Copyright (C) 2004-2006 Atmel Corporation
9 * SPDX-License-Identifier: GPL-2.0+
19 #include <linux/errno.h>
20 #include <asm/byteorder.h>
21 #include <asm/arch/clk.h>
22 #include <asm/arch/hardware.h>
23 #include "atmel_mci.h"
25 DECLARE_GLOBAL_DATA_PTR
;
27 #ifndef CONFIG_SYS_MMC_CLK_OD
28 # define CONFIG_SYS_MMC_CLK_OD 150000
31 #define MMC_DEFAULT_BLKLEN 512
33 #if defined(CONFIG_ATMEL_MCI_PORTB)
40 struct atmel_mci_plat
{
42 struct mmc_config cfg
;
43 struct atmel_mci
*mci
;
47 struct atmel_mci_priv
{
49 struct mmc_config cfg
;
50 struct atmel_mci
*mci
;
52 unsigned int initialized
:1;
53 unsigned int curr_clk
;
59 /* Read Atmel MCI IP version */
60 static unsigned int atmel_mci_get_version(struct atmel_mci
*mci
)
62 return readl(&mci
->version
) & 0x00000fff;
66 * Print command and status:
68 * - always when DEBUG is defined
71 static void dump_cmd(u32 cmdr
, u32 arg
, u32 status
, const char* msg
)
73 debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
74 cmdr
, cmdr
& 0x3F, arg
, status
, msg
);
77 static inline void mci_set_blklen(atmel_mci_t
*mci
, int blklen
)
79 unsigned int version
= atmel_mci_get_version(mci
);
83 /* MCI IP version >= 0x200 has blkr */
85 writel(MMCI_BFINS(BLKLEN
, blklen
, readl(&mci
->blkr
)),
88 writel(MMCI_BFINS(BLKLEN
, blklen
, readl(&mci
->mr
)), &mci
->mr
);
91 /* Setup for MCI Clock and Block Size */
93 static void mci_set_mode(struct udevice
*dev
, u32 hz
, u32 blklen
)
95 struct atmel_mci_plat
*plat
= dev_get_platdata(dev
);
96 struct atmel_mci_priv
*priv
= dev_get_priv(dev
);
97 struct mmc
*mmc
= &plat
->mmc
;
98 u32 bus_hz
= priv
->bus_clk_rate
;
99 atmel_mci_t
*mci
= plat
->mci
;
101 static void mci_set_mode(struct mmc
*mmc
, u32 hz
, u32 blklen
)
103 struct atmel_mci_priv
*priv
= mmc
->priv
;
104 u32 bus_hz
= get_mci_clk_rate();
105 atmel_mci_t
*mci
= priv
->mci
;
109 unsigned int version
= atmel_mci_get_version(mci
);
113 debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
116 if (version
>= 0x500) {
117 clkdiv
= DIV_ROUND_UP(bus_hz
, hz
) - 2;
124 debug("mci: setting clock %u Hz, block size %u\n",
125 bus_hz
/ (clkdiv
* 2 + clkodd
+ 2), blklen
);
127 /* find clkdiv yielding a rate <= than requested */
128 for (clkdiv
= 0; clkdiv
< 255; clkdiv
++) {
129 if ((bus_hz
/ (clkdiv
+ 1) / 2) <= hz
)
132 debug("mci: setting clock %u Hz, block size %u\n",
133 (bus_hz
/ (clkdiv
+ 1)) / 2, blklen
);
137 if (version
>= 0x500)
138 priv
->curr_clk
= bus_hz
/ (clkdiv
* 2 + clkodd
+ 2);
140 priv
->curr_clk
= (bus_hz
/ (clkdiv
+ 1)) / 2;
142 mr
= MMCI_BF(CLKDIV
, clkdiv
);
144 /* MCI IP version >= 0x200 has R/WPROOF */
145 if (version
>= 0x200)
146 mr
|= MMCI_BIT(RDPROOF
) | MMCI_BIT(WRPROOF
);
149 * MCI IP version >= 0x500 use bit 16 as clkodd.
150 * MCI IP version < 0x500 use upper 16 bits for blklen.
152 if (version
>= 0x500)
153 mr
|= MMCI_BF(CLKODD
, clkodd
);
155 writel(mr
, &mci
->mr
);
157 mci_set_blklen(mci
, blklen
);
159 if (mmc
->card_caps
& mmc
->cfg
->host_caps
& MMC_MODE_HS
)
160 writel(MMCI_BIT(HSMODE
), &mci
->cfg
);
162 priv
->initialized
= 1;
165 /* Return the CMDR with flags for a given command and data packet */
166 static u32
mci_encode_cmd(
167 struct mmc_cmd
*cmd
, struct mmc_data
*data
, u32
* error_flags
)
171 /* Default Flags for Errors */
172 *error_flags
|= (MMCI_BIT(DTOE
) | MMCI_BIT(RDIRE
) | MMCI_BIT(RENDE
) |
173 MMCI_BIT(RINDE
) | MMCI_BIT(RTOE
));
175 /* Default Flags for the Command */
176 cmdr
|= MMCI_BIT(MAXLAT
);
179 cmdr
|= MMCI_BF(TRCMD
, 1);
180 if (data
->blocks
> 1)
181 cmdr
|= MMCI_BF(TRTYP
, 1);
182 if (data
->flags
& MMC_DATA_READ
)
183 cmdr
|= MMCI_BIT(TRDIR
);
186 if (cmd
->resp_type
& MMC_RSP_CRC
)
187 *error_flags
|= MMCI_BIT(RCRCE
);
188 if (cmd
->resp_type
& MMC_RSP_136
)
189 cmdr
|= MMCI_BF(RSPTYP
, 2);
190 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
191 cmdr
|= MMCI_BF(RSPTYP
, 3);
192 else if (cmd
->resp_type
& MMC_RSP_PRESENT
)
193 cmdr
|= MMCI_BF(RSPTYP
, 1);
195 return cmdr
| MMCI_BF(CMDNB
, cmd
->cmdidx
);
198 /* Entered into function pointer in mci_send_cmd */
199 static u32
mci_data_read(atmel_mci_t
*mci
, u32
* data
, u32 error_flags
)
204 status
= readl(&mci
->sr
);
205 if (status
& (error_flags
| MMCI_BIT(OVRE
)))
207 } while (!(status
& MMCI_BIT(RXRDY
)));
209 if (status
& MMCI_BIT(RXRDY
)) {
210 *data
= readl(&mci
->rdr
);
217 /* Entered into function pointer in mci_send_cmd */
218 static u32
mci_data_write(atmel_mci_t
*mci
, u32
* data
, u32 error_flags
)
223 status
= readl(&mci
->sr
);
224 if (status
& (error_flags
| MMCI_BIT(UNRE
)))
226 } while (!(status
& MMCI_BIT(TXRDY
)));
228 if (status
& MMCI_BIT(TXRDY
)) {
229 writel(*data
, &mci
->tdr
);
237 * Entered into mmc structure during driver init
239 * Sends a command out on the bus and deals with the block data.
240 * Takes the mmc pointer, a command pointer, and an optional data pointer.
243 static int atmel_mci_send_cmd(struct udevice
*dev
, struct mmc_cmd
*cmd
,
244 struct mmc_data
*data
)
246 struct atmel_mci_plat
*plat
= dev_get_platdata(dev
);
247 struct atmel_mci_priv
*priv
= dev_get_priv(dev
);
248 atmel_mci_t
*mci
= plat
->mci
;
251 mci_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
, struct mmc_data
*data
)
253 struct atmel_mci_priv
*priv
= mmc
->priv
;
254 atmel_mci_t
*mci
= priv
->mci
;
260 if (!priv
->initialized
) {
261 puts ("MCI not initialized!\n");
265 /* Figure out the transfer arguments */
266 cmdr
= mci_encode_cmd(cmd
, data
, &error_flags
);
268 mci_set_blklen(mci
, data
->blocksize
);
270 /* For multi blocks read/write, set the block register */
271 if ((cmd
->cmdidx
== MMC_CMD_READ_MULTIPLE_BLOCK
)
272 || (cmd
->cmdidx
== MMC_CMD_WRITE_MULTIPLE_BLOCK
))
273 writel(data
->blocks
| MMCI_BF(BLKLEN
, data
->blocksize
),
276 /* Send the command */
277 writel(cmd
->cmdarg
, &mci
->argr
);
278 writel(cmdr
, &mci
->cmdr
);
281 dump_cmd(cmdr
, cmd
->cmdarg
, 0, "DEBUG");
284 /* Wait for the command to complete */
285 while (!((status
= readl(&mci
->sr
)) & MMCI_BIT(CMDRDY
)));
287 if ((status
& error_flags
) & MMCI_BIT(RTOE
)) {
288 dump_cmd(cmdr
, cmd
->cmdarg
, status
, "Command Time Out");
290 } else if (status
& error_flags
) {
291 dump_cmd(cmdr
, cmd
->cmdarg
, status
, "Command Failed");
295 /* Copy the response to the response buffer */
296 if (cmd
->resp_type
& MMC_RSP_136
) {
297 cmd
->response
[0] = readl(&mci
->rspr
);
298 cmd
->response
[1] = readl(&mci
->rspr1
);
299 cmd
->response
[2] = readl(&mci
->rspr2
);
300 cmd
->response
[3] = readl(&mci
->rspr3
);
302 cmd
->response
[0] = readl(&mci
->rspr
);
304 /* transfer all of the blocks */
306 u32 word_count
, block_count
;
310 (atmel_mci_t
*mci
, u32
* data
, u32 error_flags
);
312 if (data
->flags
& MMC_DATA_READ
) {
313 mci_data_op
= mci_data_read
;
314 ioptr
= (u32
*)data
->dest
;
316 mci_data_op
= mci_data_write
;
317 ioptr
= (u32
*)data
->src
;
321 for (block_count
= 0;
322 block_count
< data
->blocks
&& !status
;
326 status
= mci_data_op(mci
, ioptr
, error_flags
);
329 } while (!status
&& word_count
< (data
->blocksize
/4));
331 if (data
->flags
& MMC_DATA_READ
)
333 u32 cnt
= word_count
* 4;
334 printf("Read Data:\n");
335 print_buffer(0, data
->dest
+ cnt
* block_count
,
340 dump_cmd(cmdr
, cmd
->cmdarg
, status
,
341 "Data Transfer Failed");
346 /* Wait for Transfer End */
349 status
= readl(&mci
->sr
);
351 if (status
& error_flags
) {
352 dump_cmd(cmdr
, cmd
->cmdarg
, status
,
357 } while ((status
& MMCI_BIT(DTIP
)) && i
< 10000);
358 if (status
& MMCI_BIT(DTIP
)) {
359 dump_cmd(cmdr
, cmd
->cmdarg
, status
,
360 "XFER DTIP never unset, ignoring");
365 * After the switch command, wait for 8 clocks before the next
368 if (cmd
->cmdidx
== MMC_CMD_SWITCH
)
369 udelay(8*1000000 / priv
->curr_clk
); /* 8 clk in us */
375 static int atmel_mci_set_ios(struct udevice
*dev
)
377 struct atmel_mci_plat
*plat
= dev_get_platdata(dev
);
378 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
379 atmel_mci_t
*mci
= plat
->mci
;
381 /* Entered into mmc structure during driver init */
382 static int mci_set_ios(struct mmc
*mmc
)
384 struct atmel_mci_priv
*priv
= mmc
->priv
;
385 atmel_mci_t
*mci
= priv
->mci
;
387 int bus_width
= mmc
->bus_width
;
388 unsigned int version
= atmel_mci_get_version(mci
);
391 /* Set the clock speed */
393 mci_set_mode(dev
, mmc
->clock
, MMC_DEFAULT_BLKLEN
);
395 mci_set_mode(mmc
, mmc
->clock
, MMC_DEFAULT_BLKLEN
);
399 * set the bus width and select slot for this interface
400 * there is no capability for multiple slots on the same interface yet
402 if ((version
& 0xf00) >= 0x300) {
415 writel(busw
<< 6 | MMCI_BF(SCDSEL
, MCI_BUS
), &mci
->sdcr
);
417 busw
= (bus_width
== 4) ? 1 : 0;
419 writel(busw
<< 7 | MMCI_BF(SCDSEL
, MCI_BUS
), &mci
->sdcr
);
426 static int atmel_mci_hw_init(struct udevice
*dev
)
428 struct atmel_mci_plat
*plat
= dev_get_platdata(dev
);
429 atmel_mci_t
*mci
= plat
->mci
;
431 /* Entered into mmc structure during driver init */
432 static int mci_init(struct mmc
*mmc
)
434 struct atmel_mci_priv
*priv
= mmc
->priv
;
435 atmel_mci_t
*mci
= priv
->mci
;
438 /* Initialize controller */
439 writel(MMCI_BIT(SWRST
), &mci
->cr
); /* soft reset */
440 writel(MMCI_BIT(PWSDIS
), &mci
->cr
); /* disable power save */
441 writel(MMCI_BIT(MCIEN
), &mci
->cr
); /* enable mci */
442 writel(MMCI_BF(SCDSEL
, MCI_BUS
), &mci
->sdcr
); /* select port */
444 /* This delay can be optimized, but stick with max value */
445 writel(0x7f, &mci
->dtor
);
446 /* Disable Interrupts */
447 writel(~0UL, &mci
->idr
);
449 /* Set default clocks and blocklen */
451 mci_set_mode(dev
, CONFIG_SYS_MMC_CLK_OD
, MMC_DEFAULT_BLKLEN
);
453 mci_set_mode(mmc
, CONFIG_SYS_MMC_CLK_OD
, MMC_DEFAULT_BLKLEN
);
459 #ifndef CONFIG_DM_MMC
460 static const struct mmc_ops atmel_mci_ops
= {
461 .send_cmd
= mci_send_cmd
,
462 .set_ios
= mci_set_ios
,
467 * This is the only exported function
469 * Call it with the MCI register base address
471 int atmel_mci_init(void *regs
)
474 struct mmc_config
*cfg
;
475 struct atmel_mci_priv
*priv
;
476 unsigned int version
;
478 priv
= calloc(1, sizeof(*priv
));
485 cfg
->ops
= &atmel_mci_ops
;
487 priv
->mci
= (struct atmel_mci
*)regs
;
488 priv
->initialized
= 0;
490 /* need to be able to pass these in on a board by board basis */
491 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
492 version
= atmel_mci_get_version(priv
->mci
);
493 if ((version
& 0xf00) >= 0x300) {
494 cfg
->host_caps
= MMC_MODE_8BIT
;
495 cfg
->host_caps
|= MMC_MODE_HS
| MMC_MODE_HS_52MHz
;
498 cfg
->host_caps
|= MMC_MODE_4BIT
;
501 * min and max frequencies determined by
502 * max and min of clock divider
504 cfg
->f_min
= get_mci_clk_rate() / (2*256);
505 cfg
->f_max
= get_mci_clk_rate() / (2*1);
507 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
509 mmc
= mmc_create(cfg
, priv
);
515 /* NOTE: possibly leaking the priv structure */
522 static const struct dm_mmc_ops atmel_mci_mmc_ops
= {
523 .send_cmd
= atmel_mci_send_cmd
,
524 .set_ios
= atmel_mci_set_ios
,
527 static void atmel_mci_setup_cfg(struct udevice
*dev
)
529 struct atmel_mci_plat
*plat
= dev_get_platdata(dev
);
530 struct atmel_mci_priv
*priv
= dev_get_priv(dev
);
531 struct mmc_config
*cfg
;
535 cfg
->name
= "Atmel mci";
536 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
539 * If the version is above 3.0, the capabilities of the 8-bit
540 * bus width and high speed are supported.
542 version
= atmel_mci_get_version(plat
->mci
);
543 if ((version
& 0xf00) >= 0x300) {
544 cfg
->host_caps
= MMC_MODE_8BIT
|
545 MMC_MODE_HS
| MMC_MODE_HS_52MHz
;
548 cfg
->host_caps
|= MMC_MODE_4BIT
;
549 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
550 cfg
->f_min
= priv
->bus_clk_rate
/ (2 * 256);
551 cfg
->f_max
= priv
->bus_clk_rate
/ 2;
554 static int atmel_mci_enable_clk(struct udevice
*dev
)
556 struct atmel_mci_priv
*priv
= dev_get_priv(dev
);
561 ret
= clk_get_by_index(dev
, 0, &clk
);
567 ret
= clk_enable(&clk
);
571 clk_rate
= clk_get_rate(&clk
);
577 priv
->bus_clk_rate
= clk_rate
;
585 static int atmel_mci_probe(struct udevice
*dev
)
587 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
588 struct atmel_mci_plat
*plat
= dev_get_platdata(dev
);
592 ret
= atmel_mci_enable_clk(dev
);
596 plat
->mci
= (struct atmel_mci
*)devfdt_get_addr_ptr(dev
);
598 atmel_mci_setup_cfg(dev
);
601 mmc
->cfg
= &plat
->cfg
;
605 atmel_mci_hw_init(dev
);
610 static int atmel_mci_bind(struct udevice
*dev
)
612 struct atmel_mci_plat
*plat
= dev_get_platdata(dev
);
614 return mmc_bind(dev
, &plat
->mmc
, &plat
->cfg
);
617 static const struct udevice_id atmel_mci_ids
[] = {
618 { .compatible
= "atmel,hsmci" },
622 U_BOOT_DRIVER(atmel_mci
) = {
625 .of_match
= atmel_mci_ids
,
626 .bind
= atmel_mci_bind
,
627 .probe
= atmel_mci_probe
,
628 .platdata_auto_alloc_size
= sizeof(struct atmel_mci_plat
),
629 .priv_auto_alloc_size
= sizeof(struct atmel_mci_priv
),
630 .ops
= &atmel_mci_mmc_ops
,