1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * meson-mx-sdio.c - Meson6, Meson8 and Meson8b SDIO/MMC Host Controller
5 * Copyright (C) 2015 Endless Mobile, Inc.
6 * Author: Carlo Caione <carlo@endlessm.com>
7 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/platform_device.h>
21 #include <linux/of_platform.h>
22 #include <linux/timer.h>
23 #include <linux/types.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/mmc.h>
27 #include <linux/mmc/sdio.h>
28 #include <linux/mmc/slot-gpio.h>
30 #define MESON_MX_SDIO_ARGU 0x00
32 #define MESON_MX_SDIO_SEND 0x04
33 #define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK GENMASK(7, 0)
34 #define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK GENMASK(15, 8)
35 #define MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7 BIT(16)
36 #define MESON_MX_SDIO_SEND_RESP_HAS_DATA BIT(17)
37 #define MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8 BIT(18)
38 #define MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY BIT(19)
39 #define MESON_MX_SDIO_SEND_DATA BIT(20)
40 #define MESON_MX_SDIO_SEND_USE_INT_WINDOW BIT(21)
41 #define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK GENMASK(31, 24)
43 #define MESON_MX_SDIO_CONF 0x08
44 #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT 0
45 #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH 10
46 #define MESON_MX_SDIO_CONF_CMD_DISABLE_CRC BIT(10)
47 #define MESON_MX_SDIO_CONF_CMD_OUT_AT_POSITIVE_EDGE BIT(11)
48 #define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK GENMASK(17, 12)
49 #define MESON_MX_SDIO_CONF_RESP_LATCH_AT_NEGATIVE_EDGE BIT(18)
50 #define MESON_MX_SDIO_CONF_DATA_LATCH_AT_NEGATIVE_EDGE BIT(19)
51 #define MESON_MX_SDIO_CONF_BUS_WIDTH BIT(20)
52 #define MESON_MX_SDIO_CONF_M_ENDIAN_MASK GENMASK(22, 21)
53 #define MESON_MX_SDIO_CONF_WRITE_NWR_MASK GENMASK(28, 23)
54 #define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK GENMASK(31, 29)
56 #define MESON_MX_SDIO_IRQS 0x0c
57 #define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK GENMASK(3, 0)
58 #define MESON_MX_SDIO_IRQS_CMD_BUSY BIT(4)
59 #define MESON_MX_SDIO_IRQS_RESP_CRC7_OK BIT(5)
60 #define MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK BIT(6)
61 #define MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK BIT(7)
62 #define MESON_MX_SDIO_IRQS_IF_INT BIT(8)
63 #define MESON_MX_SDIO_IRQS_CMD_INT BIT(9)
64 #define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK GENMASK(15, 12)
65 #define MESON_MX_SDIO_IRQS_TIMING_OUT_INT BIT(16)
66 #define MESON_MX_SDIO_IRQS_AMRISC_TIMING_OUT_INT_EN BIT(17)
67 #define MESON_MX_SDIO_IRQS_ARC_TIMING_OUT_INT_EN BIT(18)
68 #define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK GENMASK(31, 19)
70 #define MESON_MX_SDIO_IRQC 0x10
71 #define MESON_MX_SDIO_IRQC_ARC_IF_INT_EN BIT(3)
72 #define MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN BIT(4)
73 #define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK GENMASK(7, 6)
74 #define MESON_MX_SDIO_IRQC_FORCE_DATA_CLK BIT(8)
75 #define MESON_MX_SDIO_IRQC_FORCE_DATA_CMD BIT(9)
76 #define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK GENMASK(13, 10)
77 #define MESON_MX_SDIO_IRQC_SOFT_RESET BIT(15)
78 #define MESON_MX_SDIO_IRQC_FORCE_HALT BIT(30)
79 #define MESON_MX_SDIO_IRQC_HALT_HOLE BIT(31)
81 #define MESON_MX_SDIO_MULT 0x14
82 #define MESON_MX_SDIO_MULT_PORT_SEL_MASK GENMASK(1, 0)
83 #define MESON_MX_SDIO_MULT_MEMORY_STICK_ENABLE BIT(2)
84 #define MESON_MX_SDIO_MULT_MEMORY_STICK_SCLK_ALWAYS BIT(3)
85 #define MESON_MX_SDIO_MULT_STREAM_ENABLE BIT(4)
86 #define MESON_MX_SDIO_MULT_STREAM_8BITS_MODE BIT(5)
87 #define MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX BIT(8)
88 #define MESON_MX_SDIO_MULT_DAT0_DAT1_SWAPPED BIT(10)
89 #define MESON_MX_SDIO_MULT_DAT1_DAT0_SWAPPED BIT(11)
90 #define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK GENMASK(15, 12)
92 #define MESON_MX_SDIO_ADDR 0x18
94 #define MESON_MX_SDIO_EXT 0x1c
95 #define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK GENMASK(29, 16)
97 #define MESON_MX_SDIO_BOUNCE_REQ_SIZE (128 * 1024)
98 #define MESON_MX_SDIO_RESPONSE_CRC16_BITS (16 - 1)
99 #define MESON_MX_SDIO_MAX_SLOTS 3
101 struct meson_mx_mmc_host
{
102 struct device
*controller_dev
;
104 struct clk
*parent_clk
;
105 struct clk
*core_clk
;
106 struct clk_divider cfg_div
;
107 struct clk
*cfg_div_clk
;
108 struct clk_fixed_factor fixed_factor
;
109 struct clk
*fixed_factor_clk
;
115 struct timer_list cmd_timeout
;
117 unsigned int slot_id
;
118 struct mmc_host
*mmc
;
120 struct mmc_request
*mrq
;
121 struct mmc_command
*cmd
;
125 static void meson_mx_mmc_mask_bits(struct mmc_host
*mmc
, char reg
, u32 mask
,
128 struct meson_mx_mmc_host
*host
= mmc_priv(mmc
);
131 regval
= readl(host
->base
+ reg
);
133 regval
|= (val
& mask
);
135 writel(regval
, host
->base
+ reg
);
138 static void meson_mx_mmc_soft_reset(struct meson_mx_mmc_host
*host
)
140 writel(MESON_MX_SDIO_IRQC_SOFT_RESET
, host
->base
+ MESON_MX_SDIO_IRQC
);
144 static struct mmc_command
*meson_mx_mmc_get_next_cmd(struct mmc_command
*cmd
)
146 if (cmd
->opcode
== MMC_SET_BLOCK_COUNT
&& !cmd
->error
)
147 return cmd
->mrq
->cmd
;
148 else if (mmc_op_multi(cmd
->opcode
) &&
149 (!cmd
->mrq
->sbc
|| cmd
->error
|| cmd
->data
->error
))
150 return cmd
->mrq
->stop
;
155 static void meson_mx_mmc_start_cmd(struct mmc_host
*mmc
,
156 struct mmc_command
*cmd
)
158 struct meson_mx_mmc_host
*host
= mmc_priv(mmc
);
159 unsigned int pack_size
;
160 unsigned long irqflags
, timeout
;
161 u32 mult
, send
= 0, ext
= 0;
165 if (cmd
->busy_timeout
)
166 timeout
= msecs_to_jiffies(cmd
->busy_timeout
);
168 timeout
= msecs_to_jiffies(1000);
170 switch (mmc_resp_type(cmd
)) {
174 /* 7 (CMD) + 32 (response) + 7 (CRC) -1 */
175 send
|= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK
, 45);
178 /* 7 (CMD) + 120 (response) + 7 (CRC) -1 */
179 send
|= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK
, 133);
180 send
|= MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8
;
186 if (!(cmd
->flags
& MMC_RSP_CRC
))
187 send
|= MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7
;
189 if (cmd
->flags
& MMC_RSP_BUSY
)
190 send
|= MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY
;
193 send
|= FIELD_PREP(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK
,
194 (cmd
->data
->blocks
- 1));
196 pack_size
= cmd
->data
->blksz
* BITS_PER_BYTE
;
197 if (mmc
->ios
.bus_width
== MMC_BUS_WIDTH_4
)
198 pack_size
+= MESON_MX_SDIO_RESPONSE_CRC16_BITS
* 4;
200 pack_size
+= MESON_MX_SDIO_RESPONSE_CRC16_BITS
* 1;
202 ext
|= FIELD_PREP(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK
,
205 if (cmd
->data
->flags
& MMC_DATA_WRITE
)
206 send
|= MESON_MX_SDIO_SEND_DATA
;
208 send
|= MESON_MX_SDIO_SEND_RESP_HAS_DATA
;
210 cmd
->data
->bytes_xfered
= 0;
213 send
|= FIELD_PREP(MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK
,
214 (0x40 | cmd
->opcode
));
216 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
218 mult
= readl(host
->base
+ MESON_MX_SDIO_MULT
);
219 mult
&= ~MESON_MX_SDIO_MULT_PORT_SEL_MASK
;
220 mult
|= FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK
, host
->slot_id
);
222 writel(mult
, host
->base
+ MESON_MX_SDIO_MULT
);
224 /* enable the CMD done interrupt */
225 meson_mx_mmc_mask_bits(mmc
, MESON_MX_SDIO_IRQC
,
226 MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN
,
227 MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN
);
229 /* clear pending interrupts */
230 meson_mx_mmc_mask_bits(mmc
, MESON_MX_SDIO_IRQS
,
231 MESON_MX_SDIO_IRQS_CMD_INT
,
232 MESON_MX_SDIO_IRQS_CMD_INT
);
234 writel(cmd
->arg
, host
->base
+ MESON_MX_SDIO_ARGU
);
235 writel(ext
, host
->base
+ MESON_MX_SDIO_EXT
);
236 writel(send
, host
->base
+ MESON_MX_SDIO_SEND
);
238 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
240 mod_timer(&host
->cmd_timeout
, jiffies
+ timeout
);
243 static void meson_mx_mmc_request_done(struct meson_mx_mmc_host
*host
)
245 struct mmc_request
*mrq
;
252 mmc_request_done(host
->mmc
, mrq
);
255 static void meson_mx_mmc_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
257 struct meson_mx_mmc_host
*host
= mmc_priv(mmc
);
258 unsigned short vdd
= ios
->vdd
;
259 unsigned long clk_rate
= ios
->clock
;
261 switch (ios
->bus_width
) {
262 case MMC_BUS_WIDTH_1
:
263 meson_mx_mmc_mask_bits(mmc
, MESON_MX_SDIO_CONF
,
264 MESON_MX_SDIO_CONF_BUS_WIDTH
, 0);
267 case MMC_BUS_WIDTH_4
:
268 meson_mx_mmc_mask_bits(mmc
, MESON_MX_SDIO_CONF
,
269 MESON_MX_SDIO_CONF_BUS_WIDTH
,
270 MESON_MX_SDIO_CONF_BUS_WIDTH
);
273 case MMC_BUS_WIDTH_8
:
275 dev_err(mmc_dev(mmc
), "unsupported bus width: %d\n",
277 host
->error
= -EINVAL
;
281 host
->error
= clk_set_rate(host
->cfg_div_clk
, ios
->clock
);
283 dev_warn(mmc_dev(mmc
),
284 "failed to set MMC clock to %lu: %d\n",
285 clk_rate
, host
->error
);
289 mmc
->actual_clock
= clk_get_rate(host
->cfg_div_clk
);
291 switch (ios
->power_mode
) {
296 if (!IS_ERR(mmc
->supply
.vmmc
)) {
297 host
->error
= mmc_regulator_set_ocr(mmc
,
307 static int meson_mx_mmc_map_dma(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
309 struct mmc_data
*data
= mrq
->data
;
311 struct scatterlist
*sg
;
317 if (sg
->offset
& 3 || sg
->length
& 3) {
318 dev_err(mmc_dev(mmc
),
319 "unaligned scatterlist: offset %x length %d\n",
320 sg
->offset
, sg
->length
);
324 dma_len
= dma_map_sg(mmc_dev(mmc
), data
->sg
, data
->sg_len
,
325 mmc_get_dma_dir(data
));
327 dev_err(mmc_dev(mmc
), "dma_map_sg failed\n");
334 static void meson_mx_mmc_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
336 struct meson_mx_mmc_host
*host
= mmc_priv(mmc
);
337 struct mmc_command
*cmd
= mrq
->cmd
;
340 host
->error
= meson_mx_mmc_map_dma(mmc
, mrq
);
343 cmd
->error
= host
->error
;
344 mmc_request_done(mmc
, mrq
);
351 writel(sg_dma_address(mrq
->data
->sg
),
352 host
->base
+ MESON_MX_SDIO_ADDR
);
355 meson_mx_mmc_start_cmd(mmc
, mrq
->sbc
);
357 meson_mx_mmc_start_cmd(mmc
, mrq
->cmd
);
360 static void meson_mx_mmc_read_response(struct mmc_host
*mmc
,
361 struct mmc_command
*cmd
)
363 struct meson_mx_mmc_host
*host
= mmc_priv(mmc
);
367 mult
= readl(host
->base
+ MESON_MX_SDIO_MULT
);
368 mult
|= MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX
;
369 mult
&= ~MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK
;
370 mult
|= FIELD_PREP(MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK
, 0);
371 writel(mult
, host
->base
+ MESON_MX_SDIO_MULT
);
373 if (cmd
->flags
& MMC_RSP_136
) {
374 for (i
= 0; i
<= 3; i
++)
375 resp
[3 - i
] = readl(host
->base
+ MESON_MX_SDIO_ARGU
);
376 cmd
->resp
[0] = (resp
[0] << 8) | ((resp
[1] >> 24) & 0xff);
377 cmd
->resp
[1] = (resp
[1] << 8) | ((resp
[2] >> 24) & 0xff);
378 cmd
->resp
[2] = (resp
[2] << 8) | ((resp
[3] >> 24) & 0xff);
379 cmd
->resp
[3] = (resp
[3] << 8);
380 } else if (cmd
->flags
& MMC_RSP_PRESENT
) {
381 cmd
->resp
[0] = readl(host
->base
+ MESON_MX_SDIO_ARGU
);
385 static irqreturn_t
meson_mx_mmc_process_cmd_irq(struct meson_mx_mmc_host
*host
,
388 struct mmc_command
*cmd
= host
->cmd
;
391 * NOTE: even though it shouldn't happen we sometimes get command
392 * interrupts twice (at least this is what it looks like). Ideally
393 * we find out why this happens and warn here as soon as it occurs.
399 meson_mx_mmc_read_response(host
->mmc
, cmd
);
402 if (!((irqs
& MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK
) ||
403 (irqs
& MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK
)))
404 cmd
->error
= -EILSEQ
;
406 if (!((irqs
& MESON_MX_SDIO_IRQS_RESP_CRC7_OK
) ||
407 (send
& MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7
)))
408 cmd
->error
= -EILSEQ
;
411 return IRQ_WAKE_THREAD
;
414 static irqreturn_t
meson_mx_mmc_irq(int irq
, void *data
)
416 struct meson_mx_mmc_host
*host
= (void *) data
;
418 unsigned long irqflags
;
421 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
423 irqs
= readl(host
->base
+ MESON_MX_SDIO_IRQS
);
424 send
= readl(host
->base
+ MESON_MX_SDIO_SEND
);
426 if (irqs
& MESON_MX_SDIO_IRQS_CMD_INT
)
427 ret
= meson_mx_mmc_process_cmd_irq(host
, irqs
, send
);
431 /* finally ACK all pending interrupts */
432 writel(irqs
, host
->base
+ MESON_MX_SDIO_IRQS
);
434 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
439 static irqreturn_t
meson_mx_mmc_irq_thread(int irq
, void *irq_data
)
441 struct meson_mx_mmc_host
*host
= (void *) irq_data
;
442 struct mmc_command
*cmd
= host
->cmd
, *next_cmd
;
447 del_timer_sync(&host
->cmd_timeout
);
450 dma_unmap_sg(mmc_dev(host
->mmc
), cmd
->data
->sg
,
452 mmc_get_dma_dir(cmd
->data
));
454 cmd
->data
->bytes_xfered
= cmd
->data
->blksz
* cmd
->data
->blocks
;
457 next_cmd
= meson_mx_mmc_get_next_cmd(cmd
);
459 meson_mx_mmc_start_cmd(host
->mmc
, next_cmd
);
461 meson_mx_mmc_request_done(host
);
466 static void meson_mx_mmc_timeout(struct timer_list
*t
)
468 struct meson_mx_mmc_host
*host
= from_timer(host
, t
, cmd_timeout
);
469 unsigned long irqflags
;
472 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
474 /* disable the CMD interrupt */
475 irqc
= readl(host
->base
+ MESON_MX_SDIO_IRQC
);
476 irqc
&= ~MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN
;
477 writel(irqc
, host
->base
+ MESON_MX_SDIO_IRQC
);
479 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
482 * skip the timeout handling if the interrupt handler already processed
488 dev_dbg(mmc_dev(host
->mmc
),
489 "Timeout on CMD%u (IRQS = 0x%08x, ARGU = 0x%08x)\n",
490 host
->cmd
->opcode
, readl(host
->base
+ MESON_MX_SDIO_IRQS
),
491 readl(host
->base
+ MESON_MX_SDIO_ARGU
));
493 host
->cmd
->error
= -ETIMEDOUT
;
495 meson_mx_mmc_request_done(host
);
498 static struct mmc_host_ops meson_mx_mmc_ops
= {
499 .request
= meson_mx_mmc_request
,
500 .set_ios
= meson_mx_mmc_set_ios
,
501 .get_cd
= mmc_gpio_get_cd
,
502 .get_ro
= mmc_gpio_get_ro
,
505 static struct platform_device
*meson_mx_mmc_slot_pdev(struct device
*parent
)
507 struct device_node
*slot_node
;
508 struct platform_device
*pdev
;
511 * TODO: the MMC core framework currently does not support
512 * controllers with multiple slots properly. So we only register
513 * the first slot for now
515 slot_node
= of_get_compatible_child(parent
->of_node
, "mmc-slot");
517 dev_warn(parent
, "no 'mmc-slot' sub-node found\n");
518 return ERR_PTR(-ENOENT
);
521 pdev
= of_platform_device_create(slot_node
, NULL
, parent
);
522 of_node_put(slot_node
);
527 static int meson_mx_mmc_add_host(struct meson_mx_mmc_host
*host
)
529 struct mmc_host
*mmc
= host
->mmc
;
530 struct device
*slot_dev
= mmc_dev(mmc
);
533 if (of_property_read_u32(slot_dev
->of_node
, "reg", &host
->slot_id
)) {
534 dev_err(slot_dev
, "missing 'reg' property\n");
538 if (host
->slot_id
>= MESON_MX_SDIO_MAX_SLOTS
) {
539 dev_err(slot_dev
, "invalid 'reg' property value %d\n",
544 /* Get regulators and the supported OCR mask */
545 ret
= mmc_regulator_get_supply(mmc
);
549 mmc
->max_req_size
= MESON_MX_SDIO_BOUNCE_REQ_SIZE
;
550 mmc
->max_seg_size
= mmc
->max_req_size
;
552 FIELD_GET(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK
,
554 mmc
->max_blk_size
= FIELD_GET(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK
,
556 mmc
->max_blk_size
-= (4 * MESON_MX_SDIO_RESPONSE_CRC16_BITS
);
557 mmc
->max_blk_size
/= BITS_PER_BYTE
;
559 /* Get the min and max supported clock rates */
560 mmc
->f_min
= clk_round_rate(host
->cfg_div_clk
, 1);
561 mmc
->f_max
= clk_round_rate(host
->cfg_div_clk
,
562 clk_get_rate(host
->parent_clk
));
564 mmc
->caps
|= MMC_CAP_ERASE
| MMC_CAP_CMD23
| MMC_CAP_WAIT_WHILE_BUSY
;
565 mmc
->ops
= &meson_mx_mmc_ops
;
567 ret
= mmc_of_parse(mmc
);
571 ret
= mmc_add_host(mmc
);
578 static int meson_mx_mmc_register_clks(struct meson_mx_mmc_host
*host
)
580 struct clk_init_data init
;
581 const char *clk_div_parent
, *clk_fixed_factor_parent
;
583 clk_fixed_factor_parent
= __clk_get_name(host
->parent_clk
);
584 init
.name
= devm_kasprintf(host
->controller_dev
, GFP_KERNEL
,
586 dev_name(host
->controller_dev
));
590 init
.ops
= &clk_fixed_factor_ops
;
592 init
.parent_names
= &clk_fixed_factor_parent
;
593 init
.num_parents
= 1;
594 host
->fixed_factor
.div
= 2;
595 host
->fixed_factor
.mult
= 1;
596 host
->fixed_factor
.hw
.init
= &init
;
598 host
->fixed_factor_clk
= devm_clk_register(host
->controller_dev
,
599 &host
->fixed_factor
.hw
);
600 if (WARN_ON(IS_ERR(host
->fixed_factor_clk
)))
601 return PTR_ERR(host
->fixed_factor_clk
);
603 clk_div_parent
= __clk_get_name(host
->fixed_factor_clk
);
604 init
.name
= devm_kasprintf(host
->controller_dev
, GFP_KERNEL
,
605 "%s#div", dev_name(host
->controller_dev
));
609 init
.ops
= &clk_divider_ops
;
610 init
.flags
= CLK_SET_RATE_PARENT
;
611 init
.parent_names
= &clk_div_parent
;
612 init
.num_parents
= 1;
613 host
->cfg_div
.reg
= host
->base
+ MESON_MX_SDIO_CONF
;
614 host
->cfg_div
.shift
= MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT
;
615 host
->cfg_div
.width
= MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH
;
616 host
->cfg_div
.hw
.init
= &init
;
617 host
->cfg_div
.flags
= CLK_DIVIDER_ALLOW_ZERO
;
619 host
->cfg_div_clk
= devm_clk_register(host
->controller_dev
,
621 if (WARN_ON(IS_ERR(host
->cfg_div_clk
)))
622 return PTR_ERR(host
->cfg_div_clk
);
627 static int meson_mx_mmc_probe(struct platform_device
*pdev
)
629 struct platform_device
*slot_pdev
;
630 struct mmc_host
*mmc
;
631 struct meson_mx_mmc_host
*host
;
635 slot_pdev
= meson_mx_mmc_slot_pdev(&pdev
->dev
);
638 else if (IS_ERR(slot_pdev
))
639 return PTR_ERR(slot_pdev
);
641 mmc
= mmc_alloc_host(sizeof(*host
), &slot_pdev
->dev
);
644 goto error_unregister_slot_pdev
;
647 host
= mmc_priv(mmc
);
649 host
->controller_dev
= &pdev
->dev
;
651 spin_lock_init(&host
->irq_lock
);
652 timer_setup(&host
->cmd_timeout
, meson_mx_mmc_timeout
, 0);
654 platform_set_drvdata(pdev
, host
);
656 host
->base
= devm_platform_ioremap_resource(pdev
, 0);
657 if (IS_ERR(host
->base
)) {
658 ret
= PTR_ERR(host
->base
);
662 irq
= platform_get_irq(pdev
, 0);
663 ret
= devm_request_threaded_irq(host
->controller_dev
, irq
,
665 meson_mx_mmc_irq_thread
, IRQF_ONESHOT
,
670 host
->core_clk
= devm_clk_get(host
->controller_dev
, "core");
671 if (IS_ERR(host
->core_clk
)) {
672 ret
= PTR_ERR(host
->core_clk
);
676 host
->parent_clk
= devm_clk_get(host
->controller_dev
, "clkin");
677 if (IS_ERR(host
->parent_clk
)) {
678 ret
= PTR_ERR(host
->parent_clk
);
682 ret
= meson_mx_mmc_register_clks(host
);
686 ret
= clk_prepare_enable(host
->core_clk
);
688 dev_err(host
->controller_dev
, "Failed to enable core clock\n");
692 ret
= clk_prepare_enable(host
->cfg_div_clk
);
694 dev_err(host
->controller_dev
, "Failed to enable MMC clock\n");
695 goto error_disable_core_clk
;
699 conf
|= FIELD_PREP(MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK
, 39);
700 conf
|= FIELD_PREP(MESON_MX_SDIO_CONF_M_ENDIAN_MASK
, 0x3);
701 conf
|= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_NWR_MASK
, 0x2);
702 conf
|= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK
, 0x2);
703 writel(conf
, host
->base
+ MESON_MX_SDIO_CONF
);
705 meson_mx_mmc_soft_reset(host
);
707 ret
= meson_mx_mmc_add_host(host
);
709 goto error_disable_clks
;
714 clk_disable_unprepare(host
->cfg_div_clk
);
715 error_disable_core_clk
:
716 clk_disable_unprepare(host
->core_clk
);
719 error_unregister_slot_pdev
:
720 of_platform_device_destroy(&slot_pdev
->dev
, NULL
);
724 static int meson_mx_mmc_remove(struct platform_device
*pdev
)
726 struct meson_mx_mmc_host
*host
= platform_get_drvdata(pdev
);
727 struct device
*slot_dev
= mmc_dev(host
->mmc
);
729 del_timer_sync(&host
->cmd_timeout
);
731 mmc_remove_host(host
->mmc
);
733 of_platform_device_destroy(slot_dev
, NULL
);
735 clk_disable_unprepare(host
->cfg_div_clk
);
736 clk_disable_unprepare(host
->core_clk
);
738 mmc_free_host(host
->mmc
);
743 static const struct of_device_id meson_mx_mmc_of_match
[] = {
744 { .compatible
= "amlogic,meson8-sdio", },
745 { .compatible
= "amlogic,meson8b-sdio", },
748 MODULE_DEVICE_TABLE(of
, meson_mx_mmc_of_match
);
750 static struct platform_driver meson_mx_mmc_driver
= {
751 .probe
= meson_mx_mmc_probe
,
752 .remove
= meson_mx_mmc_remove
,
754 .name
= "meson-mx-sdio",
755 .of_match_table
= of_match_ptr(meson_mx_mmc_of_match
),
759 module_platform_driver(meson_mx_mmc_driver
);
761 MODULE_DESCRIPTION("Meson6, Meson8 and Meson8b SDIO/MMC Host Driver");
762 MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
763 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
764 MODULE_LICENSE("GPL v2");