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[thirdparty/kernel/stable.git] / drivers / mmc / host / mmci.c
1 /*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/io.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/highmem.h>
23 #include <linux/log2.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/mmc/pm.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/card.h>
28 #include <linux/mmc/slot-gpio.h>
29 #include <linux/amba/bus.h>
30 #include <linux/clk.h>
31 #include <linux/scatterlist.h>
32 #include <linux/of.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/amba/mmci.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/types.h>
39 #include <linux/pinctrl/consumer.h>
40 #include <linux/reset.h>
41
42 #include <asm/div64.h>
43 #include <asm/io.h>
44
45 #include "mmci.h"
46
47 #define DRIVER_NAME "mmci-pl18x"
48
49 static void mmci_variant_init(struct mmci_host *host);
50 static void ux500v2_variant_init(struct mmci_host *host);
51
52 static unsigned int fmax = 515633;
53
54 static struct variant_data variant_arm = {
55 .fifosize = 16 * 4,
56 .fifohalfsize = 8 * 4,
57 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
58 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
59 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
60 .cmdreg_srsp = MCI_CPSM_RESPONSE,
61 .datalength_bits = 16,
62 .datactrl_blocksz = 11,
63 .pwrreg_powerup = MCI_PWR_UP,
64 .f_max = 100000000,
65 .reversed_irq_handling = true,
66 .mmcimask1 = true,
67 .irq_pio_mask = MCI_IRQ_PIO_MASK,
68 .start_err = MCI_STARTBITERR,
69 .opendrain = MCI_ROD,
70 .init = mmci_variant_init,
71 };
72
73 static struct variant_data variant_arm_extended_fifo = {
74 .fifosize = 128 * 4,
75 .fifohalfsize = 64 * 4,
76 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
77 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
78 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
79 .cmdreg_srsp = MCI_CPSM_RESPONSE,
80 .datalength_bits = 16,
81 .datactrl_blocksz = 11,
82 .pwrreg_powerup = MCI_PWR_UP,
83 .f_max = 100000000,
84 .mmcimask1 = true,
85 .irq_pio_mask = MCI_IRQ_PIO_MASK,
86 .start_err = MCI_STARTBITERR,
87 .opendrain = MCI_ROD,
88 .init = mmci_variant_init,
89 };
90
91 static struct variant_data variant_arm_extended_fifo_hwfc = {
92 .fifosize = 128 * 4,
93 .fifohalfsize = 64 * 4,
94 .clkreg_enable = MCI_ARM_HWFCEN,
95 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
96 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
97 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
98 .cmdreg_srsp = MCI_CPSM_RESPONSE,
99 .datalength_bits = 16,
100 .datactrl_blocksz = 11,
101 .pwrreg_powerup = MCI_PWR_UP,
102 .f_max = 100000000,
103 .mmcimask1 = true,
104 .irq_pio_mask = MCI_IRQ_PIO_MASK,
105 .start_err = MCI_STARTBITERR,
106 .opendrain = MCI_ROD,
107 .init = mmci_variant_init,
108 };
109
110 static struct variant_data variant_u300 = {
111 .fifosize = 16 * 4,
112 .fifohalfsize = 8 * 4,
113 .clkreg_enable = MCI_ST_U300_HWFCEN,
114 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
115 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
116 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
117 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
118 .cmdreg_srsp = MCI_CPSM_RESPONSE,
119 .datalength_bits = 16,
120 .datactrl_blocksz = 11,
121 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
122 .st_sdio = true,
123 .pwrreg_powerup = MCI_PWR_ON,
124 .f_max = 100000000,
125 .signal_direction = true,
126 .pwrreg_clkgate = true,
127 .pwrreg_nopower = true,
128 .mmcimask1 = true,
129 .irq_pio_mask = MCI_IRQ_PIO_MASK,
130 .start_err = MCI_STARTBITERR,
131 .opendrain = MCI_OD,
132 .init = mmci_variant_init,
133 };
134
135 static struct variant_data variant_nomadik = {
136 .fifosize = 16 * 4,
137 .fifohalfsize = 8 * 4,
138 .clkreg = MCI_CLK_ENABLE,
139 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
140 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
141 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
142 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
143 .cmdreg_srsp = MCI_CPSM_RESPONSE,
144 .datalength_bits = 24,
145 .datactrl_blocksz = 11,
146 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
147 .st_sdio = true,
148 .st_clkdiv = true,
149 .pwrreg_powerup = MCI_PWR_ON,
150 .f_max = 100000000,
151 .signal_direction = true,
152 .pwrreg_clkgate = true,
153 .pwrreg_nopower = true,
154 .mmcimask1 = true,
155 .irq_pio_mask = MCI_IRQ_PIO_MASK,
156 .start_err = MCI_STARTBITERR,
157 .opendrain = MCI_OD,
158 .init = mmci_variant_init,
159 };
160
161 static struct variant_data variant_ux500 = {
162 .fifosize = 30 * 4,
163 .fifohalfsize = 8 * 4,
164 .clkreg = MCI_CLK_ENABLE,
165 .clkreg_enable = MCI_ST_UX500_HWFCEN,
166 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
167 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
168 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
169 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
170 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
171 .cmdreg_srsp = MCI_CPSM_RESPONSE,
172 .datalength_bits = 24,
173 .datactrl_blocksz = 11,
174 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
175 .st_sdio = true,
176 .st_clkdiv = true,
177 .pwrreg_powerup = MCI_PWR_ON,
178 .f_max = 100000000,
179 .signal_direction = true,
180 .pwrreg_clkgate = true,
181 .busy_detect = true,
182 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
183 .busy_detect_flag = MCI_ST_CARDBUSY,
184 .busy_detect_mask = MCI_ST_BUSYENDMASK,
185 .pwrreg_nopower = true,
186 .mmcimask1 = true,
187 .irq_pio_mask = MCI_IRQ_PIO_MASK,
188 .start_err = MCI_STARTBITERR,
189 .opendrain = MCI_OD,
190 .init = mmci_variant_init,
191 };
192
193 static struct variant_data variant_ux500v2 = {
194 .fifosize = 30 * 4,
195 .fifohalfsize = 8 * 4,
196 .clkreg = MCI_CLK_ENABLE,
197 .clkreg_enable = MCI_ST_UX500_HWFCEN,
198 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
199 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
200 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
201 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
202 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
203 .cmdreg_srsp = MCI_CPSM_RESPONSE,
204 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE,
205 .datalength_bits = 24,
206 .datactrl_blocksz = 11,
207 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
208 .st_sdio = true,
209 .st_clkdiv = true,
210 .pwrreg_powerup = MCI_PWR_ON,
211 .f_max = 100000000,
212 .signal_direction = true,
213 .pwrreg_clkgate = true,
214 .busy_detect = true,
215 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
216 .busy_detect_flag = MCI_ST_CARDBUSY,
217 .busy_detect_mask = MCI_ST_BUSYENDMASK,
218 .pwrreg_nopower = true,
219 .mmcimask1 = true,
220 .irq_pio_mask = MCI_IRQ_PIO_MASK,
221 .start_err = MCI_STARTBITERR,
222 .opendrain = MCI_OD,
223 .init = ux500v2_variant_init,
224 };
225
226 static struct variant_data variant_stm32 = {
227 .fifosize = 32 * 4,
228 .fifohalfsize = 8 * 4,
229 .clkreg = MCI_CLK_ENABLE,
230 .clkreg_enable = MCI_ST_UX500_HWFCEN,
231 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
232 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
233 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
234 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
235 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
236 .cmdreg_srsp = MCI_CPSM_RESPONSE,
237 .irq_pio_mask = MCI_IRQ_PIO_MASK,
238 .datalength_bits = 24,
239 .datactrl_blocksz = 11,
240 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
241 .st_sdio = true,
242 .st_clkdiv = true,
243 .pwrreg_powerup = MCI_PWR_ON,
244 .f_max = 48000000,
245 .pwrreg_clkgate = true,
246 .pwrreg_nopower = true,
247 .init = mmci_variant_init,
248 };
249
250 static struct variant_data variant_stm32_sdmmc = {
251 .fifosize = 16 * 4,
252 .fifohalfsize = 8 * 4,
253 .f_max = 208000000,
254 .stm32_clkdiv = true,
255 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
256 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,
257 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC,
258 .cmdreg_srsp = MCI_CPSM_STM32_SRSP,
259 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP,
260 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS,
261 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK,
262 .datactrl_first = true,
263 .datacnt_useless = true,
264 .datalength_bits = 25,
265 .datactrl_blocksz = 14,
266 .stm32_idmabsize_mask = GENMASK(12, 5),
267 .init = sdmmc_variant_init,
268 };
269
270 static struct variant_data variant_qcom = {
271 .fifosize = 16 * 4,
272 .fifohalfsize = 8 * 4,
273 .clkreg = MCI_CLK_ENABLE,
274 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
275 MCI_QCOM_CLK_SELECT_IN_FBCLK,
276 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
277 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
278 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
279 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
280 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
281 .cmdreg_srsp = MCI_CPSM_RESPONSE,
282 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD,
283 .datalength_bits = 24,
284 .datactrl_blocksz = 11,
285 .pwrreg_powerup = MCI_PWR_UP,
286 .f_max = 208000000,
287 .explicit_mclk_control = true,
288 .qcom_fifo = true,
289 .qcom_dml = true,
290 .mmcimask1 = true,
291 .irq_pio_mask = MCI_IRQ_PIO_MASK,
292 .start_err = MCI_STARTBITERR,
293 .opendrain = MCI_ROD,
294 .init = qcom_variant_init,
295 };
296
297 /* Busy detection for the ST Micro variant */
298 static int mmci_card_busy(struct mmc_host *mmc)
299 {
300 struct mmci_host *host = mmc_priv(mmc);
301 unsigned long flags;
302 int busy = 0;
303
304 spin_lock_irqsave(&host->lock, flags);
305 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
306 busy = 1;
307 spin_unlock_irqrestore(&host->lock, flags);
308
309 return busy;
310 }
311
312 static void mmci_reg_delay(struct mmci_host *host)
313 {
314 /*
315 * According to the spec, at least three feedback clock cycles
316 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
317 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
318 * Worst delay time during card init is at 100 kHz => 30 us.
319 * Worst delay time when up and running is at 25 MHz => 120 ns.
320 */
321 if (host->cclk < 25000000)
322 udelay(30);
323 else
324 ndelay(120);
325 }
326
327 /*
328 * This must be called with host->lock held
329 */
330 void mmci_write_clkreg(struct mmci_host *host, u32 clk)
331 {
332 if (host->clk_reg != clk) {
333 host->clk_reg = clk;
334 writel(clk, host->base + MMCICLOCK);
335 }
336 }
337
338 /*
339 * This must be called with host->lock held
340 */
341 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
342 {
343 if (host->pwr_reg != pwr) {
344 host->pwr_reg = pwr;
345 writel(pwr, host->base + MMCIPOWER);
346 }
347 }
348
349 /*
350 * This must be called with host->lock held
351 */
352 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
353 {
354 /* Keep busy mode in DPSM if enabled */
355 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
356
357 if (host->datactrl_reg != datactrl) {
358 host->datactrl_reg = datactrl;
359 writel(datactrl, host->base + MMCIDATACTRL);
360 }
361 }
362
363 /*
364 * This must be called with host->lock held
365 */
366 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
367 {
368 struct variant_data *variant = host->variant;
369 u32 clk = variant->clkreg;
370
371 /* Make sure cclk reflects the current calculated clock */
372 host->cclk = 0;
373
374 if (desired) {
375 if (variant->explicit_mclk_control) {
376 host->cclk = host->mclk;
377 } else if (desired >= host->mclk) {
378 clk = MCI_CLK_BYPASS;
379 if (variant->st_clkdiv)
380 clk |= MCI_ST_UX500_NEG_EDGE;
381 host->cclk = host->mclk;
382 } else if (variant->st_clkdiv) {
383 /*
384 * DB8500 TRM says f = mclk / (clkdiv + 2)
385 * => clkdiv = (mclk / f) - 2
386 * Round the divider up so we don't exceed the max
387 * frequency
388 */
389 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
390 if (clk >= 256)
391 clk = 255;
392 host->cclk = host->mclk / (clk + 2);
393 } else {
394 /*
395 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
396 * => clkdiv = mclk / (2 * f) - 1
397 */
398 clk = host->mclk / (2 * desired) - 1;
399 if (clk >= 256)
400 clk = 255;
401 host->cclk = host->mclk / (2 * (clk + 1));
402 }
403
404 clk |= variant->clkreg_enable;
405 clk |= MCI_CLK_ENABLE;
406 /* This hasn't proven to be worthwhile */
407 /* clk |= MCI_CLK_PWRSAVE; */
408 }
409
410 /* Set actual clock for debug */
411 host->mmc->actual_clock = host->cclk;
412
413 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
414 clk |= MCI_4BIT_BUS;
415 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
416 clk |= variant->clkreg_8bit_bus_enable;
417
418 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
419 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
420 clk |= variant->clkreg_neg_edge_enable;
421
422 mmci_write_clkreg(host, clk);
423 }
424
425 void mmci_dma_release(struct mmci_host *host)
426 {
427 if (host->ops && host->ops->dma_release)
428 host->ops->dma_release(host);
429
430 host->use_dma = false;
431 }
432
433 void mmci_dma_setup(struct mmci_host *host)
434 {
435 if (!host->ops || !host->ops->dma_setup)
436 return;
437
438 if (host->ops->dma_setup(host))
439 return;
440
441 /* initialize pre request cookie */
442 host->next_cookie = 1;
443
444 host->use_dma = true;
445 }
446
447 /*
448 * Validate mmc prerequisites
449 */
450 static int mmci_validate_data(struct mmci_host *host,
451 struct mmc_data *data)
452 {
453 if (!data)
454 return 0;
455
456 if (!is_power_of_2(data->blksz)) {
457 dev_err(mmc_dev(host->mmc),
458 "unsupported block size (%d bytes)\n", data->blksz);
459 return -EINVAL;
460 }
461
462 if (host->ops && host->ops->validate_data)
463 return host->ops->validate_data(host, data);
464
465 return 0;
466 }
467
468 int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next)
469 {
470 int err;
471
472 if (!host->ops || !host->ops->prep_data)
473 return 0;
474
475 err = host->ops->prep_data(host, data, next);
476
477 if (next && !err)
478 data->host_cookie = ++host->next_cookie < 0 ?
479 1 : host->next_cookie;
480
481 return err;
482 }
483
484 void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data,
485 int err)
486 {
487 if (host->ops && host->ops->unprep_data)
488 host->ops->unprep_data(host, data, err);
489
490 data->host_cookie = 0;
491 }
492
493 void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
494 {
495 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);
496
497 if (host->ops && host->ops->get_next_data)
498 host->ops->get_next_data(host, data);
499 }
500
501 int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)
502 {
503 struct mmc_data *data = host->data;
504 int ret;
505
506 if (!host->use_dma)
507 return -EINVAL;
508
509 ret = mmci_prep_data(host, data, false);
510 if (ret)
511 return ret;
512
513 if (!host->ops || !host->ops->dma_start)
514 return -EINVAL;
515
516 /* Okay, go for it. */
517 dev_vdbg(mmc_dev(host->mmc),
518 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
519 data->sg_len, data->blksz, data->blocks, data->flags);
520
521 host->ops->dma_start(host, &datactrl);
522
523 /* Trigger the DMA transfer */
524 mmci_write_datactrlreg(host, datactrl);
525
526 /*
527 * Let the MMCI say when the data is ended and it's time
528 * to fire next DMA request. When that happens, MMCI will
529 * call mmci_data_end()
530 */
531 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
532 host->base + MMCIMASK0);
533 return 0;
534 }
535
536 void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
537 {
538 if (!host->use_dma)
539 return;
540
541 if (host->ops && host->ops->dma_finalize)
542 host->ops->dma_finalize(host, data);
543 }
544
545 void mmci_dma_error(struct mmci_host *host)
546 {
547 if (!host->use_dma)
548 return;
549
550 if (host->ops && host->ops->dma_error)
551 host->ops->dma_error(host);
552 }
553
554 static void
555 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
556 {
557 writel(0, host->base + MMCICOMMAND);
558
559 BUG_ON(host->data);
560
561 host->mrq = NULL;
562 host->cmd = NULL;
563
564 mmc_request_done(host->mmc, mrq);
565 }
566
567 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
568 {
569 void __iomem *base = host->base;
570 struct variant_data *variant = host->variant;
571
572 if (host->singleirq) {
573 unsigned int mask0 = readl(base + MMCIMASK0);
574
575 mask0 &= ~variant->irq_pio_mask;
576 mask0 |= mask;
577
578 writel(mask0, base + MMCIMASK0);
579 }
580
581 if (variant->mmcimask1)
582 writel(mask, base + MMCIMASK1);
583
584 host->mask1_reg = mask;
585 }
586
587 static void mmci_stop_data(struct mmci_host *host)
588 {
589 mmci_write_datactrlreg(host, 0);
590 mmci_set_mask1(host, 0);
591 host->data = NULL;
592 }
593
594 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
595 {
596 unsigned int flags = SG_MITER_ATOMIC;
597
598 if (data->flags & MMC_DATA_READ)
599 flags |= SG_MITER_TO_SG;
600 else
601 flags |= SG_MITER_FROM_SG;
602
603 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
604 }
605
606 static u32 mmci_get_dctrl_cfg(struct mmci_host *host)
607 {
608 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host);
609 }
610
611 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host)
612 {
613 return MCI_DPSM_ENABLE | (host->data->blksz << 16);
614 }
615
616 /*
617 * All the DMA operation mode stuff goes inside this ifdef.
618 * This assumes that you have a generic DMA device interface,
619 * no custom DMA interfaces are supported.
620 */
621 #ifdef CONFIG_DMA_ENGINE
622 struct mmci_dmae_next {
623 struct dma_async_tx_descriptor *desc;
624 struct dma_chan *chan;
625 };
626
627 struct mmci_dmae_priv {
628 struct dma_chan *cur;
629 struct dma_chan *rx_channel;
630 struct dma_chan *tx_channel;
631 struct dma_async_tx_descriptor *desc_current;
632 struct mmci_dmae_next next_data;
633 };
634
635 int mmci_dmae_setup(struct mmci_host *host)
636 {
637 const char *rxname, *txname;
638 struct mmci_dmae_priv *dmae;
639
640 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL);
641 if (!dmae)
642 return -ENOMEM;
643
644 host->dma_priv = dmae;
645
646 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc),
647 "rx");
648 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc),
649 "tx");
650
651 /*
652 * If only an RX channel is specified, the driver will
653 * attempt to use it bidirectionally, however if it is
654 * is specified but cannot be located, DMA will be disabled.
655 */
656 if (dmae->rx_channel && !dmae->tx_channel)
657 dmae->tx_channel = dmae->rx_channel;
658
659 if (dmae->rx_channel)
660 rxname = dma_chan_name(dmae->rx_channel);
661 else
662 rxname = "none";
663
664 if (dmae->tx_channel)
665 txname = dma_chan_name(dmae->tx_channel);
666 else
667 txname = "none";
668
669 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
670 rxname, txname);
671
672 /*
673 * Limit the maximum segment size in any SG entry according to
674 * the parameters of the DMA engine device.
675 */
676 if (dmae->tx_channel) {
677 struct device *dev = dmae->tx_channel->device->dev;
678 unsigned int max_seg_size = dma_get_max_seg_size(dev);
679
680 if (max_seg_size < host->mmc->max_seg_size)
681 host->mmc->max_seg_size = max_seg_size;
682 }
683 if (dmae->rx_channel) {
684 struct device *dev = dmae->rx_channel->device->dev;
685 unsigned int max_seg_size = dma_get_max_seg_size(dev);
686
687 if (max_seg_size < host->mmc->max_seg_size)
688 host->mmc->max_seg_size = max_seg_size;
689 }
690
691 if (!dmae->tx_channel || !dmae->rx_channel) {
692 mmci_dmae_release(host);
693 return -EINVAL;
694 }
695
696 return 0;
697 }
698
699 /*
700 * This is used in or so inline it
701 * so it can be discarded.
702 */
703 void mmci_dmae_release(struct mmci_host *host)
704 {
705 struct mmci_dmae_priv *dmae = host->dma_priv;
706
707 if (dmae->rx_channel)
708 dma_release_channel(dmae->rx_channel);
709 if (dmae->tx_channel)
710 dma_release_channel(dmae->tx_channel);
711 dmae->rx_channel = dmae->tx_channel = NULL;
712 }
713
714 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
715 {
716 struct mmci_dmae_priv *dmae = host->dma_priv;
717 struct dma_chan *chan;
718
719 if (data->flags & MMC_DATA_READ)
720 chan = dmae->rx_channel;
721 else
722 chan = dmae->tx_channel;
723
724 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
725 mmc_get_dma_dir(data));
726 }
727
728 void mmci_dmae_error(struct mmci_host *host)
729 {
730 struct mmci_dmae_priv *dmae = host->dma_priv;
731
732 if (!dma_inprogress(host))
733 return;
734
735 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
736 dmaengine_terminate_all(dmae->cur);
737 host->dma_in_progress = false;
738 dmae->cur = NULL;
739 dmae->desc_current = NULL;
740 host->data->host_cookie = 0;
741
742 mmci_dma_unmap(host, host->data);
743 }
744
745 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data)
746 {
747 struct mmci_dmae_priv *dmae = host->dma_priv;
748 u32 status;
749 int i;
750
751 if (!dma_inprogress(host))
752 return;
753
754 /* Wait up to 1ms for the DMA to complete */
755 for (i = 0; ; i++) {
756 status = readl(host->base + MMCISTATUS);
757 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
758 break;
759 udelay(10);
760 }
761
762 /*
763 * Check to see whether we still have some data left in the FIFO -
764 * this catches DMA controllers which are unable to monitor the
765 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
766 * contiguous buffers. On TX, we'll get a FIFO underrun error.
767 */
768 if (status & MCI_RXDATAAVLBLMASK) {
769 mmci_dma_error(host);
770 if (!data->error)
771 data->error = -EIO;
772 } else if (!data->host_cookie) {
773 mmci_dma_unmap(host, data);
774 }
775
776 /*
777 * Use of DMA with scatter-gather is impossible.
778 * Give up with DMA and switch back to PIO mode.
779 */
780 if (status & MCI_RXDATAAVLBLMASK) {
781 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
782 mmci_dma_release(host);
783 }
784
785 host->dma_in_progress = false;
786 dmae->cur = NULL;
787 dmae->desc_current = NULL;
788 }
789
790 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
791 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
792 struct dma_chan **dma_chan,
793 struct dma_async_tx_descriptor **dma_desc)
794 {
795 struct mmci_dmae_priv *dmae = host->dma_priv;
796 struct variant_data *variant = host->variant;
797 struct dma_slave_config conf = {
798 .src_addr = host->phybase + MMCIFIFO,
799 .dst_addr = host->phybase + MMCIFIFO,
800 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
801 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
802 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
803 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
804 .device_fc = false,
805 };
806 struct dma_chan *chan;
807 struct dma_device *device;
808 struct dma_async_tx_descriptor *desc;
809 int nr_sg;
810 unsigned long flags = DMA_CTRL_ACK;
811
812 if (data->flags & MMC_DATA_READ) {
813 conf.direction = DMA_DEV_TO_MEM;
814 chan = dmae->rx_channel;
815 } else {
816 conf.direction = DMA_MEM_TO_DEV;
817 chan = dmae->tx_channel;
818 }
819
820 /* If there's no DMA channel, fall back to PIO */
821 if (!chan)
822 return -EINVAL;
823
824 /* If less than or equal to the fifo size, don't bother with DMA */
825 if (data->blksz * data->blocks <= variant->fifosize)
826 return -EINVAL;
827
828 device = chan->device;
829 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len,
830 mmc_get_dma_dir(data));
831 if (nr_sg == 0)
832 return -EINVAL;
833
834 if (host->variant->qcom_dml)
835 flags |= DMA_PREP_INTERRUPT;
836
837 dmaengine_slave_config(chan, &conf);
838 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
839 conf.direction, flags);
840 if (!desc)
841 goto unmap_exit;
842
843 *dma_chan = chan;
844 *dma_desc = desc;
845
846 return 0;
847
848 unmap_exit:
849 dma_unmap_sg(device->dev, data->sg, data->sg_len,
850 mmc_get_dma_dir(data));
851 return -ENOMEM;
852 }
853
854 int mmci_dmae_prep_data(struct mmci_host *host,
855 struct mmc_data *data,
856 bool next)
857 {
858 struct mmci_dmae_priv *dmae = host->dma_priv;
859 struct mmci_dmae_next *nd = &dmae->next_data;
860
861 if (!host->use_dma)
862 return -EINVAL;
863
864 if (next)
865 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc);
866 /* Check if next job is already prepared. */
867 if (dmae->cur && dmae->desc_current)
868 return 0;
869
870 /* No job were prepared thus do it now. */
871 return _mmci_dmae_prep_data(host, data, &dmae->cur,
872 &dmae->desc_current);
873 }
874
875 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl)
876 {
877 struct mmci_dmae_priv *dmae = host->dma_priv;
878
879 host->dma_in_progress = true;
880 dmaengine_submit(dmae->desc_current);
881 dma_async_issue_pending(dmae->cur);
882
883 *datactrl |= MCI_DPSM_DMAENABLE;
884
885 return 0;
886 }
887
888 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data)
889 {
890 struct mmci_dmae_priv *dmae = host->dma_priv;
891 struct mmci_dmae_next *next = &dmae->next_data;
892
893 if (!host->use_dma)
894 return;
895
896 WARN_ON(!data->host_cookie && (next->desc || next->chan));
897
898 dmae->desc_current = next->desc;
899 dmae->cur = next->chan;
900 next->desc = NULL;
901 next->chan = NULL;
902 }
903
904 void mmci_dmae_unprep_data(struct mmci_host *host,
905 struct mmc_data *data, int err)
906
907 {
908 struct mmci_dmae_priv *dmae = host->dma_priv;
909
910 if (!host->use_dma)
911 return;
912
913 mmci_dma_unmap(host, data);
914
915 if (err) {
916 struct mmci_dmae_next *next = &dmae->next_data;
917 struct dma_chan *chan;
918 if (data->flags & MMC_DATA_READ)
919 chan = dmae->rx_channel;
920 else
921 chan = dmae->tx_channel;
922 dmaengine_terminate_all(chan);
923
924 if (dmae->desc_current == next->desc)
925 dmae->desc_current = NULL;
926
927 if (dmae->cur == next->chan) {
928 host->dma_in_progress = false;
929 dmae->cur = NULL;
930 }
931
932 next->desc = NULL;
933 next->chan = NULL;
934 }
935 }
936
937 static struct mmci_host_ops mmci_variant_ops = {
938 .prep_data = mmci_dmae_prep_data,
939 .unprep_data = mmci_dmae_unprep_data,
940 .get_datactrl_cfg = mmci_get_dctrl_cfg,
941 .get_next_data = mmci_dmae_get_next_data,
942 .dma_setup = mmci_dmae_setup,
943 .dma_release = mmci_dmae_release,
944 .dma_start = mmci_dmae_start,
945 .dma_finalize = mmci_dmae_finalize,
946 .dma_error = mmci_dmae_error,
947 };
948 #else
949 static struct mmci_host_ops mmci_variant_ops = {
950 .get_datactrl_cfg = mmci_get_dctrl_cfg,
951 };
952 #endif
953
954 void mmci_variant_init(struct mmci_host *host)
955 {
956 host->ops = &mmci_variant_ops;
957 }
958
959 void ux500v2_variant_init(struct mmci_host *host)
960 {
961 host->ops = &mmci_variant_ops;
962 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg;
963 }
964
965 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
966 {
967 struct mmci_host *host = mmc_priv(mmc);
968 struct mmc_data *data = mrq->data;
969
970 if (!data)
971 return;
972
973 WARN_ON(data->host_cookie);
974
975 if (mmci_validate_data(host, data))
976 return;
977
978 mmci_prep_data(host, data, true);
979 }
980
981 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
982 int err)
983 {
984 struct mmci_host *host = mmc_priv(mmc);
985 struct mmc_data *data = mrq->data;
986
987 if (!data || !data->host_cookie)
988 return;
989
990 mmci_unprep_data(host, data, err);
991 }
992
993 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
994 {
995 struct variant_data *variant = host->variant;
996 unsigned int datactrl, timeout, irqmask;
997 unsigned long long clks;
998 void __iomem *base;
999
1000 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
1001 data->blksz, data->blocks, data->flags);
1002
1003 host->data = data;
1004 host->size = data->blksz * data->blocks;
1005 data->bytes_xfered = 0;
1006
1007 clks = (unsigned long long)data->timeout_ns * host->cclk;
1008 do_div(clks, NSEC_PER_SEC);
1009
1010 timeout = data->timeout_clks + (unsigned int)clks;
1011
1012 base = host->base;
1013 writel(timeout, base + MMCIDATATIMER);
1014 writel(host->size, base + MMCIDATALENGTH);
1015
1016 datactrl = host->ops->get_datactrl_cfg(host);
1017 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0;
1018
1019 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
1020 u32 clk;
1021
1022 datactrl |= variant->datactrl_mask_sdio;
1023
1024 /*
1025 * The ST Micro variant for SDIO small write transfers
1026 * needs to have clock H/W flow control disabled,
1027 * otherwise the transfer will not start. The threshold
1028 * depends on the rate of MCLK.
1029 */
1030 if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
1031 (host->size < 8 ||
1032 (host->size <= 8 && host->mclk > 50000000)))
1033 clk = host->clk_reg & ~variant->clkreg_enable;
1034 else
1035 clk = host->clk_reg | variant->clkreg_enable;
1036
1037 mmci_write_clkreg(host, clk);
1038 }
1039
1040 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
1041 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
1042 datactrl |= variant->datactrl_mask_ddrmode;
1043
1044 /*
1045 * Attempt to use DMA operation mode, if this
1046 * should fail, fall back to PIO mode
1047 */
1048 if (!mmci_dma_start(host, datactrl))
1049 return;
1050
1051 /* IRQ mode, map the SG list for CPU reading/writing */
1052 mmci_init_sg(host, data);
1053
1054 if (data->flags & MMC_DATA_READ) {
1055 irqmask = MCI_RXFIFOHALFFULLMASK;
1056
1057 /*
1058 * If we have less than the fifo 'half-full' threshold to
1059 * transfer, trigger a PIO interrupt as soon as any data
1060 * is available.
1061 */
1062 if (host->size < variant->fifohalfsize)
1063 irqmask |= MCI_RXDATAAVLBLMASK;
1064 } else {
1065 /*
1066 * We don't actually need to include "FIFO empty" here
1067 * since its implicit in "FIFO half empty".
1068 */
1069 irqmask = MCI_TXFIFOHALFEMPTYMASK;
1070 }
1071
1072 mmci_write_datactrlreg(host, datactrl);
1073 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
1074 mmci_set_mask1(host, irqmask);
1075 }
1076
1077 static void
1078 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
1079 {
1080 void __iomem *base = host->base;
1081
1082 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
1083 cmd->opcode, cmd->arg, cmd->flags);
1084
1085 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) {
1086 writel(0, base + MMCICOMMAND);
1087 mmci_reg_delay(host);
1088 }
1089
1090 if (host->variant->cmdreg_stop &&
1091 cmd->opcode == MMC_STOP_TRANSMISSION)
1092 c |= host->variant->cmdreg_stop;
1093
1094 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable;
1095 if (cmd->flags & MMC_RSP_PRESENT) {
1096 if (cmd->flags & MMC_RSP_136)
1097 c |= host->variant->cmdreg_lrsp_crc;
1098 else if (cmd->flags & MMC_RSP_CRC)
1099 c |= host->variant->cmdreg_srsp_crc;
1100 else
1101 c |= host->variant->cmdreg_srsp;
1102 }
1103 if (/*interrupt*/0)
1104 c |= MCI_CPSM_INTERRUPT;
1105
1106 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
1107 c |= host->variant->data_cmd_enable;
1108
1109 host->cmd = cmd;
1110
1111 writel(cmd->arg, base + MMCIARGUMENT);
1112 writel(c, base + MMCICOMMAND);
1113 }
1114
1115 static void mmci_stop_command(struct mmci_host *host)
1116 {
1117 host->stop_abort.error = 0;
1118 mmci_start_command(host, &host->stop_abort, 0);
1119 }
1120
1121 static void
1122 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
1123 unsigned int status)
1124 {
1125 unsigned int status_err;
1126
1127 /* Make sure we have data to handle */
1128 if (!data)
1129 return;
1130
1131 /* First check for errors */
1132 status_err = status & (host->variant->start_err |
1133 MCI_DATACRCFAIL | MCI_DATATIMEOUT |
1134 MCI_TXUNDERRUN | MCI_RXOVERRUN);
1135
1136 if (status_err) {
1137 u32 remain, success;
1138
1139 /* Terminate the DMA transfer */
1140 mmci_dma_error(host);
1141
1142 /*
1143 * Calculate how far we are into the transfer. Note that
1144 * the data counter gives the number of bytes transferred
1145 * on the MMC bus, not on the host side. On reads, this
1146 * can be as much as a FIFO-worth of data ahead. This
1147 * matters for FIFO overruns only.
1148 */
1149 if (!host->variant->datacnt_useless) {
1150 remain = readl(host->base + MMCIDATACNT);
1151 success = data->blksz * data->blocks - remain;
1152 } else {
1153 success = 0;
1154 }
1155
1156 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
1157 status_err, success);
1158 if (status_err & MCI_DATACRCFAIL) {
1159 /* Last block was not successful */
1160 success -= 1;
1161 data->error = -EILSEQ;
1162 } else if (status_err & MCI_DATATIMEOUT) {
1163 data->error = -ETIMEDOUT;
1164 } else if (status_err & MCI_STARTBITERR) {
1165 data->error = -ECOMM;
1166 } else if (status_err & MCI_TXUNDERRUN) {
1167 data->error = -EIO;
1168 } else if (status_err & MCI_RXOVERRUN) {
1169 if (success > host->variant->fifosize)
1170 success -= host->variant->fifosize;
1171 else
1172 success = 0;
1173 data->error = -EIO;
1174 }
1175 data->bytes_xfered = round_down(success, data->blksz);
1176 }
1177
1178 if (status & MCI_DATABLOCKEND)
1179 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
1180
1181 if (status & MCI_DATAEND || data->error) {
1182 mmci_dma_finalize(host, data);
1183
1184 mmci_stop_data(host);
1185
1186 if (!data->error)
1187 /* The error clause is handled above, success! */
1188 data->bytes_xfered = data->blksz * data->blocks;
1189
1190 if (!data->stop) {
1191 if (host->variant->cmdreg_stop && data->error)
1192 mmci_stop_command(host);
1193 else
1194 mmci_request_end(host, data->mrq);
1195 } else if (host->mrq->sbc && !data->error) {
1196 mmci_request_end(host, data->mrq);
1197 } else {
1198 mmci_start_command(host, data->stop, 0);
1199 }
1200 }
1201 }
1202
1203 static void
1204 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
1205 unsigned int status)
1206 {
1207 void __iomem *base = host->base;
1208 bool sbc, busy_resp;
1209
1210 if (!cmd)
1211 return;
1212
1213 sbc = (cmd == host->mrq->sbc);
1214 busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
1215
1216 /*
1217 * We need to be one of these interrupts to be considered worth
1218 * handling. Note that we tag on any latent IRQs postponed
1219 * due to waiting for busy status.
1220 */
1221 if (!((status|host->busy_status) &
1222 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND)))
1223 return;
1224
1225 /*
1226 * ST Micro variant: handle busy detection.
1227 */
1228 if (busy_resp && host->variant->busy_detect) {
1229
1230 /* We are busy with a command, return */
1231 if (host->busy_status &&
1232 (status & host->variant->busy_detect_flag))
1233 return;
1234
1235 /*
1236 * We were not busy, but we now got a busy response on
1237 * something that was not an error, and we double-check
1238 * that the special busy status bit is still set before
1239 * proceeding.
1240 */
1241 if (!host->busy_status &&
1242 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1243 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
1244
1245 /* Clear the busy start IRQ */
1246 writel(host->variant->busy_detect_mask,
1247 host->base + MMCICLEAR);
1248
1249 /* Unmask the busy end IRQ */
1250 writel(readl(base + MMCIMASK0) |
1251 host->variant->busy_detect_mask,
1252 base + MMCIMASK0);
1253 /*
1254 * Now cache the last response status code (until
1255 * the busy bit goes low), and return.
1256 */
1257 host->busy_status =
1258 status & (MCI_CMDSENT|MCI_CMDRESPEND);
1259 return;
1260 }
1261
1262 /*
1263 * At this point we are not busy with a command, we have
1264 * not received a new busy request, clear and mask the busy
1265 * end IRQ and fall through to process the IRQ.
1266 */
1267 if (host->busy_status) {
1268
1269 writel(host->variant->busy_detect_mask,
1270 host->base + MMCICLEAR);
1271
1272 writel(readl(base + MMCIMASK0) &
1273 ~host->variant->busy_detect_mask,
1274 base + MMCIMASK0);
1275 host->busy_status = 0;
1276 }
1277 }
1278
1279 host->cmd = NULL;
1280
1281 if (status & MCI_CMDTIMEOUT) {
1282 cmd->error = -ETIMEDOUT;
1283 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
1284 cmd->error = -EILSEQ;
1285 } else {
1286 cmd->resp[0] = readl(base + MMCIRESPONSE0);
1287 cmd->resp[1] = readl(base + MMCIRESPONSE1);
1288 cmd->resp[2] = readl(base + MMCIRESPONSE2);
1289 cmd->resp[3] = readl(base + MMCIRESPONSE3);
1290 }
1291
1292 if ((!sbc && !cmd->data) || cmd->error) {
1293 if (host->data) {
1294 /* Terminate the DMA transfer */
1295 mmci_dma_error(host);
1296
1297 mmci_stop_data(host);
1298 if (host->variant->cmdreg_stop && cmd->error) {
1299 mmci_stop_command(host);
1300 return;
1301 }
1302 }
1303 mmci_request_end(host, host->mrq);
1304 } else if (sbc) {
1305 mmci_start_command(host, host->mrq->cmd, 0);
1306 } else if (!host->variant->datactrl_first &&
1307 !(cmd->data->flags & MMC_DATA_READ)) {
1308 mmci_start_data(host, cmd->data);
1309 }
1310 }
1311
1312 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1313 {
1314 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1315 }
1316
1317 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1318 {
1319 /*
1320 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1321 * from the fifo range should be used
1322 */
1323 if (status & MCI_RXFIFOHALFFULL)
1324 return host->variant->fifohalfsize;
1325 else if (status & MCI_RXDATAAVLBL)
1326 return 4;
1327
1328 return 0;
1329 }
1330
1331 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1332 {
1333 void __iomem *base = host->base;
1334 char *ptr = buffer;
1335 u32 status = readl(host->base + MMCISTATUS);
1336 int host_remain = host->size;
1337
1338 do {
1339 int count = host->get_rx_fifocnt(host, status, host_remain);
1340
1341 if (count > remain)
1342 count = remain;
1343
1344 if (count <= 0)
1345 break;
1346
1347 /*
1348 * SDIO especially may want to send something that is
1349 * not divisible by 4 (as opposed to card sectors
1350 * etc). Therefore make sure to always read the last bytes
1351 * while only doing full 32-bit reads towards the FIFO.
1352 */
1353 if (unlikely(count & 0x3)) {
1354 if (count < 4) {
1355 unsigned char buf[4];
1356 ioread32_rep(base + MMCIFIFO, buf, 1);
1357 memcpy(ptr, buf, count);
1358 } else {
1359 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1360 count &= ~0x3;
1361 }
1362 } else {
1363 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1364 }
1365
1366 ptr += count;
1367 remain -= count;
1368 host_remain -= count;
1369
1370 if (remain == 0)
1371 break;
1372
1373 status = readl(base + MMCISTATUS);
1374 } while (status & MCI_RXDATAAVLBL);
1375
1376 return ptr - buffer;
1377 }
1378
1379 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1380 {
1381 struct variant_data *variant = host->variant;
1382 void __iomem *base = host->base;
1383 char *ptr = buffer;
1384
1385 do {
1386 unsigned int count, maxcnt;
1387
1388 maxcnt = status & MCI_TXFIFOEMPTY ?
1389 variant->fifosize : variant->fifohalfsize;
1390 count = min(remain, maxcnt);
1391
1392 /*
1393 * SDIO especially may want to send something that is
1394 * not divisible by 4 (as opposed to card sectors
1395 * etc), and the FIFO only accept full 32-bit writes.
1396 * So compensate by adding +3 on the count, a single
1397 * byte become a 32bit write, 7 bytes will be two
1398 * 32bit writes etc.
1399 */
1400 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1401
1402 ptr += count;
1403 remain -= count;
1404
1405 if (remain == 0)
1406 break;
1407
1408 status = readl(base + MMCISTATUS);
1409 } while (status & MCI_TXFIFOHALFEMPTY);
1410
1411 return ptr - buffer;
1412 }
1413
1414 /*
1415 * PIO data transfer IRQ handler.
1416 */
1417 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1418 {
1419 struct mmci_host *host = dev_id;
1420 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1421 struct variant_data *variant = host->variant;
1422 void __iomem *base = host->base;
1423 u32 status;
1424
1425 status = readl(base + MMCISTATUS);
1426
1427 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1428
1429 do {
1430 unsigned int remain, len;
1431 char *buffer;
1432
1433 /*
1434 * For write, we only need to test the half-empty flag
1435 * here - if the FIFO is completely empty, then by
1436 * definition it is more than half empty.
1437 *
1438 * For read, check for data available.
1439 */
1440 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1441 break;
1442
1443 if (!sg_miter_next(sg_miter))
1444 break;
1445
1446 buffer = sg_miter->addr;
1447 remain = sg_miter->length;
1448
1449 len = 0;
1450 if (status & MCI_RXACTIVE)
1451 len = mmci_pio_read(host, buffer, remain);
1452 if (status & MCI_TXACTIVE)
1453 len = mmci_pio_write(host, buffer, remain, status);
1454
1455 sg_miter->consumed = len;
1456
1457 host->size -= len;
1458 remain -= len;
1459
1460 if (remain)
1461 break;
1462
1463 status = readl(base + MMCISTATUS);
1464 } while (1);
1465
1466 sg_miter_stop(sg_miter);
1467
1468 /*
1469 * If we have less than the fifo 'half-full' threshold to transfer,
1470 * trigger a PIO interrupt as soon as any data is available.
1471 */
1472 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1473 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1474
1475 /*
1476 * If we run out of data, disable the data IRQs; this
1477 * prevents a race where the FIFO becomes empty before
1478 * the chip itself has disabled the data path, and
1479 * stops us racing with our data end IRQ.
1480 */
1481 if (host->size == 0) {
1482 mmci_set_mask1(host, 0);
1483 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1484 }
1485
1486 return IRQ_HANDLED;
1487 }
1488
1489 /*
1490 * Handle completion of command and data transfers.
1491 */
1492 static irqreturn_t mmci_irq(int irq, void *dev_id)
1493 {
1494 struct mmci_host *host = dev_id;
1495 u32 status;
1496 int ret = 0;
1497
1498 spin_lock(&host->lock);
1499
1500 do {
1501 status = readl(host->base + MMCISTATUS);
1502
1503 if (host->singleirq) {
1504 if (status & host->mask1_reg)
1505 mmci_pio_irq(irq, dev_id);
1506
1507 status &= ~host->variant->irq_pio_mask;
1508 }
1509
1510 /*
1511 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's
1512 * enabled) in mmci_cmd_irq() function where ST Micro busy
1513 * detection variant is handled. Considering the HW seems to be
1514 * triggering the IRQ on both edges while monitoring DAT0 for
1515 * busy completion and that same status bit is used to monitor
1516 * start and end of busy detection, special care must be taken
1517 * to make sure that both start and end interrupts are always
1518 * cleared one after the other.
1519 */
1520 status &= readl(host->base + MMCIMASK0);
1521 if (host->variant->busy_detect)
1522 writel(status & ~host->variant->busy_detect_mask,
1523 host->base + MMCICLEAR);
1524 else
1525 writel(status, host->base + MMCICLEAR);
1526
1527 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1528
1529 if (host->variant->reversed_irq_handling) {
1530 mmci_data_irq(host, host->data, status);
1531 mmci_cmd_irq(host, host->cmd, status);
1532 } else {
1533 mmci_cmd_irq(host, host->cmd, status);
1534 mmci_data_irq(host, host->data, status);
1535 }
1536
1537 /*
1538 * Busy detection has been handled by mmci_cmd_irq() above.
1539 * Clear the status bit to prevent polling in IRQ context.
1540 */
1541 if (host->variant->busy_detect_flag)
1542 status &= ~host->variant->busy_detect_flag;
1543
1544 ret = 1;
1545 } while (status);
1546
1547 spin_unlock(&host->lock);
1548
1549 return IRQ_RETVAL(ret);
1550 }
1551
1552 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1553 {
1554 struct mmci_host *host = mmc_priv(mmc);
1555 unsigned long flags;
1556
1557 WARN_ON(host->mrq != NULL);
1558
1559 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1560 if (mrq->cmd->error) {
1561 mmc_request_done(mmc, mrq);
1562 return;
1563 }
1564
1565 spin_lock_irqsave(&host->lock, flags);
1566
1567 host->mrq = mrq;
1568
1569 if (mrq->data)
1570 mmci_get_next_data(host, mrq->data);
1571
1572 if (mrq->data &&
1573 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ))
1574 mmci_start_data(host, mrq->data);
1575
1576 if (mrq->sbc)
1577 mmci_start_command(host, mrq->sbc, 0);
1578 else
1579 mmci_start_command(host, mrq->cmd, 0);
1580
1581 spin_unlock_irqrestore(&host->lock, flags);
1582 }
1583
1584 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1585 {
1586 struct mmci_host *host = mmc_priv(mmc);
1587 struct variant_data *variant = host->variant;
1588 u32 pwr = 0;
1589 unsigned long flags;
1590 int ret;
1591
1592 if (host->plat->ios_handler &&
1593 host->plat->ios_handler(mmc_dev(mmc), ios))
1594 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1595
1596 switch (ios->power_mode) {
1597 case MMC_POWER_OFF:
1598 if (!IS_ERR(mmc->supply.vmmc))
1599 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1600
1601 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1602 regulator_disable(mmc->supply.vqmmc);
1603 host->vqmmc_enabled = false;
1604 }
1605
1606 break;
1607 case MMC_POWER_UP:
1608 if (!IS_ERR(mmc->supply.vmmc))
1609 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1610
1611 /*
1612 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1613 * and instead uses MCI_PWR_ON so apply whatever value is
1614 * configured in the variant data.
1615 */
1616 pwr |= variant->pwrreg_powerup;
1617
1618 break;
1619 case MMC_POWER_ON:
1620 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1621 ret = regulator_enable(mmc->supply.vqmmc);
1622 if (ret < 0)
1623 dev_err(mmc_dev(mmc),
1624 "failed to enable vqmmc regulator\n");
1625 else
1626 host->vqmmc_enabled = true;
1627 }
1628
1629 pwr |= MCI_PWR_ON;
1630 break;
1631 }
1632
1633 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1634 /*
1635 * The ST Micro variant has some additional bits
1636 * indicating signal direction for the signals in
1637 * the SD/MMC bus and feedback-clock usage.
1638 */
1639 pwr |= host->pwr_reg_add;
1640
1641 if (ios->bus_width == MMC_BUS_WIDTH_4)
1642 pwr &= ~MCI_ST_DATA74DIREN;
1643 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1644 pwr &= (~MCI_ST_DATA74DIREN &
1645 ~MCI_ST_DATA31DIREN &
1646 ~MCI_ST_DATA2DIREN);
1647 }
1648
1649 if (variant->opendrain) {
1650 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1651 pwr |= variant->opendrain;
1652 } else {
1653 /*
1654 * If the variant cannot configure the pads by its own, then we
1655 * expect the pinctrl to be able to do that for us
1656 */
1657 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1658 pinctrl_select_state(host->pinctrl, host->pins_opendrain);
1659 else
1660 pinctrl_select_state(host->pinctrl, host->pins_default);
1661 }
1662
1663 /*
1664 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1665 * gating the clock, the MCI_PWR_ON bit is cleared.
1666 */
1667 if (!ios->clock && variant->pwrreg_clkgate)
1668 pwr &= ~MCI_PWR_ON;
1669
1670 if (host->variant->explicit_mclk_control &&
1671 ios->clock != host->clock_cache) {
1672 ret = clk_set_rate(host->clk, ios->clock);
1673 if (ret < 0)
1674 dev_err(mmc_dev(host->mmc),
1675 "Error setting clock rate (%d)\n", ret);
1676 else
1677 host->mclk = clk_get_rate(host->clk);
1678 }
1679 host->clock_cache = ios->clock;
1680
1681 spin_lock_irqsave(&host->lock, flags);
1682
1683 if (host->ops && host->ops->set_clkreg)
1684 host->ops->set_clkreg(host, ios->clock);
1685 else
1686 mmci_set_clkreg(host, ios->clock);
1687
1688 if (host->ops && host->ops->set_pwrreg)
1689 host->ops->set_pwrreg(host, pwr);
1690 else
1691 mmci_write_pwrreg(host, pwr);
1692
1693 mmci_reg_delay(host);
1694
1695 spin_unlock_irqrestore(&host->lock, flags);
1696 }
1697
1698 static int mmci_get_cd(struct mmc_host *mmc)
1699 {
1700 struct mmci_host *host = mmc_priv(mmc);
1701 struct mmci_platform_data *plat = host->plat;
1702 unsigned int status = mmc_gpio_get_cd(mmc);
1703
1704 if (status == -ENOSYS) {
1705 if (!plat->status)
1706 return 1; /* Assume always present */
1707
1708 status = plat->status(mmc_dev(host->mmc));
1709 }
1710 return status;
1711 }
1712
1713 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1714 {
1715 int ret = 0;
1716
1717 if (!IS_ERR(mmc->supply.vqmmc)) {
1718
1719 switch (ios->signal_voltage) {
1720 case MMC_SIGNAL_VOLTAGE_330:
1721 ret = regulator_set_voltage(mmc->supply.vqmmc,
1722 2700000, 3600000);
1723 break;
1724 case MMC_SIGNAL_VOLTAGE_180:
1725 ret = regulator_set_voltage(mmc->supply.vqmmc,
1726 1700000, 1950000);
1727 break;
1728 case MMC_SIGNAL_VOLTAGE_120:
1729 ret = regulator_set_voltage(mmc->supply.vqmmc,
1730 1100000, 1300000);
1731 break;
1732 }
1733
1734 if (ret)
1735 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1736 }
1737
1738 return ret;
1739 }
1740
1741 static struct mmc_host_ops mmci_ops = {
1742 .request = mmci_request,
1743 .pre_req = mmci_pre_request,
1744 .post_req = mmci_post_request,
1745 .set_ios = mmci_set_ios,
1746 .get_ro = mmc_gpio_get_ro,
1747 .get_cd = mmci_get_cd,
1748 .start_signal_voltage_switch = mmci_sig_volt_switch,
1749 };
1750
1751 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1752 {
1753 struct mmci_host *host = mmc_priv(mmc);
1754 int ret = mmc_of_parse(mmc);
1755
1756 if (ret)
1757 return ret;
1758
1759 if (of_get_property(np, "st,sig-dir-dat0", NULL))
1760 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1761 if (of_get_property(np, "st,sig-dir-dat2", NULL))
1762 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1763 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1764 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1765 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1766 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1767 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1768 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1769 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1770 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1771 if (of_get_property(np, "st,sig-dir", NULL))
1772 host->pwr_reg_add |= MCI_STM32_DIRPOL;
1773 if (of_get_property(np, "st,neg-edge", NULL))
1774 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE;
1775 if (of_get_property(np, "st,use-ckin", NULL))
1776 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
1777
1778 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1779 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1780 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1781 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1782
1783 return 0;
1784 }
1785
1786 static int mmci_probe(struct amba_device *dev,
1787 const struct amba_id *id)
1788 {
1789 struct mmci_platform_data *plat = dev->dev.platform_data;
1790 struct device_node *np = dev->dev.of_node;
1791 struct variant_data *variant = id->data;
1792 struct mmci_host *host;
1793 struct mmc_host *mmc;
1794 int ret;
1795
1796 /* Must have platform data or Device Tree. */
1797 if (!plat && !np) {
1798 dev_err(&dev->dev, "No plat data or DT found\n");
1799 return -EINVAL;
1800 }
1801
1802 if (!plat) {
1803 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1804 if (!plat)
1805 return -ENOMEM;
1806 }
1807
1808 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1809 if (!mmc)
1810 return -ENOMEM;
1811
1812 ret = mmci_of_parse(np, mmc);
1813 if (ret)
1814 goto host_free;
1815
1816 host = mmc_priv(mmc);
1817 host->mmc = mmc;
1818
1819 /*
1820 * Some variant (STM32) doesn't have opendrain bit, nevertheless
1821 * pins can be set accordingly using pinctrl
1822 */
1823 if (!variant->opendrain) {
1824 host->pinctrl = devm_pinctrl_get(&dev->dev);
1825 if (IS_ERR(host->pinctrl)) {
1826 dev_err(&dev->dev, "failed to get pinctrl");
1827 ret = PTR_ERR(host->pinctrl);
1828 goto host_free;
1829 }
1830
1831 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1832 PINCTRL_STATE_DEFAULT);
1833 if (IS_ERR(host->pins_default)) {
1834 dev_err(mmc_dev(mmc), "Can't select default pins\n");
1835 ret = PTR_ERR(host->pins_default);
1836 goto host_free;
1837 }
1838
1839 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
1840 MMCI_PINCTRL_STATE_OPENDRAIN);
1841 if (IS_ERR(host->pins_opendrain)) {
1842 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n");
1843 ret = PTR_ERR(host->pins_opendrain);
1844 goto host_free;
1845 }
1846 }
1847
1848 host->hw_designer = amba_manf(dev);
1849 host->hw_revision = amba_rev(dev);
1850 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1851 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1852
1853 host->clk = devm_clk_get(&dev->dev, NULL);
1854 if (IS_ERR(host->clk)) {
1855 ret = PTR_ERR(host->clk);
1856 goto host_free;
1857 }
1858
1859 ret = clk_prepare_enable(host->clk);
1860 if (ret)
1861 goto host_free;
1862
1863 if (variant->qcom_fifo)
1864 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1865 else
1866 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1867
1868 host->plat = plat;
1869 host->variant = variant;
1870 host->mclk = clk_get_rate(host->clk);
1871 /*
1872 * According to the spec, mclk is max 100 MHz,
1873 * so we try to adjust the clock down to this,
1874 * (if possible).
1875 */
1876 if (host->mclk > variant->f_max) {
1877 ret = clk_set_rate(host->clk, variant->f_max);
1878 if (ret < 0)
1879 goto clk_disable;
1880 host->mclk = clk_get_rate(host->clk);
1881 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1882 host->mclk);
1883 }
1884
1885 host->phybase = dev->res.start;
1886 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1887 if (IS_ERR(host->base)) {
1888 ret = PTR_ERR(host->base);
1889 goto clk_disable;
1890 }
1891
1892 if (variant->init)
1893 variant->init(host);
1894
1895 /*
1896 * The ARM and ST versions of the block have slightly different
1897 * clock divider equations which means that the minimum divider
1898 * differs too.
1899 * on Qualcomm like controllers get the nearest minimum clock to 100Khz
1900 */
1901 if (variant->st_clkdiv)
1902 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1903 else if (variant->stm32_clkdiv)
1904 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046);
1905 else if (variant->explicit_mclk_control)
1906 mmc->f_min = clk_round_rate(host->clk, 100000);
1907 else
1908 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1909 /*
1910 * If no maximum operating frequency is supplied, fall back to use
1911 * the module parameter, which has a (low) default value in case it
1912 * is not specified. Either value must not exceed the clock rate into
1913 * the block, of course.
1914 */
1915 if (mmc->f_max)
1916 mmc->f_max = variant->explicit_mclk_control ?
1917 min(variant->f_max, mmc->f_max) :
1918 min(host->mclk, mmc->f_max);
1919 else
1920 mmc->f_max = variant->explicit_mclk_control ?
1921 fmax : min(host->mclk, fmax);
1922
1923
1924 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1925
1926 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
1927 if (IS_ERR(host->rst)) {
1928 ret = PTR_ERR(host->rst);
1929 goto clk_disable;
1930 }
1931
1932 /* Get regulators and the supported OCR mask */
1933 ret = mmc_regulator_get_supply(mmc);
1934 if (ret)
1935 goto clk_disable;
1936
1937 if (!mmc->ocr_avail)
1938 mmc->ocr_avail = plat->ocr_mask;
1939 else if (plat->ocr_mask)
1940 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1941
1942 /* We support these capabilities. */
1943 mmc->caps |= MMC_CAP_CMD23;
1944
1945 /*
1946 * Enable busy detection.
1947 */
1948 if (variant->busy_detect) {
1949 mmci_ops.card_busy = mmci_card_busy;
1950 /*
1951 * Not all variants have a flag to enable busy detection
1952 * in the DPSM, but if they do, set it here.
1953 */
1954 if (variant->busy_dpsm_flag)
1955 mmci_write_datactrlreg(host,
1956 host->variant->busy_dpsm_flag);
1957 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1958 mmc->max_busy_timeout = 0;
1959 }
1960
1961 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */
1962 host->stop_abort.opcode = MMC_STOP_TRANSMISSION;
1963 host->stop_abort.arg = 0;
1964 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC;
1965
1966 mmc->ops = &mmci_ops;
1967
1968 /* We support these PM capabilities. */
1969 mmc->pm_caps |= MMC_PM_KEEP_POWER;
1970
1971 /*
1972 * We can do SGIO
1973 */
1974 mmc->max_segs = NR_SG;
1975
1976 /*
1977 * Since only a certain number of bits are valid in the data length
1978 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1979 * single request.
1980 */
1981 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1982
1983 /*
1984 * Set the maximum segment size. Since we aren't doing DMA
1985 * (yet) we are only limited by the data length register.
1986 */
1987 mmc->max_seg_size = mmc->max_req_size;
1988
1989 /*
1990 * Block size can be up to 2048 bytes, but must be a power of two.
1991 */
1992 mmc->max_blk_size = 1 << variant->datactrl_blocksz;
1993
1994 /*
1995 * Limit the number of blocks transferred so that we don't overflow
1996 * the maximum request size.
1997 */
1998 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz;
1999
2000 spin_lock_init(&host->lock);
2001
2002 writel(0, host->base + MMCIMASK0);
2003
2004 if (variant->mmcimask1)
2005 writel(0, host->base + MMCIMASK1);
2006
2007 writel(0xfff, host->base + MMCICLEAR);
2008
2009 /*
2010 * If:
2011 * - not using DT but using a descriptor table, or
2012 * - using a table of descriptors ALONGSIDE DT, or
2013 * look up these descriptors named "cd" and "wp" right here, fail
2014 * silently of these do not exist
2015 */
2016 if (!np) {
2017 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
2018 if (ret == -EPROBE_DEFER)
2019 goto clk_disable;
2020
2021 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0, NULL);
2022 if (ret == -EPROBE_DEFER)
2023 goto clk_disable;
2024 }
2025
2026 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
2027 DRIVER_NAME " (cmd)", host);
2028 if (ret)
2029 goto clk_disable;
2030
2031 if (!dev->irq[1])
2032 host->singleirq = true;
2033 else {
2034 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
2035 IRQF_SHARED, DRIVER_NAME " (pio)", host);
2036 if (ret)
2037 goto clk_disable;
2038 }
2039
2040 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
2041
2042 amba_set_drvdata(dev, mmc);
2043
2044 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
2045 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
2046 amba_rev(dev), (unsigned long long)dev->res.start,
2047 dev->irq[0], dev->irq[1]);
2048
2049 mmci_dma_setup(host);
2050
2051 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
2052 pm_runtime_use_autosuspend(&dev->dev);
2053
2054 mmc_add_host(mmc);
2055
2056 pm_runtime_put(&dev->dev);
2057 return 0;
2058
2059 clk_disable:
2060 clk_disable_unprepare(host->clk);
2061 host_free:
2062 mmc_free_host(mmc);
2063 return ret;
2064 }
2065
2066 static int mmci_remove(struct amba_device *dev)
2067 {
2068 struct mmc_host *mmc = amba_get_drvdata(dev);
2069
2070 if (mmc) {
2071 struct mmci_host *host = mmc_priv(mmc);
2072 struct variant_data *variant = host->variant;
2073
2074 /*
2075 * Undo pm_runtime_put() in probe. We use the _sync
2076 * version here so that we can access the primecell.
2077 */
2078 pm_runtime_get_sync(&dev->dev);
2079
2080 mmc_remove_host(mmc);
2081
2082 writel(0, host->base + MMCIMASK0);
2083
2084 if (variant->mmcimask1)
2085 writel(0, host->base + MMCIMASK1);
2086
2087 writel(0, host->base + MMCICOMMAND);
2088 writel(0, host->base + MMCIDATACTRL);
2089
2090 mmci_dma_release(host);
2091 clk_disable_unprepare(host->clk);
2092 mmc_free_host(mmc);
2093 }
2094
2095 return 0;
2096 }
2097
2098 #ifdef CONFIG_PM
2099 static void mmci_save(struct mmci_host *host)
2100 {
2101 unsigned long flags;
2102
2103 spin_lock_irqsave(&host->lock, flags);
2104
2105 writel(0, host->base + MMCIMASK0);
2106 if (host->variant->pwrreg_nopower) {
2107 writel(0, host->base + MMCIDATACTRL);
2108 writel(0, host->base + MMCIPOWER);
2109 writel(0, host->base + MMCICLOCK);
2110 }
2111 mmci_reg_delay(host);
2112
2113 spin_unlock_irqrestore(&host->lock, flags);
2114 }
2115
2116 static void mmci_restore(struct mmci_host *host)
2117 {
2118 unsigned long flags;
2119
2120 spin_lock_irqsave(&host->lock, flags);
2121
2122 if (host->variant->pwrreg_nopower) {
2123 writel(host->clk_reg, host->base + MMCICLOCK);
2124 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
2125 writel(host->pwr_reg, host->base + MMCIPOWER);
2126 }
2127 writel(MCI_IRQENABLE | host->variant->start_err,
2128 host->base + MMCIMASK0);
2129 mmci_reg_delay(host);
2130
2131 spin_unlock_irqrestore(&host->lock, flags);
2132 }
2133
2134 static int mmci_runtime_suspend(struct device *dev)
2135 {
2136 struct amba_device *adev = to_amba_device(dev);
2137 struct mmc_host *mmc = amba_get_drvdata(adev);
2138
2139 if (mmc) {
2140 struct mmci_host *host = mmc_priv(mmc);
2141 pinctrl_pm_select_sleep_state(dev);
2142 mmci_save(host);
2143 clk_disable_unprepare(host->clk);
2144 }
2145
2146 return 0;
2147 }
2148
2149 static int mmci_runtime_resume(struct device *dev)
2150 {
2151 struct amba_device *adev = to_amba_device(dev);
2152 struct mmc_host *mmc = amba_get_drvdata(adev);
2153
2154 if (mmc) {
2155 struct mmci_host *host = mmc_priv(mmc);
2156 clk_prepare_enable(host->clk);
2157 mmci_restore(host);
2158 pinctrl_pm_select_default_state(dev);
2159 }
2160
2161 return 0;
2162 }
2163 #endif
2164
2165 static const struct dev_pm_ops mmci_dev_pm_ops = {
2166 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2167 pm_runtime_force_resume)
2168 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
2169 };
2170
2171 static const struct amba_id mmci_ids[] = {
2172 {
2173 .id = 0x00041180,
2174 .mask = 0xff0fffff,
2175 .data = &variant_arm,
2176 },
2177 {
2178 .id = 0x01041180,
2179 .mask = 0xff0fffff,
2180 .data = &variant_arm_extended_fifo,
2181 },
2182 {
2183 .id = 0x02041180,
2184 .mask = 0xff0fffff,
2185 .data = &variant_arm_extended_fifo_hwfc,
2186 },
2187 {
2188 .id = 0x00041181,
2189 .mask = 0x000fffff,
2190 .data = &variant_arm,
2191 },
2192 /* ST Micro variants */
2193 {
2194 .id = 0x00180180,
2195 .mask = 0x00ffffff,
2196 .data = &variant_u300,
2197 },
2198 {
2199 .id = 0x10180180,
2200 .mask = 0xf0ffffff,
2201 .data = &variant_nomadik,
2202 },
2203 {
2204 .id = 0x00280180,
2205 .mask = 0x00ffffff,
2206 .data = &variant_nomadik,
2207 },
2208 {
2209 .id = 0x00480180,
2210 .mask = 0xf0ffffff,
2211 .data = &variant_ux500,
2212 },
2213 {
2214 .id = 0x10480180,
2215 .mask = 0xf0ffffff,
2216 .data = &variant_ux500v2,
2217 },
2218 {
2219 .id = 0x00880180,
2220 .mask = 0x00ffffff,
2221 .data = &variant_stm32,
2222 },
2223 {
2224 .id = 0x10153180,
2225 .mask = 0xf0ffffff,
2226 .data = &variant_stm32_sdmmc,
2227 },
2228 /* Qualcomm variants */
2229 {
2230 .id = 0x00051180,
2231 .mask = 0x000fffff,
2232 .data = &variant_qcom,
2233 },
2234 { 0, 0 },
2235 };
2236
2237 MODULE_DEVICE_TABLE(amba, mmci_ids);
2238
2239 static struct amba_driver mmci_driver = {
2240 .drv = {
2241 .name = DRIVER_NAME,
2242 .pm = &mmci_dev_pm_ops,
2243 },
2244 .probe = mmci_probe,
2245 .remove = mmci_remove,
2246 .id_table = mmci_ids,
2247 };
2248
2249 module_amba_driver(mmci_driver);
2250
2251 module_param(fmax, uint, 0444);
2252
2253 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
2254 MODULE_LICENSE("GPL");
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git