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ARM: dts: lan966x: Fix the interrupt number for internal PHYs
[people/ms/linux.git] / drivers / mmc / host / mtk-sd.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 */
6
7 #include <linux/module.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/iopoll.h>
13 #include <linux/ioport.h>
14 #include <linux/irq.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_gpio.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/pm_wakeirq.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/interrupt.h>
28 #include <linux/reset.h>
29
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/core.h>
32 #include <linux/mmc/host.h>
33 #include <linux/mmc/mmc.h>
34 #include <linux/mmc/sd.h>
35 #include <linux/mmc/sdio.h>
36 #include <linux/mmc/slot-gpio.h>
37
38 #include "cqhci.h"
39
40 #define MAX_BD_NUM 1024
41 #define MSDC_NR_CLOCKS 3
42
43 /*--------------------------------------------------------------------------*/
44 /* Common Definition */
45 /*--------------------------------------------------------------------------*/
46 #define MSDC_BUS_1BITS 0x0
47 #define MSDC_BUS_4BITS 0x1
48 #define MSDC_BUS_8BITS 0x2
49
50 #define MSDC_BURST_64B 0x6
51
52 /*--------------------------------------------------------------------------*/
53 /* Register Offset */
54 /*--------------------------------------------------------------------------*/
55 #define MSDC_CFG 0x0
56 #define MSDC_IOCON 0x04
57 #define MSDC_PS 0x08
58 #define MSDC_INT 0x0c
59 #define MSDC_INTEN 0x10
60 #define MSDC_FIFOCS 0x14
61 #define SDC_CFG 0x30
62 #define SDC_CMD 0x34
63 #define SDC_ARG 0x38
64 #define SDC_STS 0x3c
65 #define SDC_RESP0 0x40
66 #define SDC_RESP1 0x44
67 #define SDC_RESP2 0x48
68 #define SDC_RESP3 0x4c
69 #define SDC_BLK_NUM 0x50
70 #define SDC_ADV_CFG0 0x64
71 #define EMMC_IOCON 0x7c
72 #define SDC_ACMD_RESP 0x80
73 #define DMA_SA_H4BIT 0x8c
74 #define MSDC_DMA_SA 0x90
75 #define MSDC_DMA_CTRL 0x98
76 #define MSDC_DMA_CFG 0x9c
77 #define MSDC_PATCH_BIT 0xb0
78 #define MSDC_PATCH_BIT1 0xb4
79 #define MSDC_PATCH_BIT2 0xb8
80 #define MSDC_PAD_TUNE 0xec
81 #define MSDC_PAD_TUNE0 0xf0
82 #define PAD_DS_TUNE 0x188
83 #define PAD_CMD_TUNE 0x18c
84 #define EMMC51_CFG0 0x204
85 #define EMMC50_CFG0 0x208
86 #define EMMC50_CFG1 0x20c
87 #define EMMC50_CFG3 0x220
88 #define SDC_FIFO_CFG 0x228
89 #define CQHCI_SETTING 0x7fc
90
91 /*--------------------------------------------------------------------------*/
92 /* Top Pad Register Offset */
93 /*--------------------------------------------------------------------------*/
94 #define EMMC_TOP_CONTROL 0x00
95 #define EMMC_TOP_CMD 0x04
96 #define EMMC50_PAD_DS_TUNE 0x0c
97
98 /*--------------------------------------------------------------------------*/
99 /* Register Mask */
100 /*--------------------------------------------------------------------------*/
101
102 /* MSDC_CFG mask */
103 #define MSDC_CFG_MODE BIT(0) /* RW */
104 #define MSDC_CFG_CKPDN BIT(1) /* RW */
105 #define MSDC_CFG_RST BIT(2) /* RW */
106 #define MSDC_CFG_PIO BIT(3) /* RW */
107 #define MSDC_CFG_CKDRVEN BIT(4) /* RW */
108 #define MSDC_CFG_BV18SDT BIT(5) /* RW */
109 #define MSDC_CFG_BV18PSS BIT(6) /* R */
110 #define MSDC_CFG_CKSTB BIT(7) /* R */
111 #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */
112 #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */
113 #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */
114 #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */
115 #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */
116 #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */
117
118 /* MSDC_IOCON mask */
119 #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */
120 #define MSDC_IOCON_RSPL BIT(1) /* RW */
121 #define MSDC_IOCON_DSPL BIT(2) /* RW */
122 #define MSDC_IOCON_DDLSEL BIT(3) /* RW */
123 #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */
124 #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */
125 #define MSDC_IOCON_W_DSPL BIT(8) /* RW */
126 #define MSDC_IOCON_D0SPL BIT(16) /* RW */
127 #define MSDC_IOCON_D1SPL BIT(17) /* RW */
128 #define MSDC_IOCON_D2SPL BIT(18) /* RW */
129 #define MSDC_IOCON_D3SPL BIT(19) /* RW */
130 #define MSDC_IOCON_D4SPL BIT(20) /* RW */
131 #define MSDC_IOCON_D5SPL BIT(21) /* RW */
132 #define MSDC_IOCON_D6SPL BIT(22) /* RW */
133 #define MSDC_IOCON_D7SPL BIT(23) /* RW */
134 #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */
135
136 /* MSDC_PS mask */
137 #define MSDC_PS_CDEN BIT(0) /* RW */
138 #define MSDC_PS_CDSTS BIT(1) /* R */
139 #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */
140 #define MSDC_PS_DAT GENMASK(23, 16) /* R */
141 #define MSDC_PS_DATA1 BIT(17) /* R */
142 #define MSDC_PS_CMD BIT(24) /* R */
143 #define MSDC_PS_WP BIT(31) /* R */
144
145 /* MSDC_INT mask */
146 #define MSDC_INT_MMCIRQ BIT(0) /* W1C */
147 #define MSDC_INT_CDSC BIT(1) /* W1C */
148 #define MSDC_INT_ACMDRDY BIT(3) /* W1C */
149 #define MSDC_INT_ACMDTMO BIT(4) /* W1C */
150 #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */
151 #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */
152 #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */
153 #define MSDC_INT_CMDRDY BIT(8) /* W1C */
154 #define MSDC_INT_CMDTMO BIT(9) /* W1C */
155 #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */
156 #define MSDC_INT_CSTA BIT(11) /* R */
157 #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */
158 #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */
159 #define MSDC_INT_DATTMO BIT(14) /* W1C */
160 #define MSDC_INT_DATCRCERR BIT(15) /* W1C */
161 #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */
162 #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */
163 #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */
164 #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */
165 #define MSDC_INT_CMDQ BIT(28) /* W1C */
166
167 /* MSDC_INTEN mask */
168 #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */
169 #define MSDC_INTEN_CDSC BIT(1) /* RW */
170 #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */
171 #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */
172 #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */
173 #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */
174 #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */
175 #define MSDC_INTEN_CMDRDY BIT(8) /* RW */
176 #define MSDC_INTEN_CMDTMO BIT(9) /* RW */
177 #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */
178 #define MSDC_INTEN_CSTA BIT(11) /* RW */
179 #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */
180 #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */
181 #define MSDC_INTEN_DATTMO BIT(14) /* RW */
182 #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */
183 #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */
184 #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */
185 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */
186 #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */
187
188 /* MSDC_FIFOCS mask */
189 #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */
190 #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */
191 #define MSDC_FIFOCS_CLR BIT(31) /* RW */
192
193 /* SDC_CFG mask */
194 #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */
195 #define SDC_CFG_INSWKUP BIT(1) /* RW */
196 #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */
197 #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */
198 #define SDC_CFG_SDIO BIT(19) /* RW */
199 #define SDC_CFG_SDIOIDE BIT(20) /* RW */
200 #define SDC_CFG_INTATGAP BIT(21) /* RW */
201 #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */
202
203 /* SDC_STS mask */
204 #define SDC_STS_SDCBUSY BIT(0) /* RW */
205 #define SDC_STS_CMDBUSY BIT(1) /* RW */
206 #define SDC_STS_SWR_COMPL BIT(31) /* RW */
207
208 #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */
209 /* SDC_ADV_CFG0 mask */
210 #define SDC_RX_ENHANCE_EN BIT(20) /* RW */
211
212 /* DMA_SA_H4BIT mask */
213 #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */
214
215 /* MSDC_DMA_CTRL mask */
216 #define MSDC_DMA_CTRL_START BIT(0) /* W */
217 #define MSDC_DMA_CTRL_STOP BIT(1) /* W */
218 #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */
219 #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */
220 #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */
221 #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */
222
223 /* MSDC_DMA_CFG mask */
224 #define MSDC_DMA_CFG_STS BIT(0) /* R */
225 #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */
226 #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */
227 #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */
228 #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */
229
230 /* MSDC_PATCH_BIT mask */
231 #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */
232 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
233 #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10)
234 #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */
235 #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */
236 #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */
237 #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */
238 #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */
239 #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */
240 #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */
241 #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */
242 #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */
243
244 #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */
245 #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */
246 #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */
247
248 #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */
249 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */
250 #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */
251 #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */
252 #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */
253 #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */
254
255 #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */
256 #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */
257 #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */
258 #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */
259 #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */
260 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */
261 #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */
262 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */
263
264 #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */
265 #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */
266 #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */
267 #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */
268
269 #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */
270
271 /* EMMC51_CFG0 mask */
272 #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */
273
274 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */
275 #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */
276 #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */
277 #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */
278
279 /* EMMC50_CFG1 mask */
280 #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */
281
282 #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */
283
284 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */
285 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */
286
287 /* CQHCI_SETTING */
288 #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */
289 #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */
290
291 /* EMMC_TOP_CONTROL mask */
292 #define PAD_RXDLY_SEL BIT(0) /* RW */
293 #define DELAY_EN BIT(1) /* RW */
294 #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */
295 #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */
296 #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */
297 #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */
298 #define DATA_K_VALUE_SEL BIT(14) /* RW */
299 #define SDC_RX_ENH_EN BIT(15) /* TW */
300
301 /* EMMC_TOP_CMD mask */
302 #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */
303 #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */
304 #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */
305 #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */
306 #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */
307
308 /* EMMC50_PAD_DS_TUNE mask */
309 #define PAD_DS_DLY_SEL BIT(16) /* RW */
310 #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */
311 #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */
312
313 #define REQ_CMD_EIO BIT(0)
314 #define REQ_CMD_TMO BIT(1)
315 #define REQ_DAT_ERR BIT(2)
316 #define REQ_STOP_EIO BIT(3)
317 #define REQ_STOP_TMO BIT(4)
318 #define REQ_CMD_BUSY BIT(5)
319
320 #define MSDC_PREPARE_FLAG BIT(0)
321 #define MSDC_ASYNC_FLAG BIT(1)
322 #define MSDC_MMAP_FLAG BIT(2)
323
324 #define MTK_MMC_AUTOSUSPEND_DELAY 50
325 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
326 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
327
328 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */
329
330 #define PAD_DELAY_MAX 32 /* PAD delay cells */
331 /*--------------------------------------------------------------------------*/
332 /* Descriptor Structure */
333 /*--------------------------------------------------------------------------*/
334 struct mt_gpdma_desc {
335 u32 gpd_info;
336 #define GPDMA_DESC_HWO BIT(0)
337 #define GPDMA_DESC_BDP BIT(1)
338 #define GPDMA_DESC_CHECKSUM GENMASK(15, 8)
339 #define GPDMA_DESC_INT BIT(16)
340 #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24)
341 #define GPDMA_DESC_PTR_H4 GENMASK(31, 28)
342 u32 next;
343 u32 ptr;
344 u32 gpd_data_len;
345 #define GPDMA_DESC_BUFLEN GENMASK(15, 0)
346 #define GPDMA_DESC_EXTLEN GENMASK(23, 16)
347 u32 arg;
348 u32 blknum;
349 u32 cmd;
350 };
351
352 struct mt_bdma_desc {
353 u32 bd_info;
354 #define BDMA_DESC_EOL BIT(0)
355 #define BDMA_DESC_CHECKSUM GENMASK(15, 8)
356 #define BDMA_DESC_BLKPAD BIT(17)
357 #define BDMA_DESC_DWPAD BIT(18)
358 #define BDMA_DESC_NEXT_H4 GENMASK(27, 24)
359 #define BDMA_DESC_PTR_H4 GENMASK(31, 28)
360 u32 next;
361 u32 ptr;
362 u32 bd_data_len;
363 #define BDMA_DESC_BUFLEN GENMASK(15, 0)
364 #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0)
365 };
366
367 struct msdc_dma {
368 struct scatterlist *sg; /* I/O scatter list */
369 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
370 struct mt_bdma_desc *bd; /* pointer to bd array */
371 dma_addr_t gpd_addr; /* the physical address of gpd array */
372 dma_addr_t bd_addr; /* the physical address of bd array */
373 };
374
375 struct msdc_save_para {
376 u32 msdc_cfg;
377 u32 iocon;
378 u32 sdc_cfg;
379 u32 pad_tune;
380 u32 patch_bit0;
381 u32 patch_bit1;
382 u32 patch_bit2;
383 u32 pad_ds_tune;
384 u32 pad_cmd_tune;
385 u32 emmc50_cfg0;
386 u32 emmc50_cfg3;
387 u32 sdc_fifo_cfg;
388 u32 emmc_top_control;
389 u32 emmc_top_cmd;
390 u32 emmc50_pad_ds_tune;
391 };
392
393 struct mtk_mmc_compatible {
394 u8 clk_div_bits;
395 bool recheck_sdio_irq;
396 bool hs400_tune; /* only used for MT8173 */
397 u32 pad_tune_reg;
398 bool async_fifo;
399 bool data_tune;
400 bool busy_check;
401 bool stop_clk_fix;
402 bool enhance_rx;
403 bool support_64g;
404 bool use_internal_cd;
405 };
406
407 struct msdc_tune_para {
408 u32 iocon;
409 u32 pad_tune;
410 u32 pad_cmd_tune;
411 u32 emmc_top_control;
412 u32 emmc_top_cmd;
413 };
414
415 struct msdc_delay_phase {
416 u8 maxlen;
417 u8 start;
418 u8 final_phase;
419 };
420
421 struct msdc_host {
422 struct device *dev;
423 const struct mtk_mmc_compatible *dev_comp;
424 int cmd_rsp;
425
426 spinlock_t lock;
427 struct mmc_request *mrq;
428 struct mmc_command *cmd;
429 struct mmc_data *data;
430 int error;
431
432 void __iomem *base; /* host base address */
433 void __iomem *top_base; /* host top register base address */
434
435 struct msdc_dma dma; /* dma channel */
436 u64 dma_mask;
437
438 u32 timeout_ns; /* data timeout ns */
439 u32 timeout_clks; /* data timeout clks */
440
441 struct pinctrl *pinctrl;
442 struct pinctrl_state *pins_default;
443 struct pinctrl_state *pins_uhs;
444 struct pinctrl_state *pins_eint;
445 struct delayed_work req_timeout;
446 int irq; /* host interrupt */
447 int eint_irq; /* interrupt from sdio device for waking up system */
448 struct reset_control *reset;
449
450 struct clk *src_clk; /* msdc source clock */
451 struct clk *h_clk; /* msdc h_clk */
452 struct clk *bus_clk; /* bus clock which used to access register */
453 struct clk *src_clk_cg; /* msdc source clock control gate */
454 struct clk *sys_clk_cg; /* msdc subsys clock control gate */
455 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
456 u32 mclk; /* mmc subsystem clock frequency */
457 u32 src_clk_freq; /* source clock frequency */
458 unsigned char timing;
459 bool vqmmc_enabled;
460 u32 latch_ck;
461 u32 hs400_ds_delay;
462 u32 hs400_ds_dly3;
463 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
464 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
465 bool hs400_cmd_resp_sel_rising;
466 /* cmd response sample selection for HS400 */
467 bool hs400_mode; /* current eMMC will run at hs400 mode */
468 bool hs400_tuning; /* hs400 mode online tuning */
469 bool internal_cd; /* Use internal card-detect logic */
470 bool cqhci; /* support eMMC hw cmdq */
471 struct msdc_save_para save_para; /* used when gate HCLK */
472 struct msdc_tune_para def_tune_para; /* default tune setting */
473 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
474 struct cqhci_host *cq_host;
475 };
476
477 static const struct mtk_mmc_compatible mt8135_compat = {
478 .clk_div_bits = 8,
479 .recheck_sdio_irq = true,
480 .hs400_tune = false,
481 .pad_tune_reg = MSDC_PAD_TUNE,
482 .async_fifo = false,
483 .data_tune = false,
484 .busy_check = false,
485 .stop_clk_fix = false,
486 .enhance_rx = false,
487 .support_64g = false,
488 };
489
490 static const struct mtk_mmc_compatible mt8173_compat = {
491 .clk_div_bits = 8,
492 .recheck_sdio_irq = true,
493 .hs400_tune = true,
494 .pad_tune_reg = MSDC_PAD_TUNE,
495 .async_fifo = false,
496 .data_tune = false,
497 .busy_check = false,
498 .stop_clk_fix = false,
499 .enhance_rx = false,
500 .support_64g = false,
501 };
502
503 static const struct mtk_mmc_compatible mt8183_compat = {
504 .clk_div_bits = 12,
505 .recheck_sdio_irq = false,
506 .hs400_tune = false,
507 .pad_tune_reg = MSDC_PAD_TUNE0,
508 .async_fifo = true,
509 .data_tune = true,
510 .busy_check = true,
511 .stop_clk_fix = true,
512 .enhance_rx = true,
513 .support_64g = true,
514 };
515
516 static const struct mtk_mmc_compatible mt2701_compat = {
517 .clk_div_bits = 12,
518 .recheck_sdio_irq = true,
519 .hs400_tune = false,
520 .pad_tune_reg = MSDC_PAD_TUNE0,
521 .async_fifo = true,
522 .data_tune = true,
523 .busy_check = false,
524 .stop_clk_fix = false,
525 .enhance_rx = false,
526 .support_64g = false,
527 };
528
529 static const struct mtk_mmc_compatible mt2712_compat = {
530 .clk_div_bits = 12,
531 .recheck_sdio_irq = false,
532 .hs400_tune = false,
533 .pad_tune_reg = MSDC_PAD_TUNE0,
534 .async_fifo = true,
535 .data_tune = true,
536 .busy_check = true,
537 .stop_clk_fix = true,
538 .enhance_rx = true,
539 .support_64g = true,
540 };
541
542 static const struct mtk_mmc_compatible mt7622_compat = {
543 .clk_div_bits = 12,
544 .recheck_sdio_irq = true,
545 .hs400_tune = false,
546 .pad_tune_reg = MSDC_PAD_TUNE0,
547 .async_fifo = true,
548 .data_tune = true,
549 .busy_check = true,
550 .stop_clk_fix = true,
551 .enhance_rx = true,
552 .support_64g = false,
553 };
554
555 static const struct mtk_mmc_compatible mt8516_compat = {
556 .clk_div_bits = 12,
557 .recheck_sdio_irq = true,
558 .hs400_tune = false,
559 .pad_tune_reg = MSDC_PAD_TUNE0,
560 .async_fifo = true,
561 .data_tune = true,
562 .busy_check = true,
563 .stop_clk_fix = true,
564 };
565
566 static const struct mtk_mmc_compatible mt7620_compat = {
567 .clk_div_bits = 8,
568 .recheck_sdio_irq = true,
569 .hs400_tune = false,
570 .pad_tune_reg = MSDC_PAD_TUNE,
571 .async_fifo = false,
572 .data_tune = false,
573 .busy_check = false,
574 .stop_clk_fix = false,
575 .enhance_rx = false,
576 .use_internal_cd = true,
577 };
578
579 static const struct mtk_mmc_compatible mt6779_compat = {
580 .clk_div_bits = 12,
581 .recheck_sdio_irq = false,
582 .hs400_tune = false,
583 .pad_tune_reg = MSDC_PAD_TUNE0,
584 .async_fifo = true,
585 .data_tune = true,
586 .busy_check = true,
587 .stop_clk_fix = true,
588 .enhance_rx = true,
589 .support_64g = true,
590 };
591
592 static const struct of_device_id msdc_of_ids[] = {
593 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
594 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
595 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
596 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
597 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
598 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
599 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
600 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
601 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
602 {}
603 };
604 MODULE_DEVICE_TABLE(of, msdc_of_ids);
605
606 static void sdr_set_bits(void __iomem *reg, u32 bs)
607 {
608 u32 val = readl(reg);
609
610 val |= bs;
611 writel(val, reg);
612 }
613
614 static void sdr_clr_bits(void __iomem *reg, u32 bs)
615 {
616 u32 val = readl(reg);
617
618 val &= ~bs;
619 writel(val, reg);
620 }
621
622 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
623 {
624 unsigned int tv = readl(reg);
625
626 tv &= ~field;
627 tv |= ((val) << (ffs((unsigned int)field) - 1));
628 writel(tv, reg);
629 }
630
631 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
632 {
633 unsigned int tv = readl(reg);
634
635 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
636 }
637
638 static void msdc_reset_hw(struct msdc_host *host)
639 {
640 u32 val;
641
642 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
643 readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
644
645 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
646 readl_poll_timeout(host->base + MSDC_FIFOCS, val,
647 !(val & MSDC_FIFOCS_CLR), 0, 0);
648
649 val = readl(host->base + MSDC_INT);
650 writel(val, host->base + MSDC_INT);
651 }
652
653 static void msdc_cmd_next(struct msdc_host *host,
654 struct mmc_request *mrq, struct mmc_command *cmd);
655 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
656
657 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
658 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
659 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
660 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
661 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
662 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
663
664 static u8 msdc_dma_calcs(u8 *buf, u32 len)
665 {
666 u32 i, sum = 0;
667
668 for (i = 0; i < len; i++)
669 sum += buf[i];
670 return 0xff - (u8) sum;
671 }
672
673 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
674 struct mmc_data *data)
675 {
676 unsigned int j, dma_len;
677 dma_addr_t dma_address;
678 u32 dma_ctrl;
679 struct scatterlist *sg;
680 struct mt_gpdma_desc *gpd;
681 struct mt_bdma_desc *bd;
682
683 sg = data->sg;
684
685 gpd = dma->gpd;
686 bd = dma->bd;
687
688 /* modify gpd */
689 gpd->gpd_info |= GPDMA_DESC_HWO;
690 gpd->gpd_info |= GPDMA_DESC_BDP;
691 /* need to clear first. use these bits to calc checksum */
692 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
693 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
694
695 /* modify bd */
696 for_each_sg(data->sg, sg, data->sg_count, j) {
697 dma_address = sg_dma_address(sg);
698 dma_len = sg_dma_len(sg);
699
700 /* init bd */
701 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
702 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
703 bd[j].ptr = lower_32_bits(dma_address);
704 if (host->dev_comp->support_64g) {
705 bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
706 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
707 << 28;
708 }
709
710 if (host->dev_comp->support_64g) {
711 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
712 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
713 } else {
714 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
715 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
716 }
717
718 if (j == data->sg_count - 1) /* the last bd */
719 bd[j].bd_info |= BDMA_DESC_EOL;
720 else
721 bd[j].bd_info &= ~BDMA_DESC_EOL;
722
723 /* checksume need to clear first */
724 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
725 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
726 }
727
728 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
729 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
730 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
731 dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
732 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
733 if (host->dev_comp->support_64g)
734 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
735 upper_32_bits(dma->gpd_addr) & 0xf);
736 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
737 }
738
739 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
740 {
741 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
742 data->host_cookie |= MSDC_PREPARE_FLAG;
743 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
744 mmc_get_dma_dir(data));
745 }
746 }
747
748 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
749 {
750 if (data->host_cookie & MSDC_ASYNC_FLAG)
751 return;
752
753 if (data->host_cookie & MSDC_PREPARE_FLAG) {
754 dma_unmap_sg(host->dev, data->sg, data->sg_len,
755 mmc_get_dma_dir(data));
756 data->host_cookie &= ~MSDC_PREPARE_FLAG;
757 }
758 }
759
760 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
761 {
762 struct mmc_host *mmc = mmc_from_priv(host);
763 u64 timeout, clk_ns;
764 u32 mode = 0;
765
766 if (mmc->actual_clock == 0) {
767 timeout = 0;
768 } else {
769 clk_ns = 1000000000ULL;
770 do_div(clk_ns, mmc->actual_clock);
771 timeout = ns + clk_ns - 1;
772 do_div(timeout, clk_ns);
773 timeout += clks;
774 /* in 1048576 sclk cycle unit */
775 timeout = DIV_ROUND_UP(timeout, BIT(20));
776 if (host->dev_comp->clk_div_bits == 8)
777 sdr_get_field(host->base + MSDC_CFG,
778 MSDC_CFG_CKMOD, &mode);
779 else
780 sdr_get_field(host->base + MSDC_CFG,
781 MSDC_CFG_CKMOD_EXTRA, &mode);
782 /*DDR mode will double the clk cycles for data timeout */
783 timeout = mode >= 2 ? timeout * 2 : timeout;
784 timeout = timeout > 1 ? timeout - 1 : 0;
785 }
786 return timeout;
787 }
788
789 /* clock control primitives */
790 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
791 {
792 u64 timeout;
793
794 host->timeout_ns = ns;
795 host->timeout_clks = clks;
796
797 timeout = msdc_timeout_cal(host, ns, clks);
798 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
799 (u32)(timeout > 255 ? 255 : timeout));
800 }
801
802 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
803 {
804 u64 timeout;
805
806 timeout = msdc_timeout_cal(host, ns, clks);
807 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
808 (u32)(timeout > 8191 ? 8191 : timeout));
809 }
810
811 static void msdc_gate_clock(struct msdc_host *host)
812 {
813 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
814 clk_disable_unprepare(host->src_clk_cg);
815 clk_disable_unprepare(host->src_clk);
816 clk_disable_unprepare(host->bus_clk);
817 clk_disable_unprepare(host->h_clk);
818 }
819
820 static int msdc_ungate_clock(struct msdc_host *host)
821 {
822 u32 val;
823 int ret;
824
825 clk_prepare_enable(host->h_clk);
826 clk_prepare_enable(host->bus_clk);
827 clk_prepare_enable(host->src_clk);
828 clk_prepare_enable(host->src_clk_cg);
829 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
830 if (ret) {
831 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
832 return ret;
833 }
834
835 return readl_poll_timeout(host->base + MSDC_CFG, val,
836 (val & MSDC_CFG_CKSTB), 1, 20000);
837 }
838
839 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
840 {
841 struct mmc_host *mmc = mmc_from_priv(host);
842 u32 mode;
843 u32 flags;
844 u32 div;
845 u32 sclk;
846 u32 tune_reg = host->dev_comp->pad_tune_reg;
847 u32 val;
848
849 if (!hz) {
850 dev_dbg(host->dev, "set mclk to 0\n");
851 host->mclk = 0;
852 mmc->actual_clock = 0;
853 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
854 return;
855 }
856
857 flags = readl(host->base + MSDC_INTEN);
858 sdr_clr_bits(host->base + MSDC_INTEN, flags);
859 if (host->dev_comp->clk_div_bits == 8)
860 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
861 else
862 sdr_clr_bits(host->base + MSDC_CFG,
863 MSDC_CFG_HS400_CK_MODE_EXTRA);
864 if (timing == MMC_TIMING_UHS_DDR50 ||
865 timing == MMC_TIMING_MMC_DDR52 ||
866 timing == MMC_TIMING_MMC_HS400) {
867 if (timing == MMC_TIMING_MMC_HS400)
868 mode = 0x3;
869 else
870 mode = 0x2; /* ddr mode and use divisor */
871
872 if (hz >= (host->src_clk_freq >> 2)) {
873 div = 0; /* mean div = 1/4 */
874 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
875 } else {
876 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
877 sclk = (host->src_clk_freq >> 2) / div;
878 div = (div >> 1);
879 }
880
881 if (timing == MMC_TIMING_MMC_HS400 &&
882 hz >= (host->src_clk_freq >> 1)) {
883 if (host->dev_comp->clk_div_bits == 8)
884 sdr_set_bits(host->base + MSDC_CFG,
885 MSDC_CFG_HS400_CK_MODE);
886 else
887 sdr_set_bits(host->base + MSDC_CFG,
888 MSDC_CFG_HS400_CK_MODE_EXTRA);
889 sclk = host->src_clk_freq >> 1;
890 div = 0; /* div is ignore when bit18 is set */
891 }
892 } else if (hz >= host->src_clk_freq) {
893 mode = 0x1; /* no divisor */
894 div = 0;
895 sclk = host->src_clk_freq;
896 } else {
897 mode = 0x0; /* use divisor */
898 if (hz >= (host->src_clk_freq >> 1)) {
899 div = 0; /* mean div = 1/2 */
900 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
901 } else {
902 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
903 sclk = (host->src_clk_freq >> 2) / div;
904 }
905 }
906 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
907
908 clk_disable_unprepare(host->src_clk_cg);
909 if (host->dev_comp->clk_div_bits == 8)
910 sdr_set_field(host->base + MSDC_CFG,
911 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
912 (mode << 8) | div);
913 else
914 sdr_set_field(host->base + MSDC_CFG,
915 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
916 (mode << 12) | div);
917
918 clk_prepare_enable(host->src_clk_cg);
919 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
920 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
921 mmc->actual_clock = sclk;
922 host->mclk = hz;
923 host->timing = timing;
924 /* need because clk changed. */
925 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
926 sdr_set_bits(host->base + MSDC_INTEN, flags);
927
928 /*
929 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
930 * tune result of hs200/200Mhz is not suitable for 50Mhz
931 */
932 if (mmc->actual_clock <= 52000000) {
933 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
934 if (host->top_base) {
935 writel(host->def_tune_para.emmc_top_control,
936 host->top_base + EMMC_TOP_CONTROL);
937 writel(host->def_tune_para.emmc_top_cmd,
938 host->top_base + EMMC_TOP_CMD);
939 } else {
940 writel(host->def_tune_para.pad_tune,
941 host->base + tune_reg);
942 }
943 } else {
944 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
945 writel(host->saved_tune_para.pad_cmd_tune,
946 host->base + PAD_CMD_TUNE);
947 if (host->top_base) {
948 writel(host->saved_tune_para.emmc_top_control,
949 host->top_base + EMMC_TOP_CONTROL);
950 writel(host->saved_tune_para.emmc_top_cmd,
951 host->top_base + EMMC_TOP_CMD);
952 } else {
953 writel(host->saved_tune_para.pad_tune,
954 host->base + tune_reg);
955 }
956 }
957
958 if (timing == MMC_TIMING_MMC_HS400 &&
959 host->dev_comp->hs400_tune)
960 sdr_set_field(host->base + tune_reg,
961 MSDC_PAD_TUNE_CMDRRDLY,
962 host->hs400_cmd_int_delay);
963 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
964 timing);
965 }
966
967 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
968 struct mmc_command *cmd)
969 {
970 u32 resp;
971
972 switch (mmc_resp_type(cmd)) {
973 /* Actually, R1, R5, R6, R7 are the same */
974 case MMC_RSP_R1:
975 resp = 0x1;
976 break;
977 case MMC_RSP_R1B:
978 resp = 0x7;
979 break;
980 case MMC_RSP_R2:
981 resp = 0x2;
982 break;
983 case MMC_RSP_R3:
984 resp = 0x3;
985 break;
986 case MMC_RSP_NONE:
987 default:
988 resp = 0x0;
989 break;
990 }
991
992 return resp;
993 }
994
995 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
996 struct mmc_request *mrq, struct mmc_command *cmd)
997 {
998 struct mmc_host *mmc = mmc_from_priv(host);
999 /* rawcmd :
1000 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1001 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1002 */
1003 u32 opcode = cmd->opcode;
1004 u32 resp = msdc_cmd_find_resp(host, cmd);
1005 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1006
1007 host->cmd_rsp = resp;
1008
1009 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1010 opcode == MMC_STOP_TRANSMISSION)
1011 rawcmd |= BIT(14);
1012 else if (opcode == SD_SWITCH_VOLTAGE)
1013 rawcmd |= BIT(30);
1014 else if (opcode == SD_APP_SEND_SCR ||
1015 opcode == SD_APP_SEND_NUM_WR_BLKS ||
1016 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1017 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1018 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1019 rawcmd |= BIT(11);
1020
1021 if (cmd->data) {
1022 struct mmc_data *data = cmd->data;
1023
1024 if (mmc_op_multi(opcode)) {
1025 if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1026 !(mrq->sbc->arg & 0xFFFF0000))
1027 rawcmd |= BIT(29); /* AutoCMD23 */
1028 }
1029
1030 rawcmd |= ((data->blksz & 0xFFF) << 16);
1031 if (data->flags & MMC_DATA_WRITE)
1032 rawcmd |= BIT(13);
1033 if (data->blocks > 1)
1034 rawcmd |= BIT(12);
1035 else
1036 rawcmd |= BIT(11);
1037 /* Always use dma mode */
1038 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1039
1040 if (host->timeout_ns != data->timeout_ns ||
1041 host->timeout_clks != data->timeout_clks)
1042 msdc_set_timeout(host, data->timeout_ns,
1043 data->timeout_clks);
1044
1045 writel(data->blocks, host->base + SDC_BLK_NUM);
1046 }
1047 return rawcmd;
1048 }
1049
1050 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1051 struct mmc_data *data)
1052 {
1053 bool read;
1054
1055 WARN_ON(host->data);
1056 host->data = data;
1057 read = data->flags & MMC_DATA_READ;
1058
1059 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1060 msdc_dma_setup(host, &host->dma, data);
1061 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1062 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1063 dev_dbg(host->dev, "DMA start\n");
1064 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1065 __func__, cmd->opcode, data->blocks, read);
1066 }
1067
1068 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1069 struct mmc_command *cmd)
1070 {
1071 u32 *rsp = cmd->resp;
1072
1073 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1074
1075 if (events & MSDC_INT_ACMDRDY) {
1076 cmd->error = 0;
1077 } else {
1078 msdc_reset_hw(host);
1079 if (events & MSDC_INT_ACMDCRCERR) {
1080 cmd->error = -EILSEQ;
1081 host->error |= REQ_STOP_EIO;
1082 } else if (events & MSDC_INT_ACMDTMO) {
1083 cmd->error = -ETIMEDOUT;
1084 host->error |= REQ_STOP_TMO;
1085 }
1086 dev_err(host->dev,
1087 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1088 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1089 }
1090 return cmd->error;
1091 }
1092
1093 /*
1094 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1095 *
1096 * Host controller may lost interrupt in some special case.
1097 * Add SDIO irq recheck mechanism to make sure all interrupts
1098 * can be processed immediately
1099 */
1100 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1101 {
1102 struct mmc_host *mmc = mmc_from_priv(host);
1103 u32 reg_int, reg_inten, reg_ps;
1104
1105 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1106 reg_inten = readl(host->base + MSDC_INTEN);
1107 if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1108 reg_int = readl(host->base + MSDC_INT);
1109 reg_ps = readl(host->base + MSDC_PS);
1110 if (!(reg_int & MSDC_INT_SDIOIRQ ||
1111 reg_ps & MSDC_PS_DATA1)) {
1112 __msdc_enable_sdio_irq(host, 0);
1113 sdio_signal_irq(mmc);
1114 }
1115 }
1116 }
1117 }
1118
1119 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1120 {
1121 if (host->error)
1122 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1123 __func__, cmd->opcode, cmd->arg, host->error);
1124 }
1125
1126 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1127 {
1128 unsigned long flags;
1129
1130 /*
1131 * No need check the return value of cancel_delayed_work, as only ONE
1132 * path will go here!
1133 */
1134 cancel_delayed_work(&host->req_timeout);
1135
1136 spin_lock_irqsave(&host->lock, flags);
1137 host->mrq = NULL;
1138 spin_unlock_irqrestore(&host->lock, flags);
1139
1140 msdc_track_cmd_data(host, mrq->cmd);
1141 if (mrq->data)
1142 msdc_unprepare_data(host, mrq->data);
1143 if (host->error)
1144 msdc_reset_hw(host);
1145 mmc_request_done(mmc_from_priv(host), mrq);
1146 if (host->dev_comp->recheck_sdio_irq)
1147 msdc_recheck_sdio_irq(host);
1148 }
1149
1150 /* returns true if command is fully handled; returns false otherwise */
1151 static bool msdc_cmd_done(struct msdc_host *host, int events,
1152 struct mmc_request *mrq, struct mmc_command *cmd)
1153 {
1154 bool done = false;
1155 bool sbc_error;
1156 unsigned long flags;
1157 u32 *rsp;
1158
1159 if (mrq->sbc && cmd == mrq->cmd &&
1160 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1161 | MSDC_INT_ACMDTMO)))
1162 msdc_auto_cmd_done(host, events, mrq->sbc);
1163
1164 sbc_error = mrq->sbc && mrq->sbc->error;
1165
1166 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1167 | MSDC_INT_RSPCRCERR
1168 | MSDC_INT_CMDTMO)))
1169 return done;
1170
1171 spin_lock_irqsave(&host->lock, flags);
1172 done = !host->cmd;
1173 host->cmd = NULL;
1174 spin_unlock_irqrestore(&host->lock, flags);
1175
1176 if (done)
1177 return true;
1178 rsp = cmd->resp;
1179
1180 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1181
1182 if (cmd->flags & MMC_RSP_PRESENT) {
1183 if (cmd->flags & MMC_RSP_136) {
1184 rsp[0] = readl(host->base + SDC_RESP3);
1185 rsp[1] = readl(host->base + SDC_RESP2);
1186 rsp[2] = readl(host->base + SDC_RESP1);
1187 rsp[3] = readl(host->base + SDC_RESP0);
1188 } else {
1189 rsp[0] = readl(host->base + SDC_RESP0);
1190 }
1191 }
1192
1193 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1194 if (events & MSDC_INT_CMDTMO ||
1195 (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
1196 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 &&
1197 !host->hs400_tuning))
1198 /*
1199 * should not clear fifo/interrupt as the tune data
1200 * may have alreay come when cmd19/cmd21 gets response
1201 * CRC error.
1202 */
1203 msdc_reset_hw(host);
1204 if (events & MSDC_INT_RSPCRCERR) {
1205 cmd->error = -EILSEQ;
1206 host->error |= REQ_CMD_EIO;
1207 } else if (events & MSDC_INT_CMDTMO) {
1208 cmd->error = -ETIMEDOUT;
1209 host->error |= REQ_CMD_TMO;
1210 }
1211 }
1212 if (cmd->error)
1213 dev_dbg(host->dev,
1214 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1215 __func__, cmd->opcode, cmd->arg, rsp[0],
1216 cmd->error);
1217
1218 msdc_cmd_next(host, mrq, cmd);
1219 return true;
1220 }
1221
1222 /* It is the core layer's responsibility to ensure card status
1223 * is correct before issue a request. but host design do below
1224 * checks recommended.
1225 */
1226 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1227 struct mmc_request *mrq, struct mmc_command *cmd)
1228 {
1229 u32 val;
1230 int ret;
1231
1232 /* The max busy time we can endure is 20ms */
1233 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1234 !(val & SDC_STS_CMDBUSY), 1, 20000);
1235 if (ret) {
1236 dev_err(host->dev, "CMD bus busy detected\n");
1237 host->error |= REQ_CMD_BUSY;
1238 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1239 return false;
1240 }
1241
1242 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1243 /* R1B or with data, should check SDCBUSY */
1244 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1245 !(val & SDC_STS_SDCBUSY), 1, 20000);
1246 if (ret) {
1247 dev_err(host->dev, "Controller busy detected\n");
1248 host->error |= REQ_CMD_BUSY;
1249 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1250 return false;
1251 }
1252 }
1253 return true;
1254 }
1255
1256 static void msdc_start_command(struct msdc_host *host,
1257 struct mmc_request *mrq, struct mmc_command *cmd)
1258 {
1259 u32 rawcmd;
1260 unsigned long flags;
1261
1262 WARN_ON(host->cmd);
1263 host->cmd = cmd;
1264
1265 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1266 if (!msdc_cmd_is_ready(host, mrq, cmd))
1267 return;
1268
1269 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1270 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1271 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1272 msdc_reset_hw(host);
1273 }
1274
1275 cmd->error = 0;
1276 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1277
1278 spin_lock_irqsave(&host->lock, flags);
1279 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1280 spin_unlock_irqrestore(&host->lock, flags);
1281
1282 writel(cmd->arg, host->base + SDC_ARG);
1283 writel(rawcmd, host->base + SDC_CMD);
1284 }
1285
1286 static void msdc_cmd_next(struct msdc_host *host,
1287 struct mmc_request *mrq, struct mmc_command *cmd)
1288 {
1289 if ((cmd->error &&
1290 !(cmd->error == -EILSEQ &&
1291 (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1292 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 ||
1293 host->hs400_tuning))) ||
1294 (mrq->sbc && mrq->sbc->error))
1295 msdc_request_done(host, mrq);
1296 else if (cmd == mrq->sbc)
1297 msdc_start_command(host, mrq, mrq->cmd);
1298 else if (!cmd->data)
1299 msdc_request_done(host, mrq);
1300 else
1301 msdc_start_data(host, cmd, cmd->data);
1302 }
1303
1304 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1305 {
1306 struct msdc_host *host = mmc_priv(mmc);
1307
1308 host->error = 0;
1309 WARN_ON(host->mrq);
1310 host->mrq = mrq;
1311
1312 if (mrq->data)
1313 msdc_prepare_data(host, mrq->data);
1314
1315 /* if SBC is required, we have HW option and SW option.
1316 * if HW option is enabled, and SBC does not have "special" flags,
1317 * use HW option, otherwise use SW option
1318 */
1319 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1320 (mrq->sbc->arg & 0xFFFF0000)))
1321 msdc_start_command(host, mrq, mrq->sbc);
1322 else
1323 msdc_start_command(host, mrq, mrq->cmd);
1324 }
1325
1326 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1327 {
1328 struct msdc_host *host = mmc_priv(mmc);
1329 struct mmc_data *data = mrq->data;
1330
1331 if (!data)
1332 return;
1333
1334 msdc_prepare_data(host, data);
1335 data->host_cookie |= MSDC_ASYNC_FLAG;
1336 }
1337
1338 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1339 int err)
1340 {
1341 struct msdc_host *host = mmc_priv(mmc);
1342 struct mmc_data *data = mrq->data;
1343
1344 if (!data)
1345 return;
1346
1347 if (data->host_cookie) {
1348 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1349 msdc_unprepare_data(host, data);
1350 }
1351 }
1352
1353 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1354 {
1355 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1356 !mrq->sbc)
1357 msdc_start_command(host, mrq, mrq->stop);
1358 else
1359 msdc_request_done(host, mrq);
1360 }
1361
1362 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1363 struct mmc_request *mrq, struct mmc_data *data)
1364 {
1365 struct mmc_command *stop;
1366 unsigned long flags;
1367 bool done;
1368 unsigned int check_data = events &
1369 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1370 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1371 | MSDC_INT_DMA_PROTECT);
1372 u32 val;
1373 int ret;
1374
1375 spin_lock_irqsave(&host->lock, flags);
1376 done = !host->data;
1377 if (check_data)
1378 host->data = NULL;
1379 spin_unlock_irqrestore(&host->lock, flags);
1380
1381 if (done)
1382 return;
1383 stop = data->stop;
1384
1385 if (check_data || (stop && stop->error)) {
1386 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1387 readl(host->base + MSDC_DMA_CFG));
1388 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1389 1);
1390
1391 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1392 !(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1393 if (ret)
1394 dev_dbg(host->dev, "DMA stop timed out\n");
1395
1396 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1397 !(val & MSDC_DMA_CFG_STS), 1, 20000);
1398 if (ret)
1399 dev_dbg(host->dev, "DMA inactive timed out\n");
1400
1401 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1402 dev_dbg(host->dev, "DMA stop\n");
1403
1404 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1405 data->bytes_xfered = data->blocks * data->blksz;
1406 } else {
1407 dev_dbg(host->dev, "interrupt events: %x\n", events);
1408 msdc_reset_hw(host);
1409 host->error |= REQ_DAT_ERR;
1410 data->bytes_xfered = 0;
1411
1412 if (events & MSDC_INT_DATTMO)
1413 data->error = -ETIMEDOUT;
1414 else if (events & MSDC_INT_DATCRCERR)
1415 data->error = -EILSEQ;
1416
1417 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1418 __func__, mrq->cmd->opcode, data->blocks);
1419 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1420 (int)data->error, data->bytes_xfered);
1421 }
1422
1423 msdc_data_xfer_next(host, mrq);
1424 }
1425 }
1426
1427 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1428 {
1429 u32 val = readl(host->base + SDC_CFG);
1430
1431 val &= ~SDC_CFG_BUSWIDTH;
1432
1433 switch (width) {
1434 default:
1435 case MMC_BUS_WIDTH_1:
1436 val |= (MSDC_BUS_1BITS << 16);
1437 break;
1438 case MMC_BUS_WIDTH_4:
1439 val |= (MSDC_BUS_4BITS << 16);
1440 break;
1441 case MMC_BUS_WIDTH_8:
1442 val |= (MSDC_BUS_8BITS << 16);
1443 break;
1444 }
1445
1446 writel(val, host->base + SDC_CFG);
1447 dev_dbg(host->dev, "Bus Width = %d", width);
1448 }
1449
1450 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1451 {
1452 struct msdc_host *host = mmc_priv(mmc);
1453 int ret;
1454
1455 if (!IS_ERR(mmc->supply.vqmmc)) {
1456 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1457 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1458 dev_err(host->dev, "Unsupported signal voltage!\n");
1459 return -EINVAL;
1460 }
1461
1462 ret = mmc_regulator_set_vqmmc(mmc, ios);
1463 if (ret < 0) {
1464 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1465 ret, ios->signal_voltage);
1466 return ret;
1467 }
1468
1469 /* Apply different pinctrl settings for different signal voltage */
1470 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1471 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1472 else
1473 pinctrl_select_state(host->pinctrl, host->pins_default);
1474 }
1475 return 0;
1476 }
1477
1478 static int msdc_card_busy(struct mmc_host *mmc)
1479 {
1480 struct msdc_host *host = mmc_priv(mmc);
1481 u32 status = readl(host->base + MSDC_PS);
1482
1483 /* only check if data0 is low */
1484 return !(status & BIT(16));
1485 }
1486
1487 static void msdc_request_timeout(struct work_struct *work)
1488 {
1489 struct msdc_host *host = container_of(work, struct msdc_host,
1490 req_timeout.work);
1491
1492 /* simulate HW timeout status */
1493 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1494 if (host->mrq) {
1495 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1496 host->mrq, host->mrq->cmd->opcode);
1497 if (host->cmd) {
1498 dev_err(host->dev, "%s: aborting cmd=%d\n",
1499 __func__, host->cmd->opcode);
1500 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1501 host->cmd);
1502 } else if (host->data) {
1503 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1504 __func__, host->mrq->cmd->opcode,
1505 host->data->blocks);
1506 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1507 host->data);
1508 }
1509 }
1510 }
1511
1512 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1513 {
1514 if (enb) {
1515 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1516 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1517 if (host->dev_comp->recheck_sdio_irq)
1518 msdc_recheck_sdio_irq(host);
1519 } else {
1520 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1521 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1522 }
1523 }
1524
1525 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1526 {
1527 struct msdc_host *host = mmc_priv(mmc);
1528 unsigned long flags;
1529 int ret;
1530
1531 spin_lock_irqsave(&host->lock, flags);
1532 __msdc_enable_sdio_irq(host, enb);
1533 spin_unlock_irqrestore(&host->lock, flags);
1534
1535 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1536 if (enb) {
1537 /*
1538 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1539 * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1540 * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1541 * affect successfully, we change the pinstate to pins_eint firstly.
1542 */
1543 pinctrl_select_state(host->pinctrl, host->pins_eint);
1544 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1545
1546 if (ret) {
1547 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1548 host->pins_eint = NULL;
1549 pm_runtime_get_noresume(host->dev);
1550 } else {
1551 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1552 }
1553
1554 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1555 } else {
1556 dev_pm_clear_wake_irq(host->dev);
1557 }
1558 } else {
1559 if (enb) {
1560 /* Ensure host->pins_eint is NULL */
1561 host->pins_eint = NULL;
1562 pm_runtime_get_noresume(host->dev);
1563 } else {
1564 pm_runtime_put_noidle(host->dev);
1565 }
1566 }
1567 }
1568
1569 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1570 {
1571 struct mmc_host *mmc = mmc_from_priv(host);
1572 int cmd_err = 0, dat_err = 0;
1573
1574 if (intsts & MSDC_INT_RSPCRCERR) {
1575 cmd_err = -EILSEQ;
1576 dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1577 } else if (intsts & MSDC_INT_CMDTMO) {
1578 cmd_err = -ETIMEDOUT;
1579 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1580 }
1581
1582 if (intsts & MSDC_INT_DATCRCERR) {
1583 dat_err = -EILSEQ;
1584 dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1585 } else if (intsts & MSDC_INT_DATTMO) {
1586 dat_err = -ETIMEDOUT;
1587 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1588 }
1589
1590 if (cmd_err || dat_err) {
1591 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
1592 cmd_err, dat_err, intsts);
1593 }
1594
1595 return cqhci_irq(mmc, 0, cmd_err, dat_err);
1596 }
1597
1598 static irqreturn_t msdc_irq(int irq, void *dev_id)
1599 {
1600 struct msdc_host *host = (struct msdc_host *) dev_id;
1601 struct mmc_host *mmc = mmc_from_priv(host);
1602
1603 while (true) {
1604 struct mmc_request *mrq;
1605 struct mmc_command *cmd;
1606 struct mmc_data *data;
1607 u32 events, event_mask;
1608
1609 spin_lock(&host->lock);
1610 events = readl(host->base + MSDC_INT);
1611 event_mask = readl(host->base + MSDC_INTEN);
1612 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1613 __msdc_enable_sdio_irq(host, 0);
1614 /* clear interrupts */
1615 writel(events & event_mask, host->base + MSDC_INT);
1616
1617 mrq = host->mrq;
1618 cmd = host->cmd;
1619 data = host->data;
1620 spin_unlock(&host->lock);
1621
1622 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1623 sdio_signal_irq(mmc);
1624
1625 if ((events & event_mask) & MSDC_INT_CDSC) {
1626 if (host->internal_cd)
1627 mmc_detect_change(mmc, msecs_to_jiffies(20));
1628 events &= ~MSDC_INT_CDSC;
1629 }
1630
1631 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1632 break;
1633
1634 if ((mmc->caps2 & MMC_CAP2_CQE) &&
1635 (events & MSDC_INT_CMDQ)) {
1636 msdc_cmdq_irq(host, events);
1637 /* clear interrupts */
1638 writel(events, host->base + MSDC_INT);
1639 return IRQ_HANDLED;
1640 }
1641
1642 if (!mrq) {
1643 dev_err(host->dev,
1644 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1645 __func__, events, event_mask);
1646 WARN_ON(1);
1647 break;
1648 }
1649
1650 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1651
1652 if (cmd)
1653 msdc_cmd_done(host, events, mrq, cmd);
1654 else if (data)
1655 msdc_data_xfer_done(host, events, mrq, data);
1656 }
1657
1658 return IRQ_HANDLED;
1659 }
1660
1661 static void msdc_init_hw(struct msdc_host *host)
1662 {
1663 u32 val;
1664 u32 tune_reg = host->dev_comp->pad_tune_reg;
1665 struct mmc_host *mmc = mmc_from_priv(host);
1666
1667 if (host->reset) {
1668 reset_control_assert(host->reset);
1669 usleep_range(10, 50);
1670 reset_control_deassert(host->reset);
1671 }
1672
1673 /* Configure to MMC/SD mode, clock free running */
1674 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1675
1676 /* Reset */
1677 msdc_reset_hw(host);
1678
1679 /* Disable and clear all interrupts */
1680 writel(0, host->base + MSDC_INTEN);
1681 val = readl(host->base + MSDC_INT);
1682 writel(val, host->base + MSDC_INT);
1683
1684 /* Configure card detection */
1685 if (host->internal_cd) {
1686 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1687 DEFAULT_DEBOUNCE);
1688 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1689 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1690 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1691 } else {
1692 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1693 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1694 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1695 }
1696
1697 if (host->top_base) {
1698 writel(0, host->top_base + EMMC_TOP_CONTROL);
1699 writel(0, host->top_base + EMMC_TOP_CMD);
1700 } else {
1701 writel(0, host->base + tune_reg);
1702 }
1703 writel(0, host->base + MSDC_IOCON);
1704 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1705 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1706 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1707 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1708 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1709
1710 if (host->dev_comp->stop_clk_fix) {
1711 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1712 MSDC_PATCH_BIT1_STOP_DLY, 3);
1713 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1714 SDC_FIFO_CFG_WRVALIDSEL);
1715 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1716 SDC_FIFO_CFG_RDVALIDSEL);
1717 }
1718
1719 if (host->dev_comp->busy_check)
1720 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1721
1722 if (host->dev_comp->async_fifo) {
1723 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1724 MSDC_PB2_RESPWAIT, 3);
1725 if (host->dev_comp->enhance_rx) {
1726 if (host->top_base)
1727 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1728 SDC_RX_ENH_EN);
1729 else
1730 sdr_set_bits(host->base + SDC_ADV_CFG0,
1731 SDC_RX_ENHANCE_EN);
1732 } else {
1733 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1734 MSDC_PB2_RESPSTSENSEL, 2);
1735 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1736 MSDC_PB2_CRCSTSENSEL, 2);
1737 }
1738 /* use async fifo, then no need tune internal delay */
1739 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1740 MSDC_PATCH_BIT2_CFGRESP);
1741 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1742 MSDC_PATCH_BIT2_CFGCRCSTS);
1743 }
1744
1745 if (host->dev_comp->support_64g)
1746 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1747 MSDC_PB2_SUPPORT_64G);
1748 if (host->dev_comp->data_tune) {
1749 if (host->top_base) {
1750 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1751 PAD_DAT_RD_RXDLY_SEL);
1752 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1753 DATA_K_VALUE_SEL);
1754 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1755 PAD_CMD_RD_RXDLY_SEL);
1756 } else {
1757 sdr_set_bits(host->base + tune_reg,
1758 MSDC_PAD_TUNE_RD_SEL |
1759 MSDC_PAD_TUNE_CMD_SEL);
1760 }
1761 } else {
1762 /* choose clock tune */
1763 if (host->top_base)
1764 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1765 PAD_RXDLY_SEL);
1766 else
1767 sdr_set_bits(host->base + tune_reg,
1768 MSDC_PAD_TUNE_RXDLYSEL);
1769 }
1770
1771 if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
1772 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1773 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1774 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1775 } else {
1776 /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
1777 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1778
1779 /* Config SDIO device detect interrupt function */
1780 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1781 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1782 }
1783
1784 /* Configure to default data timeout */
1785 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1786
1787 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1788 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1789 if (host->top_base) {
1790 host->def_tune_para.emmc_top_control =
1791 readl(host->top_base + EMMC_TOP_CONTROL);
1792 host->def_tune_para.emmc_top_cmd =
1793 readl(host->top_base + EMMC_TOP_CMD);
1794 host->saved_tune_para.emmc_top_control =
1795 readl(host->top_base + EMMC_TOP_CONTROL);
1796 host->saved_tune_para.emmc_top_cmd =
1797 readl(host->top_base + EMMC_TOP_CMD);
1798 } else {
1799 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1800 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1801 }
1802 dev_dbg(host->dev, "init hardware done!");
1803 }
1804
1805 static void msdc_deinit_hw(struct msdc_host *host)
1806 {
1807 u32 val;
1808
1809 if (host->internal_cd) {
1810 /* Disabled card-detect */
1811 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1812 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1813 }
1814
1815 /* Disable and clear all interrupts */
1816 writel(0, host->base + MSDC_INTEN);
1817
1818 val = readl(host->base + MSDC_INT);
1819 writel(val, host->base + MSDC_INT);
1820 }
1821
1822 /* init gpd and bd list in msdc_drv_probe */
1823 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1824 {
1825 struct mt_gpdma_desc *gpd = dma->gpd;
1826 struct mt_bdma_desc *bd = dma->bd;
1827 dma_addr_t dma_addr;
1828 int i;
1829
1830 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1831
1832 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1833 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1834 /* gpd->next is must set for desc DMA
1835 * That's why must alloc 2 gpd structure.
1836 */
1837 gpd->next = lower_32_bits(dma_addr);
1838 if (host->dev_comp->support_64g)
1839 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1840
1841 dma_addr = dma->bd_addr;
1842 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1843 if (host->dev_comp->support_64g)
1844 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1845
1846 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1847 for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1848 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1849 bd[i].next = lower_32_bits(dma_addr);
1850 if (host->dev_comp->support_64g)
1851 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1852 }
1853 }
1854
1855 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1856 {
1857 struct msdc_host *host = mmc_priv(mmc);
1858 int ret;
1859
1860 msdc_set_buswidth(host, ios->bus_width);
1861
1862 /* Suspend/Resume will do power off/on */
1863 switch (ios->power_mode) {
1864 case MMC_POWER_UP:
1865 if (!IS_ERR(mmc->supply.vmmc)) {
1866 msdc_init_hw(host);
1867 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1868 ios->vdd);
1869 if (ret) {
1870 dev_err(host->dev, "Failed to set vmmc power!\n");
1871 return;
1872 }
1873 }
1874 break;
1875 case MMC_POWER_ON:
1876 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1877 ret = regulator_enable(mmc->supply.vqmmc);
1878 if (ret)
1879 dev_err(host->dev, "Failed to set vqmmc power!\n");
1880 else
1881 host->vqmmc_enabled = true;
1882 }
1883 break;
1884 case MMC_POWER_OFF:
1885 if (!IS_ERR(mmc->supply.vmmc))
1886 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1887
1888 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1889 regulator_disable(mmc->supply.vqmmc);
1890 host->vqmmc_enabled = false;
1891 }
1892 break;
1893 default:
1894 break;
1895 }
1896
1897 if (host->mclk != ios->clock || host->timing != ios->timing)
1898 msdc_set_mclk(host, ios->timing, ios->clock);
1899 }
1900
1901 static u32 test_delay_bit(u32 delay, u32 bit)
1902 {
1903 bit %= PAD_DELAY_MAX;
1904 return delay & BIT(bit);
1905 }
1906
1907 static int get_delay_len(u32 delay, u32 start_bit)
1908 {
1909 int i;
1910
1911 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1912 if (test_delay_bit(delay, start_bit + i) == 0)
1913 return i;
1914 }
1915 return PAD_DELAY_MAX - start_bit;
1916 }
1917
1918 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1919 {
1920 int start = 0, len = 0;
1921 int start_final = 0, len_final = 0;
1922 u8 final_phase = 0xff;
1923 struct msdc_delay_phase delay_phase = { 0, };
1924
1925 if (delay == 0) {
1926 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1927 delay_phase.final_phase = final_phase;
1928 return delay_phase;
1929 }
1930
1931 while (start < PAD_DELAY_MAX) {
1932 len = get_delay_len(delay, start);
1933 if (len_final < len) {
1934 start_final = start;
1935 len_final = len;
1936 }
1937 start += len ? len : 1;
1938 if (len >= 12 && start_final < 4)
1939 break;
1940 }
1941
1942 /* The rule is that to find the smallest delay cell */
1943 if (start_final == 0)
1944 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1945 else
1946 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1947 dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1948 delay, len_final, final_phase);
1949
1950 delay_phase.maxlen = len_final;
1951 delay_phase.start = start_final;
1952 delay_phase.final_phase = final_phase;
1953 return delay_phase;
1954 }
1955
1956 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1957 {
1958 u32 tune_reg = host->dev_comp->pad_tune_reg;
1959
1960 if (host->top_base)
1961 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1962 value);
1963 else
1964 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1965 value);
1966 }
1967
1968 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1969 {
1970 u32 tune_reg = host->dev_comp->pad_tune_reg;
1971
1972 if (host->top_base)
1973 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
1974 PAD_DAT_RD_RXDLY, value);
1975 else
1976 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
1977 value);
1978 }
1979
1980 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1981 {
1982 struct msdc_host *host = mmc_priv(mmc);
1983 u32 rise_delay = 0, fall_delay = 0;
1984 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1985 struct msdc_delay_phase internal_delay_phase;
1986 u8 final_delay, final_maxlen;
1987 u32 internal_delay = 0;
1988 u32 tune_reg = host->dev_comp->pad_tune_reg;
1989 int cmd_err;
1990 int i, j;
1991
1992 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1993 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1994 sdr_set_field(host->base + tune_reg,
1995 MSDC_PAD_TUNE_CMDRRDLY,
1996 host->hs200_cmd_int_delay);
1997
1998 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1999 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2000 msdc_set_cmd_delay(host, i);
2001 /*
2002 * Using the same parameters, it may sometimes pass the test,
2003 * but sometimes it may fail. To make sure the parameters are
2004 * more stable, we test each set of parameters 3 times.
2005 */
2006 for (j = 0; j < 3; j++) {
2007 mmc_send_tuning(mmc, opcode, &cmd_err);
2008 if (!cmd_err) {
2009 rise_delay |= BIT(i);
2010 } else {
2011 rise_delay &= ~BIT(i);
2012 break;
2013 }
2014 }
2015 }
2016 final_rise_delay = get_best_delay(host, rise_delay);
2017 /* if rising edge has enough margin, then do not scan falling edge */
2018 if (final_rise_delay.maxlen >= 12 ||
2019 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2020 goto skip_fall;
2021
2022 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2023 for (i = 0; i < PAD_DELAY_MAX; i++) {
2024 msdc_set_cmd_delay(host, i);
2025 /*
2026 * Using the same parameters, it may sometimes pass the test,
2027 * but sometimes it may fail. To make sure the parameters are
2028 * more stable, we test each set of parameters 3 times.
2029 */
2030 for (j = 0; j < 3; j++) {
2031 mmc_send_tuning(mmc, opcode, &cmd_err);
2032 if (!cmd_err) {
2033 fall_delay |= BIT(i);
2034 } else {
2035 fall_delay &= ~BIT(i);
2036 break;
2037 }
2038 }
2039 }
2040 final_fall_delay = get_best_delay(host, fall_delay);
2041
2042 skip_fall:
2043 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2044 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2045 final_maxlen = final_fall_delay.maxlen;
2046 if (final_maxlen == final_rise_delay.maxlen) {
2047 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2048 final_delay = final_rise_delay.final_phase;
2049 } else {
2050 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2051 final_delay = final_fall_delay.final_phase;
2052 }
2053 msdc_set_cmd_delay(host, final_delay);
2054
2055 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2056 goto skip_internal;
2057
2058 for (i = 0; i < PAD_DELAY_MAX; i++) {
2059 sdr_set_field(host->base + tune_reg,
2060 MSDC_PAD_TUNE_CMDRRDLY, i);
2061 mmc_send_tuning(mmc, opcode, &cmd_err);
2062 if (!cmd_err)
2063 internal_delay |= BIT(i);
2064 }
2065 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2066 internal_delay_phase = get_best_delay(host, internal_delay);
2067 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2068 internal_delay_phase.final_phase);
2069 skip_internal:
2070 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2071 return final_delay == 0xff ? -EIO : 0;
2072 }
2073
2074 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2075 {
2076 struct msdc_host *host = mmc_priv(mmc);
2077 u32 cmd_delay = 0;
2078 struct msdc_delay_phase final_cmd_delay = { 0,};
2079 u8 final_delay;
2080 int cmd_err;
2081 int i, j;
2082
2083 /* select EMMC50 PAD CMD tune */
2084 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2085 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2086
2087 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2088 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2089 sdr_set_field(host->base + MSDC_PAD_TUNE,
2090 MSDC_PAD_TUNE_CMDRRDLY,
2091 host->hs200_cmd_int_delay);
2092
2093 if (host->hs400_cmd_resp_sel_rising)
2094 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2095 else
2096 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2097 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2098 sdr_set_field(host->base + PAD_CMD_TUNE,
2099 PAD_CMD_TUNE_RX_DLY3, i);
2100 /*
2101 * Using the same parameters, it may sometimes pass the test,
2102 * but sometimes it may fail. To make sure the parameters are
2103 * more stable, we test each set of parameters 3 times.
2104 */
2105 for (j = 0; j < 3; j++) {
2106 mmc_send_tuning(mmc, opcode, &cmd_err);
2107 if (!cmd_err) {
2108 cmd_delay |= BIT(i);
2109 } else {
2110 cmd_delay &= ~BIT(i);
2111 break;
2112 }
2113 }
2114 }
2115 final_cmd_delay = get_best_delay(host, cmd_delay);
2116 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2117 final_cmd_delay.final_phase);
2118 final_delay = final_cmd_delay.final_phase;
2119
2120 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2121 return final_delay == 0xff ? -EIO : 0;
2122 }
2123
2124 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2125 {
2126 struct msdc_host *host = mmc_priv(mmc);
2127 u32 rise_delay = 0, fall_delay = 0;
2128 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2129 u8 final_delay, final_maxlen;
2130 int i, ret;
2131
2132 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2133 host->latch_ck);
2134 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2135 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2136 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2137 msdc_set_data_delay(host, i);
2138 ret = mmc_send_tuning(mmc, opcode, NULL);
2139 if (!ret)
2140 rise_delay |= BIT(i);
2141 }
2142 final_rise_delay = get_best_delay(host, rise_delay);
2143 /* if rising edge has enough margin, then do not scan falling edge */
2144 if (final_rise_delay.maxlen >= 12 ||
2145 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2146 goto skip_fall;
2147
2148 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2149 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2150 for (i = 0; i < PAD_DELAY_MAX; i++) {
2151 msdc_set_data_delay(host, i);
2152 ret = mmc_send_tuning(mmc, opcode, NULL);
2153 if (!ret)
2154 fall_delay |= BIT(i);
2155 }
2156 final_fall_delay = get_best_delay(host, fall_delay);
2157
2158 skip_fall:
2159 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2160 if (final_maxlen == final_rise_delay.maxlen) {
2161 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2162 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2163 final_delay = final_rise_delay.final_phase;
2164 } else {
2165 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2166 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2167 final_delay = final_fall_delay.final_phase;
2168 }
2169 msdc_set_data_delay(host, final_delay);
2170
2171 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2172 return final_delay == 0xff ? -EIO : 0;
2173 }
2174
2175 /*
2176 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2177 * together, which can save the tuning time.
2178 */
2179 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2180 {
2181 struct msdc_host *host = mmc_priv(mmc);
2182 u32 rise_delay = 0, fall_delay = 0;
2183 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2184 u8 final_delay, final_maxlen;
2185 int i, ret;
2186
2187 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2188 host->latch_ck);
2189
2190 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2191 sdr_clr_bits(host->base + MSDC_IOCON,
2192 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2193 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2194 msdc_set_cmd_delay(host, i);
2195 msdc_set_data_delay(host, i);
2196 ret = mmc_send_tuning(mmc, opcode, NULL);
2197 if (!ret)
2198 rise_delay |= BIT(i);
2199 }
2200 final_rise_delay = get_best_delay(host, rise_delay);
2201 /* if rising edge has enough margin, then do not scan falling edge */
2202 if (final_rise_delay.maxlen >= 12 ||
2203 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2204 goto skip_fall;
2205
2206 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2207 sdr_set_bits(host->base + MSDC_IOCON,
2208 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2209 for (i = 0; i < PAD_DELAY_MAX; i++) {
2210 msdc_set_cmd_delay(host, i);
2211 msdc_set_data_delay(host, i);
2212 ret = mmc_send_tuning(mmc, opcode, NULL);
2213 if (!ret)
2214 fall_delay |= BIT(i);
2215 }
2216 final_fall_delay = get_best_delay(host, fall_delay);
2217
2218 skip_fall:
2219 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2220 if (final_maxlen == final_rise_delay.maxlen) {
2221 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2222 sdr_clr_bits(host->base + MSDC_IOCON,
2223 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2224 final_delay = final_rise_delay.final_phase;
2225 } else {
2226 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2227 sdr_set_bits(host->base + MSDC_IOCON,
2228 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2229 final_delay = final_fall_delay.final_phase;
2230 }
2231
2232 msdc_set_cmd_delay(host, final_delay);
2233 msdc_set_data_delay(host, final_delay);
2234
2235 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2236 return final_delay == 0xff ? -EIO : 0;
2237 }
2238
2239 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2240 {
2241 struct msdc_host *host = mmc_priv(mmc);
2242 int ret;
2243 u32 tune_reg = host->dev_comp->pad_tune_reg;
2244
2245 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2246 ret = msdc_tune_together(mmc, opcode);
2247 if (host->hs400_mode) {
2248 sdr_clr_bits(host->base + MSDC_IOCON,
2249 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2250 msdc_set_data_delay(host, 0);
2251 }
2252 goto tune_done;
2253 }
2254 if (host->hs400_mode &&
2255 host->dev_comp->hs400_tune)
2256 ret = hs400_tune_response(mmc, opcode);
2257 else
2258 ret = msdc_tune_response(mmc, opcode);
2259 if (ret == -EIO) {
2260 dev_err(host->dev, "Tune response fail!\n");
2261 return ret;
2262 }
2263 if (host->hs400_mode == false) {
2264 ret = msdc_tune_data(mmc, opcode);
2265 if (ret == -EIO)
2266 dev_err(host->dev, "Tune data fail!\n");
2267 }
2268
2269 tune_done:
2270 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2271 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2272 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2273 if (host->top_base) {
2274 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2275 EMMC_TOP_CONTROL);
2276 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2277 EMMC_TOP_CMD);
2278 }
2279 return ret;
2280 }
2281
2282 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2283 {
2284 struct msdc_host *host = mmc_priv(mmc);
2285 host->hs400_mode = true;
2286
2287 if (host->top_base)
2288 writel(host->hs400_ds_delay,
2289 host->top_base + EMMC50_PAD_DS_TUNE);
2290 else
2291 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2292 /* hs400 mode must set it to 0 */
2293 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2294 /* to improve read performance, set outstanding to 2 */
2295 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2296
2297 return 0;
2298 }
2299
2300 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2301 {
2302 struct msdc_host *host = mmc_priv(mmc);
2303 struct msdc_delay_phase dly1_delay;
2304 u32 val, result_dly1 = 0;
2305 u8 *ext_csd;
2306 int i, ret;
2307
2308 if (host->top_base) {
2309 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2310 PAD_DS_DLY_SEL);
2311 if (host->hs400_ds_dly3)
2312 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2313 PAD_DS_DLY3, host->hs400_ds_dly3);
2314 } else {
2315 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2316 if (host->hs400_ds_dly3)
2317 sdr_set_field(host->base + PAD_DS_TUNE,
2318 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2319 }
2320
2321 host->hs400_tuning = true;
2322 for (i = 0; i < PAD_DELAY_MAX; i++) {
2323 if (host->top_base)
2324 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2325 PAD_DS_DLY1, i);
2326 else
2327 sdr_set_field(host->base + PAD_DS_TUNE,
2328 PAD_DS_TUNE_DLY1, i);
2329 ret = mmc_get_ext_csd(card, &ext_csd);
2330 if (!ret) {
2331 result_dly1 |= BIT(i);
2332 kfree(ext_csd);
2333 }
2334 }
2335 host->hs400_tuning = false;
2336
2337 dly1_delay = get_best_delay(host, result_dly1);
2338 if (dly1_delay.maxlen == 0) {
2339 dev_err(host->dev, "Failed to get DLY1 delay!\n");
2340 goto fail;
2341 }
2342 if (host->top_base)
2343 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2344 PAD_DS_DLY1, dly1_delay.final_phase);
2345 else
2346 sdr_set_field(host->base + PAD_DS_TUNE,
2347 PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2348
2349 if (host->top_base)
2350 val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2351 else
2352 val = readl(host->base + PAD_DS_TUNE);
2353
2354 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2355
2356 return 0;
2357
2358 fail:
2359 dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2360 return -EIO;
2361 }
2362
2363 static void msdc_hw_reset(struct mmc_host *mmc)
2364 {
2365 struct msdc_host *host = mmc_priv(mmc);
2366
2367 sdr_set_bits(host->base + EMMC_IOCON, 1);
2368 udelay(10); /* 10us is enough */
2369 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2370 }
2371
2372 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2373 {
2374 unsigned long flags;
2375 struct msdc_host *host = mmc_priv(mmc);
2376
2377 spin_lock_irqsave(&host->lock, flags);
2378 __msdc_enable_sdio_irq(host, 1);
2379 spin_unlock_irqrestore(&host->lock, flags);
2380 }
2381
2382 static int msdc_get_cd(struct mmc_host *mmc)
2383 {
2384 struct msdc_host *host = mmc_priv(mmc);
2385 int val;
2386
2387 if (mmc->caps & MMC_CAP_NONREMOVABLE)
2388 return 1;
2389
2390 if (!host->internal_cd)
2391 return mmc_gpio_get_cd(mmc);
2392
2393 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2394 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2395 return !!val;
2396 else
2397 return !val;
2398 }
2399
2400 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2401 struct mmc_ios *ios)
2402 {
2403 struct msdc_host *host = mmc_priv(mmc);
2404
2405 if (ios->enhanced_strobe) {
2406 msdc_prepare_hs400_tuning(mmc, ios);
2407 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2408 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2409 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2410
2411 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2412 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2413 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2414 } else {
2415 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2416 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2417 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2418
2419 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2420 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2421 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2422 }
2423 }
2424
2425 static void msdc_cqe_enable(struct mmc_host *mmc)
2426 {
2427 struct msdc_host *host = mmc_priv(mmc);
2428
2429 /* enable cmdq irq */
2430 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2431 /* enable busy check */
2432 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2433 /* default write data / busy timeout 20s */
2434 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2435 /* default read data timeout 1s */
2436 msdc_set_timeout(host, 1000000000ULL, 0);
2437 }
2438
2439 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2440 {
2441 struct msdc_host *host = mmc_priv(mmc);
2442 unsigned int val = 0;
2443
2444 /* disable cmdq irq */
2445 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2446 /* disable busy check */
2447 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2448
2449 if (recovery) {
2450 sdr_set_field(host->base + MSDC_DMA_CTRL,
2451 MSDC_DMA_CTRL_STOP, 1);
2452 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2453 !(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2454 return;
2455 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2456 !(val & MSDC_DMA_CFG_STS), 1, 3000)))
2457 return;
2458 msdc_reset_hw(host);
2459 }
2460 }
2461
2462 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2463 {
2464 struct cqhci_host *cq_host = mmc->cqe_private;
2465 u32 reg;
2466
2467 reg = cqhci_readl(cq_host, CQHCI_CFG);
2468 reg |= CQHCI_ENABLE;
2469 cqhci_writel(cq_host, reg, CQHCI_CFG);
2470 }
2471
2472 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2473 {
2474 struct cqhci_host *cq_host = mmc->cqe_private;
2475 u32 reg;
2476
2477 reg = cqhci_readl(cq_host, CQHCI_CFG);
2478 reg &= ~CQHCI_ENABLE;
2479 cqhci_writel(cq_host, reg, CQHCI_CFG);
2480 }
2481
2482 static const struct mmc_host_ops mt_msdc_ops = {
2483 .post_req = msdc_post_req,
2484 .pre_req = msdc_pre_req,
2485 .request = msdc_ops_request,
2486 .set_ios = msdc_ops_set_ios,
2487 .get_ro = mmc_gpio_get_ro,
2488 .get_cd = msdc_get_cd,
2489 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2490 .enable_sdio_irq = msdc_enable_sdio_irq,
2491 .ack_sdio_irq = msdc_ack_sdio_irq,
2492 .start_signal_voltage_switch = msdc_ops_switch_volt,
2493 .card_busy = msdc_card_busy,
2494 .execute_tuning = msdc_execute_tuning,
2495 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2496 .execute_hs400_tuning = msdc_execute_hs400_tuning,
2497 .card_hw_reset = msdc_hw_reset,
2498 };
2499
2500 static const struct cqhci_host_ops msdc_cmdq_ops = {
2501 .enable = msdc_cqe_enable,
2502 .disable = msdc_cqe_disable,
2503 .pre_enable = msdc_cqe_pre_enable,
2504 .post_disable = msdc_cqe_post_disable,
2505 };
2506
2507 static void msdc_of_property_parse(struct platform_device *pdev,
2508 struct msdc_host *host)
2509 {
2510 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2511 &host->latch_ck);
2512
2513 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2514 &host->hs400_ds_delay);
2515
2516 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2517 &host->hs400_ds_dly3);
2518
2519 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2520 &host->hs200_cmd_int_delay);
2521
2522 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2523 &host->hs400_cmd_int_delay);
2524
2525 if (of_property_read_bool(pdev->dev.of_node,
2526 "mediatek,hs400-cmd-resp-sel-rising"))
2527 host->hs400_cmd_resp_sel_rising = true;
2528 else
2529 host->hs400_cmd_resp_sel_rising = false;
2530
2531 if (of_property_read_bool(pdev->dev.of_node,
2532 "supports-cqe"))
2533 host->cqhci = true;
2534 else
2535 host->cqhci = false;
2536 }
2537
2538 static int msdc_of_clock_parse(struct platform_device *pdev,
2539 struct msdc_host *host)
2540 {
2541 int ret;
2542
2543 host->src_clk = devm_clk_get(&pdev->dev, "source");
2544 if (IS_ERR(host->src_clk))
2545 return PTR_ERR(host->src_clk);
2546
2547 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2548 if (IS_ERR(host->h_clk))
2549 return PTR_ERR(host->h_clk);
2550
2551 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2552 if (IS_ERR(host->bus_clk))
2553 host->bus_clk = NULL;
2554
2555 /*source clock control gate is optional clock*/
2556 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2557 if (IS_ERR(host->src_clk_cg))
2558 return PTR_ERR(host->src_clk_cg);
2559
2560 /*
2561 * Fallback for legacy device-trees: src_clk and HCLK use the same
2562 * bit to control gating but they are parented to a different mux,
2563 * hence if our intention is to gate only the source, required
2564 * during a clk mode switch to avoid hw hangs, we need to gate
2565 * its parent (specified as a different clock only on new DTs).
2566 */
2567 if (!host->src_clk_cg) {
2568 host->src_clk_cg = clk_get_parent(host->src_clk);
2569 if (IS_ERR(host->src_clk_cg))
2570 return PTR_ERR(host->src_clk_cg);
2571 }
2572
2573 host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg");
2574 if (IS_ERR(host->sys_clk_cg))
2575 host->sys_clk_cg = NULL;
2576
2577 /* If present, always enable for this clock gate */
2578 clk_prepare_enable(host->sys_clk_cg);
2579
2580 host->bulk_clks[0].id = "pclk_cg";
2581 host->bulk_clks[1].id = "axi_cg";
2582 host->bulk_clks[2].id = "ahb_cg";
2583 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2584 host->bulk_clks);
2585 if (ret) {
2586 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2587 return ret;
2588 }
2589
2590 return 0;
2591 }
2592
2593 static int msdc_drv_probe(struct platform_device *pdev)
2594 {
2595 struct mmc_host *mmc;
2596 struct msdc_host *host;
2597 struct resource *res;
2598 int ret;
2599
2600 if (!pdev->dev.of_node) {
2601 dev_err(&pdev->dev, "No DT found\n");
2602 return -EINVAL;
2603 }
2604
2605 /* Allocate MMC host for this device */
2606 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2607 if (!mmc)
2608 return -ENOMEM;
2609
2610 host = mmc_priv(mmc);
2611 ret = mmc_of_parse(mmc);
2612 if (ret)
2613 goto host_free;
2614
2615 host->base = devm_platform_ioremap_resource(pdev, 0);
2616 if (IS_ERR(host->base)) {
2617 ret = PTR_ERR(host->base);
2618 goto host_free;
2619 }
2620
2621 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2622 if (res) {
2623 host->top_base = devm_ioremap_resource(&pdev->dev, res);
2624 if (IS_ERR(host->top_base))
2625 host->top_base = NULL;
2626 }
2627
2628 ret = mmc_regulator_get_supply(mmc);
2629 if (ret)
2630 goto host_free;
2631
2632 ret = msdc_of_clock_parse(pdev, host);
2633 if (ret)
2634 goto host_free;
2635
2636 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2637 "hrst");
2638 if (IS_ERR(host->reset)) {
2639 ret = PTR_ERR(host->reset);
2640 goto host_free;
2641 }
2642
2643 host->irq = platform_get_irq(pdev, 0);
2644 if (host->irq < 0) {
2645 ret = -EINVAL;
2646 goto host_free;
2647 }
2648
2649 host->pinctrl = devm_pinctrl_get(&pdev->dev);
2650 if (IS_ERR(host->pinctrl)) {
2651 ret = PTR_ERR(host->pinctrl);
2652 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
2653 goto host_free;
2654 }
2655
2656 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2657 if (IS_ERR(host->pins_default)) {
2658 ret = PTR_ERR(host->pins_default);
2659 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2660 goto host_free;
2661 }
2662
2663 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2664 if (IS_ERR(host->pins_uhs)) {
2665 ret = PTR_ERR(host->pins_uhs);
2666 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2667 goto host_free;
2668 }
2669
2670 /* Support for SDIO eint irq ? */
2671 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
2672 host->eint_irq = platform_get_irq_byname(pdev, "sdio_wakeup");
2673 if (host->eint_irq > 0) {
2674 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
2675 if (IS_ERR(host->pins_eint)) {
2676 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
2677 host->pins_eint = NULL;
2678 } else {
2679 device_init_wakeup(&pdev->dev, true);
2680 }
2681 }
2682 }
2683
2684 msdc_of_property_parse(pdev, host);
2685
2686 host->dev = &pdev->dev;
2687 host->dev_comp = of_device_get_match_data(&pdev->dev);
2688 host->src_clk_freq = clk_get_rate(host->src_clk);
2689 /* Set host parameters to mmc */
2690 mmc->ops = &mt_msdc_ops;
2691 if (host->dev_comp->clk_div_bits == 8)
2692 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2693 else
2694 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2695
2696 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2697 !mmc_can_gpio_cd(mmc) &&
2698 host->dev_comp->use_internal_cd) {
2699 /*
2700 * Is removable but no GPIO declared, so
2701 * use internal functionality.
2702 */
2703 host->internal_cd = true;
2704 }
2705
2706 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2707 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2708
2709 mmc->caps |= MMC_CAP_CMD23;
2710 if (host->cqhci)
2711 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2712 /* MMC core transfer sizes tunable parameters */
2713 mmc->max_segs = MAX_BD_NUM;
2714 if (host->dev_comp->support_64g)
2715 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2716 else
2717 mmc->max_seg_size = BDMA_DESC_BUFLEN;
2718 mmc->max_blk_size = 2048;
2719 mmc->max_req_size = 512 * 1024;
2720 mmc->max_blk_count = mmc->max_req_size / 512;
2721 if (host->dev_comp->support_64g)
2722 host->dma_mask = DMA_BIT_MASK(36);
2723 else
2724 host->dma_mask = DMA_BIT_MASK(32);
2725 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2726
2727 host->timeout_clks = 3 * 1048576;
2728 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2729 2 * sizeof(struct mt_gpdma_desc),
2730 &host->dma.gpd_addr, GFP_KERNEL);
2731 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2732 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2733 &host->dma.bd_addr, GFP_KERNEL);
2734 if (!host->dma.gpd || !host->dma.bd) {
2735 ret = -ENOMEM;
2736 goto release_mem;
2737 }
2738 msdc_init_gpd_bd(host, &host->dma);
2739 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2740 spin_lock_init(&host->lock);
2741
2742 platform_set_drvdata(pdev, mmc);
2743 ret = msdc_ungate_clock(host);
2744 if (ret) {
2745 dev_err(&pdev->dev, "Cannot ungate clocks!\n");
2746 goto release_mem;
2747 }
2748 msdc_init_hw(host);
2749
2750 if (mmc->caps2 & MMC_CAP2_CQE) {
2751 host->cq_host = devm_kzalloc(mmc->parent,
2752 sizeof(*host->cq_host),
2753 GFP_KERNEL);
2754 if (!host->cq_host) {
2755 ret = -ENOMEM;
2756 goto host_free;
2757 }
2758 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2759 host->cq_host->mmio = host->base + 0x800;
2760 host->cq_host->ops = &msdc_cmdq_ops;
2761 ret = cqhci_init(host->cq_host, mmc, true);
2762 if (ret)
2763 goto host_free;
2764 mmc->max_segs = 128;
2765 /* cqhci 16bit length */
2766 /* 0 size, means 65536 so we don't have to -1 here */
2767 mmc->max_seg_size = 64 * 1024;
2768 }
2769
2770 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2771 IRQF_TRIGGER_NONE, pdev->name, host);
2772 if (ret)
2773 goto release;
2774
2775 pm_runtime_set_active(host->dev);
2776 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2777 pm_runtime_use_autosuspend(host->dev);
2778 pm_runtime_enable(host->dev);
2779 ret = mmc_add_host(mmc);
2780
2781 if (ret)
2782 goto end;
2783
2784 return 0;
2785 end:
2786 pm_runtime_disable(host->dev);
2787 release:
2788 platform_set_drvdata(pdev, NULL);
2789 msdc_deinit_hw(host);
2790 msdc_gate_clock(host);
2791 release_mem:
2792 if (host->dma.gpd)
2793 dma_free_coherent(&pdev->dev,
2794 2 * sizeof(struct mt_gpdma_desc),
2795 host->dma.gpd, host->dma.gpd_addr);
2796 if (host->dma.bd)
2797 dma_free_coherent(&pdev->dev,
2798 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2799 host->dma.bd, host->dma.bd_addr);
2800 host_free:
2801 mmc_free_host(mmc);
2802
2803 return ret;
2804 }
2805
2806 static int msdc_drv_remove(struct platform_device *pdev)
2807 {
2808 struct mmc_host *mmc;
2809 struct msdc_host *host;
2810
2811 mmc = platform_get_drvdata(pdev);
2812 host = mmc_priv(mmc);
2813
2814 pm_runtime_get_sync(host->dev);
2815
2816 platform_set_drvdata(pdev, NULL);
2817 mmc_remove_host(mmc);
2818 msdc_deinit_hw(host);
2819 msdc_gate_clock(host);
2820
2821 pm_runtime_disable(host->dev);
2822 pm_runtime_put_noidle(host->dev);
2823 dma_free_coherent(&pdev->dev,
2824 2 * sizeof(struct mt_gpdma_desc),
2825 host->dma.gpd, host->dma.gpd_addr);
2826 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2827 host->dma.bd, host->dma.bd_addr);
2828
2829 mmc_free_host(mmc);
2830
2831 return 0;
2832 }
2833
2834 static void msdc_save_reg(struct msdc_host *host)
2835 {
2836 u32 tune_reg = host->dev_comp->pad_tune_reg;
2837
2838 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2839 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2840 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2841 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2842 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2843 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2844 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2845 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2846 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2847 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2848 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2849 if (host->top_base) {
2850 host->save_para.emmc_top_control =
2851 readl(host->top_base + EMMC_TOP_CONTROL);
2852 host->save_para.emmc_top_cmd =
2853 readl(host->top_base + EMMC_TOP_CMD);
2854 host->save_para.emmc50_pad_ds_tune =
2855 readl(host->top_base + EMMC50_PAD_DS_TUNE);
2856 } else {
2857 host->save_para.pad_tune = readl(host->base + tune_reg);
2858 }
2859 }
2860
2861 static void msdc_restore_reg(struct msdc_host *host)
2862 {
2863 struct mmc_host *mmc = mmc_from_priv(host);
2864 u32 tune_reg = host->dev_comp->pad_tune_reg;
2865
2866 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2867 writel(host->save_para.iocon, host->base + MSDC_IOCON);
2868 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2869 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2870 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2871 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2872 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2873 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2874 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2875 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2876 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2877 if (host->top_base) {
2878 writel(host->save_para.emmc_top_control,
2879 host->top_base + EMMC_TOP_CONTROL);
2880 writel(host->save_para.emmc_top_cmd,
2881 host->top_base + EMMC_TOP_CMD);
2882 writel(host->save_para.emmc50_pad_ds_tune,
2883 host->top_base + EMMC50_PAD_DS_TUNE);
2884 } else {
2885 writel(host->save_para.pad_tune, host->base + tune_reg);
2886 }
2887
2888 if (sdio_irq_claimed(mmc))
2889 __msdc_enable_sdio_irq(host, 1);
2890 }
2891
2892 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
2893 {
2894 struct mmc_host *mmc = dev_get_drvdata(dev);
2895 struct msdc_host *host = mmc_priv(mmc);
2896
2897 msdc_save_reg(host);
2898
2899 if (sdio_irq_claimed(mmc)) {
2900 if (host->pins_eint) {
2901 disable_irq(host->irq);
2902 pinctrl_select_state(host->pinctrl, host->pins_eint);
2903 }
2904
2905 __msdc_enable_sdio_irq(host, 0);
2906 }
2907 msdc_gate_clock(host);
2908 return 0;
2909 }
2910
2911 static int __maybe_unused msdc_runtime_resume(struct device *dev)
2912 {
2913 struct mmc_host *mmc = dev_get_drvdata(dev);
2914 struct msdc_host *host = mmc_priv(mmc);
2915 int ret;
2916
2917 ret = msdc_ungate_clock(host);
2918 if (ret)
2919 return ret;
2920
2921 msdc_restore_reg(host);
2922
2923 if (sdio_irq_claimed(mmc) && host->pins_eint) {
2924 pinctrl_select_state(host->pinctrl, host->pins_uhs);
2925 enable_irq(host->irq);
2926 }
2927 return 0;
2928 }
2929
2930 static int __maybe_unused msdc_suspend(struct device *dev)
2931 {
2932 struct mmc_host *mmc = dev_get_drvdata(dev);
2933 struct msdc_host *host = mmc_priv(mmc);
2934 int ret;
2935
2936 if (mmc->caps2 & MMC_CAP2_CQE) {
2937 ret = cqhci_suspend(mmc);
2938 if (ret)
2939 return ret;
2940 }
2941
2942 /*
2943 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
2944 * not be marked as 1, pm_runtime_force_resume() will go out directly.
2945 */
2946 if (sdio_irq_claimed(mmc) && host->pins_eint)
2947 pm_runtime_get_noresume(dev);
2948
2949 return pm_runtime_force_suspend(dev);
2950 }
2951
2952 static int __maybe_unused msdc_resume(struct device *dev)
2953 {
2954 struct mmc_host *mmc = dev_get_drvdata(dev);
2955 struct msdc_host *host = mmc_priv(mmc);
2956
2957 if (sdio_irq_claimed(mmc) && host->pins_eint)
2958 pm_runtime_put_noidle(dev);
2959
2960 return pm_runtime_force_resume(dev);
2961 }
2962
2963 static const struct dev_pm_ops msdc_dev_pm_ops = {
2964 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
2965 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
2966 };
2967
2968 static struct platform_driver mt_msdc_driver = {
2969 .probe = msdc_drv_probe,
2970 .remove = msdc_drv_remove,
2971 .driver = {
2972 .name = "mtk-msdc",
2973 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2974 .of_match_table = msdc_of_ids,
2975 .pm = &msdc_dev_pm_ops,
2976 },
2977 };
2978
2979 module_platform_driver(mt_msdc_driver);
2980 MODULE_LICENSE("GPL v2");
2981 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
Michael's Linux tree.