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gpu: host1x: Use SMMU on Tegra124 and Tegra210
[thirdparty/linux.git] / drivers / mmc / host / sdhci-msm.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
4 *
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6 */
7
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/delay.h>
11 #include <linux/mmc/mmc.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/slab.h>
14 #include <linux/iopoll.h>
15 #include <linux/regulator/consumer.h>
16
17 #include "sdhci-pltfm.h"
18 #include "cqhci.h"
19
20 #define CORE_MCI_VERSION 0x50
21 #define CORE_VERSION_MAJOR_SHIFT 28
22 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
23 #define CORE_VERSION_MINOR_MASK 0xff
24
25 #define CORE_MCI_GENERICS 0x70
26 #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
27
28 #define HC_MODE_EN 0x1
29 #define CORE_POWER 0x0
30 #define CORE_SW_RST BIT(7)
31 #define FF_CLK_SW_RST_DIS BIT(13)
32
33 #define CORE_PWRCTL_BUS_OFF BIT(0)
34 #define CORE_PWRCTL_BUS_ON BIT(1)
35 #define CORE_PWRCTL_IO_LOW BIT(2)
36 #define CORE_PWRCTL_IO_HIGH BIT(3)
37 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
38 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
39 #define REQ_BUS_OFF BIT(0)
40 #define REQ_BUS_ON BIT(1)
41 #define REQ_IO_LOW BIT(2)
42 #define REQ_IO_HIGH BIT(3)
43 #define INT_MASK 0xf
44 #define MAX_PHASES 16
45 #define CORE_DLL_LOCK BIT(7)
46 #define CORE_DDR_DLL_LOCK BIT(11)
47 #define CORE_DLL_EN BIT(16)
48 #define CORE_CDR_EN BIT(17)
49 #define CORE_CK_OUT_EN BIT(18)
50 #define CORE_CDR_EXT_EN BIT(19)
51 #define CORE_DLL_PDN BIT(29)
52 #define CORE_DLL_RST BIT(30)
53 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
54
55 #define CORE_DDR_CAL_EN BIT(0)
56 #define CORE_FLL_CYCLE_CNT BIT(18)
57 #define CORE_DLL_CLOCK_DISABLE BIT(21)
58
59 #define CORE_VENDOR_SPEC_POR_VAL 0xa1c
60 #define CORE_CLK_PWRSAVE BIT(1)
61 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
62 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
63 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
64 #define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15)
65 #define CORE_IO_PAD_PWR_SWITCH (1 << 16)
66 #define CORE_HC_SELECT_IN_EN BIT(18)
67 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
68 #define CORE_HC_SELECT_IN_MASK (7 << 19)
69
70 #define CORE_3_0V_SUPPORT (1 << 25)
71 #define CORE_1_8V_SUPPORT (1 << 26)
72 #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
73
74 #define CORE_CSR_CDC_CTLR_CFG0 0x130
75 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
76 #define CORE_HW_AUTOCAL_ENA BIT(17)
77
78 #define CORE_CSR_CDC_CTLR_CFG1 0x134
79 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
80 #define CORE_TIMER_ENA BIT(16)
81
82 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
83 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
84 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
85 #define CORE_CDC_OFFSET_CFG 0x14C
86 #define CORE_CSR_CDC_DELAY_CFG 0x150
87 #define CORE_CDC_SLAVE_DDA_CFG 0x160
88 #define CORE_CSR_CDC_STATUS0 0x164
89 #define CORE_CALIBRATION_DONE BIT(0)
90
91 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
92
93 #define CORE_CSR_CDC_GEN_CFG 0x178
94 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
95 #define CORE_CDC_SWITCH_RC_EN BIT(1)
96
97 #define CORE_CDC_T4_DLY_SEL BIT(0)
98 #define CORE_CMDIN_RCLK_EN BIT(1)
99 #define CORE_START_CDC_TRAFFIC BIT(6)
100
101 #define CORE_PWRSAVE_DLL BIT(3)
102
103 #define DDR_CONFIG_POR_VAL 0x80040873
104
105
106 #define INVALID_TUNING_PHASE -1
107 #define SDHCI_MSM_MIN_CLOCK 400000
108 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
109
110 #define CDR_SELEXT_SHIFT 20
111 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
112 #define CMUX_SHIFT_PHASE_SHIFT 24
113 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
114
115 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
116
117 /* Timeout value to avoid infinite waiting for pwr_irq */
118 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
119
120 #define msm_host_readl(msm_host, host, offset) \
121 msm_host->var_ops->msm_readl_relaxed(host, offset)
122
123 #define msm_host_writel(msm_host, val, host, offset) \
124 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
125
126 /* CQHCI vendor specific registers */
127 #define CQHCI_VENDOR_CFG1 0xA00
128 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13)
129
130 struct sdhci_msm_offset {
131 u32 core_hc_mode;
132 u32 core_mci_data_cnt;
133 u32 core_mci_status;
134 u32 core_mci_fifo_cnt;
135 u32 core_mci_version;
136 u32 core_generics;
137 u32 core_testbus_config;
138 u32 core_testbus_sel2_bit;
139 u32 core_testbus_ena;
140 u32 core_testbus_sel2;
141 u32 core_pwrctl_status;
142 u32 core_pwrctl_mask;
143 u32 core_pwrctl_clear;
144 u32 core_pwrctl_ctl;
145 u32 core_sdcc_debug_reg;
146 u32 core_dll_config;
147 u32 core_dll_status;
148 u32 core_vendor_spec;
149 u32 core_vendor_spec_adma_err_addr0;
150 u32 core_vendor_spec_adma_err_addr1;
151 u32 core_vendor_spec_func2;
152 u32 core_vendor_spec_capabilities0;
153 u32 core_ddr_200_cfg;
154 u32 core_vendor_spec3;
155 u32 core_dll_config_2;
156 u32 core_dll_config_3;
157 u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
158 u32 core_ddr_config;
159 };
160
161 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
162 .core_mci_data_cnt = 0x35c,
163 .core_mci_status = 0x324,
164 .core_mci_fifo_cnt = 0x308,
165 .core_mci_version = 0x318,
166 .core_generics = 0x320,
167 .core_testbus_config = 0x32c,
168 .core_testbus_sel2_bit = 3,
169 .core_testbus_ena = (1 << 31),
170 .core_testbus_sel2 = (1 << 3),
171 .core_pwrctl_status = 0x240,
172 .core_pwrctl_mask = 0x244,
173 .core_pwrctl_clear = 0x248,
174 .core_pwrctl_ctl = 0x24c,
175 .core_sdcc_debug_reg = 0x358,
176 .core_dll_config = 0x200,
177 .core_dll_status = 0x208,
178 .core_vendor_spec = 0x20c,
179 .core_vendor_spec_adma_err_addr0 = 0x214,
180 .core_vendor_spec_adma_err_addr1 = 0x218,
181 .core_vendor_spec_func2 = 0x210,
182 .core_vendor_spec_capabilities0 = 0x21c,
183 .core_ddr_200_cfg = 0x224,
184 .core_vendor_spec3 = 0x250,
185 .core_dll_config_2 = 0x254,
186 .core_dll_config_3 = 0x258,
187 .core_ddr_config = 0x25c,
188 };
189
190 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
191 .core_hc_mode = 0x78,
192 .core_mci_data_cnt = 0x30,
193 .core_mci_status = 0x34,
194 .core_mci_fifo_cnt = 0x44,
195 .core_mci_version = 0x050,
196 .core_generics = 0x70,
197 .core_testbus_config = 0x0cc,
198 .core_testbus_sel2_bit = 4,
199 .core_testbus_ena = (1 << 3),
200 .core_testbus_sel2 = (1 << 4),
201 .core_pwrctl_status = 0xdc,
202 .core_pwrctl_mask = 0xe0,
203 .core_pwrctl_clear = 0xe4,
204 .core_pwrctl_ctl = 0xe8,
205 .core_sdcc_debug_reg = 0x124,
206 .core_dll_config = 0x100,
207 .core_dll_status = 0x108,
208 .core_vendor_spec = 0x10c,
209 .core_vendor_spec_adma_err_addr0 = 0x114,
210 .core_vendor_spec_adma_err_addr1 = 0x118,
211 .core_vendor_spec_func2 = 0x110,
212 .core_vendor_spec_capabilities0 = 0x11c,
213 .core_ddr_200_cfg = 0x184,
214 .core_vendor_spec3 = 0x1b0,
215 .core_dll_config_2 = 0x1b4,
216 .core_ddr_config_old = 0x1b8,
217 .core_ddr_config = 0x1bc,
218 };
219
220 struct sdhci_msm_variant_ops {
221 u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
222 void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
223 u32 offset);
224 };
225
226 /*
227 * From V5, register spaces have changed. Wrap this info in a structure
228 * and choose the data_structure based on version info mentioned in DT.
229 */
230 struct sdhci_msm_variant_info {
231 bool mci_removed;
232 bool restore_dll_config;
233 const struct sdhci_msm_variant_ops *var_ops;
234 const struct sdhci_msm_offset *offset;
235 };
236
237 struct sdhci_msm_host {
238 struct platform_device *pdev;
239 void __iomem *core_mem; /* MSM SDCC mapped address */
240 int pwr_irq; /* power irq */
241 struct clk *bus_clk; /* SDHC bus voter clock */
242 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
243 struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
244 unsigned long clk_rate;
245 struct mmc_host *mmc;
246 bool use_14lpp_dll_reset;
247 bool tuning_done;
248 bool calibration_done;
249 u8 saved_tuning_phase;
250 bool use_cdclp533;
251 u32 curr_pwr_state;
252 u32 curr_io_level;
253 wait_queue_head_t pwr_irq_wait;
254 bool pwr_irq_flag;
255 u32 caps_0;
256 bool mci_removed;
257 bool restore_dll_config;
258 const struct sdhci_msm_variant_ops *var_ops;
259 const struct sdhci_msm_offset *offset;
260 bool use_cdr;
261 u32 transfer_mode;
262 bool updated_ddr_cfg;
263 };
264
265 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
266 {
267 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
268 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
269
270 return msm_host->offset;
271 }
272
273 /*
274 * APIs to read/write to vendor specific registers which were there in the
275 * core_mem region before MCI was removed.
276 */
277 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
278 u32 offset)
279 {
280 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
281 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
282
283 return readl_relaxed(msm_host->core_mem + offset);
284 }
285
286 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
287 u32 offset)
288 {
289 return readl_relaxed(host->ioaddr + offset);
290 }
291
292 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
293 struct sdhci_host *host, u32 offset)
294 {
295 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
296 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
297
298 writel_relaxed(val, msm_host->core_mem + offset);
299 }
300
301 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
302 struct sdhci_host *host, u32 offset)
303 {
304 writel_relaxed(val, host->ioaddr + offset);
305 }
306
307 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
308 unsigned int clock)
309 {
310 struct mmc_ios ios = host->mmc->ios;
311 /*
312 * The SDHC requires internal clock frequency to be double the
313 * actual clock that will be set for DDR mode. The controller
314 * uses the faster clock(100/400MHz) for some of its parts and
315 * send the actual required clock (50/200MHz) to the card.
316 */
317 if (ios.timing == MMC_TIMING_UHS_DDR50 ||
318 ios.timing == MMC_TIMING_MMC_DDR52 ||
319 ios.timing == MMC_TIMING_MMC_HS400 ||
320 host->flags & SDHCI_HS400_TUNING)
321 clock *= 2;
322 return clock;
323 }
324
325 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
326 unsigned int clock)
327 {
328 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
329 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
330 struct mmc_ios curr_ios = host->mmc->ios;
331 struct clk *core_clk = msm_host->bulk_clks[0].clk;
332 int rc;
333
334 clock = msm_get_clock_rate_for_bus_mode(host, clock);
335 rc = clk_set_rate(core_clk, clock);
336 if (rc) {
337 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
338 mmc_hostname(host->mmc), clock,
339 curr_ios.timing);
340 return;
341 }
342 msm_host->clk_rate = clock;
343 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
344 mmc_hostname(host->mmc), clk_get_rate(core_clk),
345 curr_ios.timing);
346 }
347
348 /* Platform specific tuning */
349 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
350 {
351 u32 wait_cnt = 50;
352 u8 ck_out_en;
353 struct mmc_host *mmc = host->mmc;
354 const struct sdhci_msm_offset *msm_offset =
355 sdhci_priv_msm_offset(host);
356
357 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
358 ck_out_en = !!(readl_relaxed(host->ioaddr +
359 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
360
361 while (ck_out_en != poll) {
362 if (--wait_cnt == 0) {
363 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
364 mmc_hostname(mmc), poll);
365 return -ETIMEDOUT;
366 }
367 udelay(1);
368
369 ck_out_en = !!(readl_relaxed(host->ioaddr +
370 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
371 }
372
373 return 0;
374 }
375
376 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
377 {
378 int rc;
379 static const u8 grey_coded_phase_table[] = {
380 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
381 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
382 };
383 unsigned long flags;
384 u32 config;
385 struct mmc_host *mmc = host->mmc;
386 const struct sdhci_msm_offset *msm_offset =
387 sdhci_priv_msm_offset(host);
388
389 if (phase > 0xf)
390 return -EINVAL;
391
392 spin_lock_irqsave(&host->lock, flags);
393
394 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
395 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
396 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
397 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
398
399 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
400 rc = msm_dll_poll_ck_out_en(host, 0);
401 if (rc)
402 goto err_out;
403
404 /*
405 * Write the selected DLL clock output phase (0 ... 15)
406 * to CDR_SELEXT bit field of DLL_CONFIG register.
407 */
408 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
409 config &= ~CDR_SELEXT_MASK;
410 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
411 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
412
413 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
414 config |= CORE_CK_OUT_EN;
415 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
416
417 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
418 rc = msm_dll_poll_ck_out_en(host, 1);
419 if (rc)
420 goto err_out;
421
422 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
423 config |= CORE_CDR_EN;
424 config &= ~CORE_CDR_EXT_EN;
425 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
426 goto out;
427
428 err_out:
429 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
430 mmc_hostname(mmc), phase);
431 out:
432 spin_unlock_irqrestore(&host->lock, flags);
433 return rc;
434 }
435
436 /*
437 * Find out the greatest range of consecuitive selected
438 * DLL clock output phases that can be used as sampling
439 * setting for SD3.0 UHS-I card read operation (in SDR104
440 * timing mode) or for eMMC4.5 card read operation (in
441 * HS400/HS200 timing mode).
442 * Select the 3/4 of the range and configure the DLL with the
443 * selected DLL clock output phase.
444 */
445
446 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
447 u8 *phase_table, u8 total_phases)
448 {
449 int ret;
450 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
451 u8 phases_per_row[MAX_PHASES] = { 0 };
452 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
453 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
454 bool phase_0_found = false, phase_15_found = false;
455 struct mmc_host *mmc = host->mmc;
456
457 if (!total_phases || (total_phases > MAX_PHASES)) {
458 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
459 mmc_hostname(mmc), total_phases);
460 return -EINVAL;
461 }
462
463 for (cnt = 0; cnt < total_phases; cnt++) {
464 ranges[row_index][col_index] = phase_table[cnt];
465 phases_per_row[row_index] += 1;
466 col_index++;
467
468 if ((cnt + 1) == total_phases) {
469 continue;
470 /* check if next phase in phase_table is consecutive or not */
471 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
472 row_index++;
473 col_index = 0;
474 }
475 }
476
477 if (row_index >= MAX_PHASES)
478 return -EINVAL;
479
480 /* Check if phase-0 is present in first valid window? */
481 if (!ranges[0][0]) {
482 phase_0_found = true;
483 phase_0_raw_index = 0;
484 /* Check if cycle exist between 2 valid windows */
485 for (cnt = 1; cnt <= row_index; cnt++) {
486 if (phases_per_row[cnt]) {
487 for (i = 0; i < phases_per_row[cnt]; i++) {
488 if (ranges[cnt][i] == 15) {
489 phase_15_found = true;
490 phase_15_raw_index = cnt;
491 break;
492 }
493 }
494 }
495 }
496 }
497
498 /* If 2 valid windows form cycle then merge them as single window */
499 if (phase_0_found && phase_15_found) {
500 /* number of phases in raw where phase 0 is present */
501 u8 phases_0 = phases_per_row[phase_0_raw_index];
502 /* number of phases in raw where phase 15 is present */
503 u8 phases_15 = phases_per_row[phase_15_raw_index];
504
505 if (phases_0 + phases_15 >= MAX_PHASES)
506 /*
507 * If there are more than 1 phase windows then total
508 * number of phases in both the windows should not be
509 * more than or equal to MAX_PHASES.
510 */
511 return -EINVAL;
512
513 /* Merge 2 cyclic windows */
514 i = phases_15;
515 for (cnt = 0; cnt < phases_0; cnt++) {
516 ranges[phase_15_raw_index][i] =
517 ranges[phase_0_raw_index][cnt];
518 if (++i >= MAX_PHASES)
519 break;
520 }
521
522 phases_per_row[phase_0_raw_index] = 0;
523 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
524 }
525
526 for (cnt = 0; cnt <= row_index; cnt++) {
527 if (phases_per_row[cnt] > curr_max) {
528 curr_max = phases_per_row[cnt];
529 selected_row_index = cnt;
530 }
531 }
532
533 i = (curr_max * 3) / 4;
534 if (i)
535 i--;
536
537 ret = ranges[selected_row_index][i];
538
539 if (ret >= MAX_PHASES) {
540 ret = -EINVAL;
541 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
542 mmc_hostname(mmc), ret);
543 }
544
545 return ret;
546 }
547
548 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
549 {
550 u32 mclk_freq = 0, config;
551 const struct sdhci_msm_offset *msm_offset =
552 sdhci_priv_msm_offset(host);
553
554 /* Program the MCLK value to MCLK_FREQ bit field */
555 if (host->clock <= 112000000)
556 mclk_freq = 0;
557 else if (host->clock <= 125000000)
558 mclk_freq = 1;
559 else if (host->clock <= 137000000)
560 mclk_freq = 2;
561 else if (host->clock <= 150000000)
562 mclk_freq = 3;
563 else if (host->clock <= 162000000)
564 mclk_freq = 4;
565 else if (host->clock <= 175000000)
566 mclk_freq = 5;
567 else if (host->clock <= 187000000)
568 mclk_freq = 6;
569 else if (host->clock <= 200000000)
570 mclk_freq = 7;
571
572 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
573 config &= ~CMUX_SHIFT_PHASE_MASK;
574 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
575 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
576 }
577
578 /* Initialize the DLL (Programmable Delay Line) */
579 static int msm_init_cm_dll(struct sdhci_host *host)
580 {
581 struct mmc_host *mmc = host->mmc;
582 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
583 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
584 int wait_cnt = 50;
585 unsigned long flags, xo_clk = 0;
586 u32 config;
587 const struct sdhci_msm_offset *msm_offset =
588 msm_host->offset;
589
590 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
591 xo_clk = clk_get_rate(msm_host->xo_clk);
592
593 spin_lock_irqsave(&host->lock, flags);
594
595 /*
596 * Make sure that clock is always enabled when DLL
597 * tuning is in progress. Keeping PWRSAVE ON may
598 * turn off the clock.
599 */
600 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
601 config &= ~CORE_CLK_PWRSAVE;
602 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
603
604 if (msm_host->use_14lpp_dll_reset) {
605 config = readl_relaxed(host->ioaddr +
606 msm_offset->core_dll_config);
607 config &= ~CORE_CK_OUT_EN;
608 writel_relaxed(config, host->ioaddr +
609 msm_offset->core_dll_config);
610
611 config = readl_relaxed(host->ioaddr +
612 msm_offset->core_dll_config_2);
613 config |= CORE_DLL_CLOCK_DISABLE;
614 writel_relaxed(config, host->ioaddr +
615 msm_offset->core_dll_config_2);
616 }
617
618 config = readl_relaxed(host->ioaddr +
619 msm_offset->core_dll_config);
620 config |= CORE_DLL_RST;
621 writel_relaxed(config, host->ioaddr +
622 msm_offset->core_dll_config);
623
624 config = readl_relaxed(host->ioaddr +
625 msm_offset->core_dll_config);
626 config |= CORE_DLL_PDN;
627 writel_relaxed(config, host->ioaddr +
628 msm_offset->core_dll_config);
629 msm_cm_dll_set_freq(host);
630
631 if (msm_host->use_14lpp_dll_reset &&
632 !IS_ERR_OR_NULL(msm_host->xo_clk)) {
633 u32 mclk_freq = 0;
634
635 config = readl_relaxed(host->ioaddr +
636 msm_offset->core_dll_config_2);
637 config &= CORE_FLL_CYCLE_CNT;
638 if (config)
639 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
640 xo_clk);
641 else
642 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
643 xo_clk);
644
645 config = readl_relaxed(host->ioaddr +
646 msm_offset->core_dll_config_2);
647 config &= ~(0xFF << 10);
648 config |= mclk_freq << 10;
649
650 writel_relaxed(config, host->ioaddr +
651 msm_offset->core_dll_config_2);
652 /* wait for 5us before enabling DLL clock */
653 udelay(5);
654 }
655
656 config = readl_relaxed(host->ioaddr +
657 msm_offset->core_dll_config);
658 config &= ~CORE_DLL_RST;
659 writel_relaxed(config, host->ioaddr +
660 msm_offset->core_dll_config);
661
662 config = readl_relaxed(host->ioaddr +
663 msm_offset->core_dll_config);
664 config &= ~CORE_DLL_PDN;
665 writel_relaxed(config, host->ioaddr +
666 msm_offset->core_dll_config);
667
668 if (msm_host->use_14lpp_dll_reset) {
669 msm_cm_dll_set_freq(host);
670 config = readl_relaxed(host->ioaddr +
671 msm_offset->core_dll_config_2);
672 config &= ~CORE_DLL_CLOCK_DISABLE;
673 writel_relaxed(config, host->ioaddr +
674 msm_offset->core_dll_config_2);
675 }
676
677 config = readl_relaxed(host->ioaddr +
678 msm_offset->core_dll_config);
679 config |= CORE_DLL_EN;
680 writel_relaxed(config, host->ioaddr +
681 msm_offset->core_dll_config);
682
683 config = readl_relaxed(host->ioaddr +
684 msm_offset->core_dll_config);
685 config |= CORE_CK_OUT_EN;
686 writel_relaxed(config, host->ioaddr +
687 msm_offset->core_dll_config);
688
689 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
690 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
691 CORE_DLL_LOCK)) {
692 /* max. wait for 50us sec for LOCK bit to be set */
693 if (--wait_cnt == 0) {
694 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
695 mmc_hostname(mmc));
696 spin_unlock_irqrestore(&host->lock, flags);
697 return -ETIMEDOUT;
698 }
699 udelay(1);
700 }
701
702 spin_unlock_irqrestore(&host->lock, flags);
703 return 0;
704 }
705
706 static void msm_hc_select_default(struct sdhci_host *host)
707 {
708 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
709 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
710 u32 config;
711 const struct sdhci_msm_offset *msm_offset =
712 msm_host->offset;
713
714 if (!msm_host->use_cdclp533) {
715 config = readl_relaxed(host->ioaddr +
716 msm_offset->core_vendor_spec3);
717 config &= ~CORE_PWRSAVE_DLL;
718 writel_relaxed(config, host->ioaddr +
719 msm_offset->core_vendor_spec3);
720 }
721
722 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
723 config &= ~CORE_HC_MCLK_SEL_MASK;
724 config |= CORE_HC_MCLK_SEL_DFLT;
725 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
726
727 /*
728 * Disable HC_SELECT_IN to be able to use the UHS mode select
729 * configuration from Host Control2 register for all other
730 * modes.
731 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
732 * in VENDOR_SPEC_FUNC
733 */
734 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
735 config &= ~CORE_HC_SELECT_IN_EN;
736 config &= ~CORE_HC_SELECT_IN_MASK;
737 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
738
739 /*
740 * Make sure above writes impacting free running MCLK are completed
741 * before changing the clk_rate at GCC.
742 */
743 wmb();
744 }
745
746 static void msm_hc_select_hs400(struct sdhci_host *host)
747 {
748 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
749 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
750 struct mmc_ios ios = host->mmc->ios;
751 u32 config, dll_lock;
752 int rc;
753 const struct sdhci_msm_offset *msm_offset =
754 msm_host->offset;
755
756 /* Select the divided clock (free running MCLK/2) */
757 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
758 config &= ~CORE_HC_MCLK_SEL_MASK;
759 config |= CORE_HC_MCLK_SEL_HS400;
760
761 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
762 /*
763 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
764 * register
765 */
766 if ((msm_host->tuning_done || ios.enhanced_strobe) &&
767 !msm_host->calibration_done) {
768 config = readl_relaxed(host->ioaddr +
769 msm_offset->core_vendor_spec);
770 config |= CORE_HC_SELECT_IN_HS400;
771 config |= CORE_HC_SELECT_IN_EN;
772 writel_relaxed(config, host->ioaddr +
773 msm_offset->core_vendor_spec);
774 }
775 if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
776 /*
777 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
778 * core_dll_status to be set. This should get set
779 * within 15 us at 200 MHz.
780 */
781 rc = readl_relaxed_poll_timeout(host->ioaddr +
782 msm_offset->core_dll_status,
783 dll_lock,
784 (dll_lock &
785 (CORE_DLL_LOCK |
786 CORE_DDR_DLL_LOCK)), 10,
787 1000);
788 if (rc == -ETIMEDOUT)
789 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
790 mmc_hostname(host->mmc), dll_lock);
791 }
792 /*
793 * Make sure above writes impacting free running MCLK are completed
794 * before changing the clk_rate at GCC.
795 */
796 wmb();
797 }
798
799 /*
800 * sdhci_msm_hc_select_mode :- In general all timing modes are
801 * controlled via UHS mode select in Host Control2 register.
802 * eMMC specific HS200/HS400 doesn't have their respective modes
803 * defined here, hence we use these values.
804 *
805 * HS200 - SDR104 (Since they both are equivalent in functionality)
806 * HS400 - This involves multiple configurations
807 * Initially SDR104 - when tuning is required as HS200
808 * Then when switching to DDR @ 400MHz (HS400) we use
809 * the vendor specific HC_SELECT_IN to control the mode.
810 *
811 * In addition to controlling the modes we also need to select the
812 * correct input clock for DLL depending on the mode.
813 *
814 * HS400 - divided clock (free running MCLK/2)
815 * All other modes - default (free running MCLK)
816 */
817 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
818 {
819 struct mmc_ios ios = host->mmc->ios;
820
821 if (ios.timing == MMC_TIMING_MMC_HS400 ||
822 host->flags & SDHCI_HS400_TUNING)
823 msm_hc_select_hs400(host);
824 else
825 msm_hc_select_default(host);
826 }
827
828 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
829 {
830 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
831 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
832 u32 config, calib_done;
833 int ret;
834 const struct sdhci_msm_offset *msm_offset =
835 msm_host->offset;
836
837 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
838
839 /*
840 * Retuning in HS400 (DDR mode) will fail, just reset the
841 * tuning block and restore the saved tuning phase.
842 */
843 ret = msm_init_cm_dll(host);
844 if (ret)
845 goto out;
846
847 /* Set the selected phase in delay line hw block */
848 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
849 if (ret)
850 goto out;
851
852 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
853 config |= CORE_CMD_DAT_TRACK_SEL;
854 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
855
856 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
857 config &= ~CORE_CDC_T4_DLY_SEL;
858 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
859
860 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
861 config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
862 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
863
864 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
865 config |= CORE_CDC_SWITCH_RC_EN;
866 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
867
868 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
869 config &= ~CORE_START_CDC_TRAFFIC;
870 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
871
872 /* Perform CDC Register Initialization Sequence */
873
874 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
875 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
876 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
877 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
878 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
879 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
880 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
881 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
882 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
883
884 /* CDC HW Calibration */
885
886 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
887 config |= CORE_SW_TRIG_FULL_CALIB;
888 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
889
890 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
891 config &= ~CORE_SW_TRIG_FULL_CALIB;
892 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
893
894 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
895 config |= CORE_HW_AUTOCAL_ENA;
896 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
897
898 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
899 config |= CORE_TIMER_ENA;
900 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
901
902 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
903 calib_done,
904 (calib_done & CORE_CALIBRATION_DONE),
905 1, 50);
906
907 if (ret == -ETIMEDOUT) {
908 pr_err("%s: %s: CDC calibration was not completed\n",
909 mmc_hostname(host->mmc), __func__);
910 goto out;
911 }
912
913 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
914 & CORE_CDC_ERROR_CODE_MASK;
915 if (ret) {
916 pr_err("%s: %s: CDC error code %d\n",
917 mmc_hostname(host->mmc), __func__, ret);
918 ret = -EINVAL;
919 goto out;
920 }
921
922 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
923 config |= CORE_START_CDC_TRAFFIC;
924 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
925 out:
926 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
927 __func__, ret);
928 return ret;
929 }
930
931 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
932 {
933 struct mmc_host *mmc = host->mmc;
934 u32 dll_status, config, ddr_cfg_offset;
935 int ret;
936 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
937 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
938 const struct sdhci_msm_offset *msm_offset =
939 sdhci_priv_msm_offset(host);
940
941 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
942
943 /*
944 * Currently the core_ddr_config register defaults to desired
945 * configuration on reset. Currently reprogramming the power on
946 * reset (POR) value in case it might have been modified by
947 * bootloaders. In the future, if this changes, then the desired
948 * values will need to be programmed appropriately.
949 */
950 if (msm_host->updated_ddr_cfg)
951 ddr_cfg_offset = msm_offset->core_ddr_config;
952 else
953 ddr_cfg_offset = msm_offset->core_ddr_config_old;
954 writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + ddr_cfg_offset);
955
956 if (mmc->ios.enhanced_strobe) {
957 config = readl_relaxed(host->ioaddr +
958 msm_offset->core_ddr_200_cfg);
959 config |= CORE_CMDIN_RCLK_EN;
960 writel_relaxed(config, host->ioaddr +
961 msm_offset->core_ddr_200_cfg);
962 }
963
964 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
965 config |= CORE_DDR_CAL_EN;
966 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
967
968 ret = readl_relaxed_poll_timeout(host->ioaddr +
969 msm_offset->core_dll_status,
970 dll_status,
971 (dll_status & CORE_DDR_DLL_LOCK),
972 10, 1000);
973
974 if (ret == -ETIMEDOUT) {
975 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
976 mmc_hostname(host->mmc), __func__);
977 goto out;
978 }
979
980 /*
981 * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
982 * When MCLK is gated OFF, it is not gated for less than 0.5us
983 * and MCLK must be switched on for at-least 1us before DATA
984 * starts coming. Controllers with 14lpp and later tech DLL cannot
985 * guarantee above requirement. So PWRSAVE_DLL should not be
986 * turned on for host controllers using this DLL.
987 */
988 if (!msm_host->use_14lpp_dll_reset) {
989 config = readl_relaxed(host->ioaddr +
990 msm_offset->core_vendor_spec3);
991 config |= CORE_PWRSAVE_DLL;
992 writel_relaxed(config, host->ioaddr +
993 msm_offset->core_vendor_spec3);
994 }
995
996 /*
997 * Drain writebuffer to ensure above DLL calibration
998 * and PWRSAVE DLL is enabled.
999 */
1000 wmb();
1001 out:
1002 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1003 __func__, ret);
1004 return ret;
1005 }
1006
1007 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
1008 {
1009 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1010 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1011 struct mmc_host *mmc = host->mmc;
1012 int ret;
1013 u32 config;
1014 const struct sdhci_msm_offset *msm_offset =
1015 msm_host->offset;
1016
1017 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1018
1019 /*
1020 * Retuning in HS400 (DDR mode) will fail, just reset the
1021 * tuning block and restore the saved tuning phase.
1022 */
1023 ret = msm_init_cm_dll(host);
1024 if (ret)
1025 goto out;
1026
1027 if (!mmc->ios.enhanced_strobe) {
1028 /* Set the selected phase in delay line hw block */
1029 ret = msm_config_cm_dll_phase(host,
1030 msm_host->saved_tuning_phase);
1031 if (ret)
1032 goto out;
1033 config = readl_relaxed(host->ioaddr +
1034 msm_offset->core_dll_config);
1035 config |= CORE_CMD_DAT_TRACK_SEL;
1036 writel_relaxed(config, host->ioaddr +
1037 msm_offset->core_dll_config);
1038 }
1039
1040 if (msm_host->use_cdclp533)
1041 ret = sdhci_msm_cdclp533_calibration(host);
1042 else
1043 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1044 out:
1045 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1046 __func__, ret);
1047 return ret;
1048 }
1049
1050 static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
1051 {
1052 struct mmc_ios *ios = &host->mmc->ios;
1053
1054 /*
1055 * Tuning is required for SDR104, HS200 and HS400 cards and
1056 * if clock frequency is greater than 100MHz in these modes.
1057 */
1058 if (host->clock <= CORE_FREQ_100MHZ ||
1059 !(ios->timing == MMC_TIMING_MMC_HS400 ||
1060 ios->timing == MMC_TIMING_MMC_HS200 ||
1061 ios->timing == MMC_TIMING_UHS_SDR104) ||
1062 ios->enhanced_strobe)
1063 return false;
1064
1065 return true;
1066 }
1067
1068 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
1069 {
1070 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1071 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1072 int ret;
1073
1074 /*
1075 * SDR DLL comes into picture only for timing modes which needs
1076 * tuning.
1077 */
1078 if (!sdhci_msm_is_tuning_needed(host))
1079 return 0;
1080
1081 /* Reset the tuning block */
1082 ret = msm_init_cm_dll(host);
1083 if (ret)
1084 return ret;
1085
1086 /* Restore the tuning block */
1087 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1088
1089 return ret;
1090 }
1091
1092 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1093 {
1094 const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1095 u32 config, oldconfig = readl_relaxed(host->ioaddr +
1096 msm_offset->core_dll_config);
1097
1098 config = oldconfig;
1099 if (enable) {
1100 config |= CORE_CDR_EN;
1101 config &= ~CORE_CDR_EXT_EN;
1102 } else {
1103 config &= ~CORE_CDR_EN;
1104 config |= CORE_CDR_EXT_EN;
1105 }
1106
1107 if (config != oldconfig) {
1108 writel_relaxed(config, host->ioaddr +
1109 msm_offset->core_dll_config);
1110 }
1111 }
1112
1113 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1114 {
1115 struct sdhci_host *host = mmc_priv(mmc);
1116 int tuning_seq_cnt = 3;
1117 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1118 int rc;
1119 struct mmc_ios ios = host->mmc->ios;
1120 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1121 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1122
1123 if (!sdhci_msm_is_tuning_needed(host)) {
1124 msm_host->use_cdr = false;
1125 sdhci_msm_set_cdr(host, false);
1126 return 0;
1127 }
1128
1129 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1130 msm_host->use_cdr = true;
1131
1132 /*
1133 * For HS400 tuning in HS200 timing requires:
1134 * - select MCLK/2 in VENDOR_SPEC
1135 * - program MCLK to 400MHz (or nearest supported) in GCC
1136 */
1137 if (host->flags & SDHCI_HS400_TUNING) {
1138 sdhci_msm_hc_select_mode(host);
1139 msm_set_clock_rate_for_bus_mode(host, ios.clock);
1140 host->flags &= ~SDHCI_HS400_TUNING;
1141 }
1142
1143 retry:
1144 /* First of all reset the tuning block */
1145 rc = msm_init_cm_dll(host);
1146 if (rc)
1147 return rc;
1148
1149 phase = 0;
1150 do {
1151 /* Set the phase in delay line hw block */
1152 rc = msm_config_cm_dll_phase(host, phase);
1153 if (rc)
1154 return rc;
1155
1156 rc = mmc_send_tuning(mmc, opcode, NULL);
1157 if (!rc) {
1158 /* Tuning is successful at this tuning point */
1159 tuned_phases[tuned_phase_cnt++] = phase;
1160 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1161 mmc_hostname(mmc), phase);
1162 }
1163 } while (++phase < ARRAY_SIZE(tuned_phases));
1164
1165 if (tuned_phase_cnt) {
1166 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1167 tuned_phase_cnt);
1168 if (rc < 0)
1169 return rc;
1170 else
1171 phase = rc;
1172
1173 /*
1174 * Finally set the selected phase in delay
1175 * line hw block.
1176 */
1177 rc = msm_config_cm_dll_phase(host, phase);
1178 if (rc)
1179 return rc;
1180 msm_host->saved_tuning_phase = phase;
1181 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1182 mmc_hostname(mmc), phase);
1183 } else {
1184 if (--tuning_seq_cnt)
1185 goto retry;
1186 /* Tuning failed */
1187 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1188 mmc_hostname(mmc));
1189 rc = -EIO;
1190 }
1191
1192 if (!rc)
1193 msm_host->tuning_done = true;
1194 return rc;
1195 }
1196
1197 /*
1198 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1199 * This needs to be done for both tuning and enhanced_strobe mode.
1200 * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1201 * fixed feedback clock is used.
1202 */
1203 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1204 {
1205 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1206 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1207 int ret;
1208
1209 if (host->clock > CORE_FREQ_100MHZ &&
1210 (msm_host->tuning_done || ios->enhanced_strobe) &&
1211 !msm_host->calibration_done) {
1212 ret = sdhci_msm_hs400_dll_calibration(host);
1213 if (!ret)
1214 msm_host->calibration_done = true;
1215 else
1216 pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1217 mmc_hostname(host->mmc), ret);
1218 }
1219 }
1220
1221 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1222 unsigned int uhs)
1223 {
1224 struct mmc_host *mmc = host->mmc;
1225 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1226 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1227 u16 ctrl_2;
1228 u32 config;
1229 const struct sdhci_msm_offset *msm_offset =
1230 msm_host->offset;
1231
1232 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1233 /* Select Bus Speed Mode for host */
1234 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1235 switch (uhs) {
1236 case MMC_TIMING_UHS_SDR12:
1237 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1238 break;
1239 case MMC_TIMING_UHS_SDR25:
1240 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1241 break;
1242 case MMC_TIMING_UHS_SDR50:
1243 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1244 break;
1245 case MMC_TIMING_MMC_HS400:
1246 case MMC_TIMING_MMC_HS200:
1247 case MMC_TIMING_UHS_SDR104:
1248 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1249 break;
1250 case MMC_TIMING_UHS_DDR50:
1251 case MMC_TIMING_MMC_DDR52:
1252 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1253 break;
1254 }
1255
1256 /*
1257 * When clock frequency is less than 100MHz, the feedback clock must be
1258 * provided and DLL must not be used so that tuning can be skipped. To
1259 * provide feedback clock, the mode selection can be any value less
1260 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1261 */
1262 if (host->clock <= CORE_FREQ_100MHZ) {
1263 if (uhs == MMC_TIMING_MMC_HS400 ||
1264 uhs == MMC_TIMING_MMC_HS200 ||
1265 uhs == MMC_TIMING_UHS_SDR104)
1266 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1267 /*
1268 * DLL is not required for clock <= 100MHz
1269 * Thus, make sure DLL it is disabled when not required
1270 */
1271 config = readl_relaxed(host->ioaddr +
1272 msm_offset->core_dll_config);
1273 config |= CORE_DLL_RST;
1274 writel_relaxed(config, host->ioaddr +
1275 msm_offset->core_dll_config);
1276
1277 config = readl_relaxed(host->ioaddr +
1278 msm_offset->core_dll_config);
1279 config |= CORE_DLL_PDN;
1280 writel_relaxed(config, host->ioaddr +
1281 msm_offset->core_dll_config);
1282
1283 /*
1284 * The DLL needs to be restored and CDCLP533 recalibrated
1285 * when the clock frequency is set back to 400MHz.
1286 */
1287 msm_host->calibration_done = false;
1288 }
1289
1290 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1291 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1292 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1293
1294 if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1295 sdhci_msm_hs400(host, &mmc->ios);
1296 }
1297
1298 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1299 {
1300 init_waitqueue_head(&msm_host->pwr_irq_wait);
1301 }
1302
1303 static inline void sdhci_msm_complete_pwr_irq_wait(
1304 struct sdhci_msm_host *msm_host)
1305 {
1306 wake_up(&msm_host->pwr_irq_wait);
1307 }
1308
1309 /*
1310 * sdhci_msm_check_power_status API should be called when registers writes
1311 * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1312 * To what state the register writes will change the IO lines should be passed
1313 * as the argument req_type. This API will check whether the IO line's state
1314 * is already the expected state and will wait for power irq only if
1315 * power irq is expected to be trigerred based on the current IO line state
1316 * and expected IO line state.
1317 */
1318 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1319 {
1320 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1321 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1322 bool done = false;
1323 u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1324 const struct sdhci_msm_offset *msm_offset =
1325 msm_host->offset;
1326
1327 pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1328 mmc_hostname(host->mmc), __func__, req_type,
1329 msm_host->curr_pwr_state, msm_host->curr_io_level);
1330
1331 /*
1332 * The power interrupt will not be generated for signal voltage
1333 * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1334 * Since sdhci-msm-v5, this bit has been removed and SW must consider
1335 * it as always set.
1336 */
1337 if (!msm_host->mci_removed)
1338 val = msm_host_readl(msm_host, host,
1339 msm_offset->core_generics);
1340 if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1341 !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1342 return;
1343 }
1344
1345 /*
1346 * The IRQ for request type IO High/LOW will be generated when -
1347 * there is a state change in 1.8V enable bit (bit 3) of
1348 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1349 * which indicates 3.3V IO voltage. So, when MMC core layer tries
1350 * to set it to 3.3V before card detection happens, the
1351 * IRQ doesn't get triggered as there is no state change in this bit.
1352 * The driver already handles this case by changing the IO voltage
1353 * level to high as part of controller power up sequence. Hence, check
1354 * for host->pwr to handle a case where IO voltage high request is
1355 * issued even before controller power up.
1356 */
1357 if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1358 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1359 mmc_hostname(host->mmc), req_type);
1360 return;
1361 }
1362 if ((req_type & msm_host->curr_pwr_state) ||
1363 (req_type & msm_host->curr_io_level))
1364 done = true;
1365 /*
1366 * This is needed here to handle cases where register writes will
1367 * not change the current bus state or io level of the controller.
1368 * In this case, no power irq will be triggerred and we should
1369 * not wait.
1370 */
1371 if (!done) {
1372 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1373 msm_host->pwr_irq_flag,
1374 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1375 dev_warn(&msm_host->pdev->dev,
1376 "%s: pwr_irq for req: (%d) timed out\n",
1377 mmc_hostname(host->mmc), req_type);
1378 }
1379 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1380 __func__, req_type);
1381 }
1382
1383 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1384 {
1385 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1386 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1387 const struct sdhci_msm_offset *msm_offset =
1388 msm_host->offset;
1389
1390 pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1391 mmc_hostname(host->mmc),
1392 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1393 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1394 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1395 }
1396
1397 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1398 {
1399 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1400 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1401 u32 irq_status, irq_ack = 0;
1402 int retry = 10;
1403 u32 pwr_state = 0, io_level = 0;
1404 u32 config;
1405 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1406
1407 irq_status = msm_host_readl(msm_host, host,
1408 msm_offset->core_pwrctl_status);
1409 irq_status &= INT_MASK;
1410
1411 msm_host_writel(msm_host, irq_status, host,
1412 msm_offset->core_pwrctl_clear);
1413
1414 /*
1415 * There is a rare HW scenario where the first clear pulse could be
1416 * lost when actual reset and clear/read of status register is
1417 * happening at a time. Hence, retry for at least 10 times to make
1418 * sure status register is cleared. Otherwise, this will result in
1419 * a spurious power IRQ resulting in system instability.
1420 */
1421 while (irq_status & msm_host_readl(msm_host, host,
1422 msm_offset->core_pwrctl_status)) {
1423 if (retry == 0) {
1424 pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1425 mmc_hostname(host->mmc), irq_status);
1426 sdhci_msm_dump_pwr_ctrl_regs(host);
1427 WARN_ON(1);
1428 break;
1429 }
1430 msm_host_writel(msm_host, irq_status, host,
1431 msm_offset->core_pwrctl_clear);
1432 retry--;
1433 udelay(10);
1434 }
1435
1436 /* Handle BUS ON/OFF*/
1437 if (irq_status & CORE_PWRCTL_BUS_ON) {
1438 pwr_state = REQ_BUS_ON;
1439 io_level = REQ_IO_HIGH;
1440 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1441 }
1442 if (irq_status & CORE_PWRCTL_BUS_OFF) {
1443 pwr_state = REQ_BUS_OFF;
1444 io_level = REQ_IO_LOW;
1445 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1446 }
1447 /* Handle IO LOW/HIGH */
1448 if (irq_status & CORE_PWRCTL_IO_LOW) {
1449 io_level = REQ_IO_LOW;
1450 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1451 }
1452 if (irq_status & CORE_PWRCTL_IO_HIGH) {
1453 io_level = REQ_IO_HIGH;
1454 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1455 }
1456
1457 /*
1458 * The driver has to acknowledge the interrupt, switch voltages and
1459 * report back if it succeded or not to this register. The voltage
1460 * switches are handled by the sdhci core, so just report success.
1461 */
1462 msm_host_writel(msm_host, irq_ack, host,
1463 msm_offset->core_pwrctl_ctl);
1464
1465 /*
1466 * If we don't have info regarding the voltage levels supported by
1467 * regulators, don't change the IO PAD PWR SWITCH.
1468 */
1469 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1470 u32 new_config;
1471 /*
1472 * We should unset IO PAD PWR switch only if the register write
1473 * can set IO lines high and the regulator also switches to 3 V.
1474 * Else, we should keep the IO PAD PWR switch set.
1475 * This is applicable to certain targets where eMMC vccq supply
1476 * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1477 * IO PAD PWR switch must be kept set to reflect actual
1478 * regulator voltage. This way, during initialization of
1479 * controllers with only 1.8V, we will set the IO PAD bit
1480 * without waiting for a REQ_IO_LOW.
1481 */
1482 config = readl_relaxed(host->ioaddr +
1483 msm_offset->core_vendor_spec);
1484 new_config = config;
1485
1486 if ((io_level & REQ_IO_HIGH) &&
1487 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1488 new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1489 else if ((io_level & REQ_IO_LOW) ||
1490 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1491 new_config |= CORE_IO_PAD_PWR_SWITCH;
1492
1493 if (config ^ new_config)
1494 writel_relaxed(new_config, host->ioaddr +
1495 msm_offset->core_vendor_spec);
1496 }
1497
1498 if (pwr_state)
1499 msm_host->curr_pwr_state = pwr_state;
1500 if (io_level)
1501 msm_host->curr_io_level = io_level;
1502
1503 pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1504 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1505 irq_ack);
1506 }
1507
1508 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1509 {
1510 struct sdhci_host *host = (struct sdhci_host *)data;
1511 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1512 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1513
1514 sdhci_msm_handle_pwr_irq(host, irq);
1515 msm_host->pwr_irq_flag = 1;
1516 sdhci_msm_complete_pwr_irq_wait(msm_host);
1517
1518
1519 return IRQ_HANDLED;
1520 }
1521
1522 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1523 {
1524 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1525 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1526 struct clk *core_clk = msm_host->bulk_clks[0].clk;
1527
1528 return clk_round_rate(core_clk, ULONG_MAX);
1529 }
1530
1531 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1532 {
1533 return SDHCI_MSM_MIN_CLOCK;
1534 }
1535
1536 /**
1537 * __sdhci_msm_set_clock - sdhci_msm clock control.
1538 *
1539 * Description:
1540 * MSM controller does not use internal divider and
1541 * instead directly control the GCC clock as per
1542 * HW recommendation.
1543 **/
1544 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1545 {
1546 u16 clk;
1547 /*
1548 * Keep actual_clock as zero -
1549 * - since there is no divider used so no need of having actual_clock.
1550 * - MSM controller uses SDCLK for data timeout calculation. If
1551 * actual_clock is zero, host->clock is taken for calculation.
1552 */
1553 host->mmc->actual_clock = 0;
1554
1555 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1556
1557 if (clock == 0)
1558 return;
1559
1560 /*
1561 * MSM controller do not use clock divider.
1562 * Thus read SDHCI_CLOCK_CONTROL and only enable
1563 * clock with no divider value programmed.
1564 */
1565 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1566 sdhci_enable_clk(host, clk);
1567 }
1568
1569 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1570 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1571 {
1572 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1573 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1574
1575 if (!clock) {
1576 msm_host->clk_rate = clock;
1577 goto out;
1578 }
1579
1580 sdhci_msm_hc_select_mode(host);
1581
1582 msm_set_clock_rate_for_bus_mode(host, clock);
1583 out:
1584 __sdhci_msm_set_clock(host, clock);
1585 }
1586
1587 /*****************************************************************************\
1588 * *
1589 * MSM Command Queue Engine (CQE) *
1590 * *
1591 \*****************************************************************************/
1592
1593 static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
1594 {
1595 int cmd_error = 0;
1596 int data_error = 0;
1597
1598 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1599 return intmask;
1600
1601 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1602 return 0;
1603 }
1604
1605 static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
1606 {
1607 struct sdhci_host *host = mmc_priv(mmc);
1608 unsigned long flags;
1609 u32 ctrl;
1610
1611 /*
1612 * When CQE is halted, the legacy SDHCI path operates only
1613 * on 16-byte descriptors in 64bit mode.
1614 */
1615 if (host->flags & SDHCI_USE_64_BIT_DMA)
1616 host->desc_sz = 16;
1617
1618 spin_lock_irqsave(&host->lock, flags);
1619
1620 /*
1621 * During CQE command transfers, command complete bit gets latched.
1622 * So s/w should clear command complete interrupt status when CQE is
1623 * either halted or disabled. Otherwise unexpected SDCHI legacy
1624 * interrupt gets triggered when CQE is halted/disabled.
1625 */
1626 ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
1627 ctrl |= SDHCI_INT_RESPONSE;
1628 sdhci_writel(host, ctrl, SDHCI_INT_ENABLE);
1629 sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
1630
1631 spin_unlock_irqrestore(&host->lock, flags);
1632
1633 sdhci_cqe_disable(mmc, recovery);
1634 }
1635
1636 static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
1637 .enable = sdhci_cqe_enable,
1638 .disable = sdhci_msm_cqe_disable,
1639 };
1640
1641 static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
1642 struct platform_device *pdev)
1643 {
1644 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1645 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1646 struct cqhci_host *cq_host;
1647 bool dma64;
1648 u32 cqcfg;
1649 int ret;
1650
1651 /*
1652 * When CQE is halted, SDHC operates only on 16byte ADMA descriptors.
1653 * So ensure ADMA table is allocated for 16byte descriptors.
1654 */
1655 if (host->caps & SDHCI_CAN_64BIT)
1656 host->alloc_desc_sz = 16;
1657
1658 ret = sdhci_setup_host(host);
1659 if (ret)
1660 return ret;
1661
1662 cq_host = cqhci_pltfm_init(pdev);
1663 if (IS_ERR(cq_host)) {
1664 ret = PTR_ERR(cq_host);
1665 dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret);
1666 goto cleanup;
1667 }
1668
1669 msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1670 cq_host->ops = &sdhci_msm_cqhci_ops;
1671
1672 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1673
1674 ret = cqhci_init(cq_host, host->mmc, dma64);
1675 if (ret) {
1676 dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",
1677 mmc_hostname(host->mmc), ret);
1678 goto cleanup;
1679 }
1680
1681 /* Disable cqe reset due to cqe enable signal */
1682 cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1);
1683 cqcfg |= CQHCI_VENDOR_DIS_RST_ON_CQ_EN;
1684 cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1);
1685
1686 /*
1687 * SDHC expects 12byte ADMA descriptors till CQE is enabled.
1688 * So limit desc_sz to 12 so that the data commands that are sent
1689 * during card initialization (before CQE gets enabled) would
1690 * get executed without any issues.
1691 */
1692 if (host->flags & SDHCI_USE_64_BIT_DMA)
1693 host->desc_sz = 12;
1694
1695 ret = __sdhci_add_host(host);
1696 if (ret)
1697 goto cleanup;
1698
1699 dev_info(&pdev->dev, "%s: CQE init: success\n",
1700 mmc_hostname(host->mmc));
1701 return ret;
1702
1703 cleanup:
1704 sdhci_cleanup_host(host);
1705 return ret;
1706 }
1707
1708 /*
1709 * Platform specific register write functions. This is so that, if any
1710 * register write needs to be followed up by platform specific actions,
1711 * they can be added here. These functions can go to sleep when writes
1712 * to certain registers are done.
1713 * These functions are relying on sdhci_set_ios not using spinlock.
1714 */
1715 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
1716 {
1717 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1718 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1719 u32 req_type = 0;
1720
1721 switch (reg) {
1722 case SDHCI_HOST_CONTROL2:
1723 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
1724 REQ_IO_HIGH;
1725 break;
1726 case SDHCI_SOFTWARE_RESET:
1727 if (host->pwr && (val & SDHCI_RESET_ALL))
1728 req_type = REQ_BUS_OFF;
1729 break;
1730 case SDHCI_POWER_CONTROL:
1731 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
1732 break;
1733 case SDHCI_TRANSFER_MODE:
1734 msm_host->transfer_mode = val;
1735 break;
1736 case SDHCI_COMMAND:
1737 if (!msm_host->use_cdr)
1738 break;
1739 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
1740 SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 &&
1741 SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK)
1742 sdhci_msm_set_cdr(host, true);
1743 else
1744 sdhci_msm_set_cdr(host, false);
1745 break;
1746 }
1747
1748 if (req_type) {
1749 msm_host->pwr_irq_flag = 0;
1750 /*
1751 * Since this register write may trigger a power irq, ensure
1752 * all previous register writes are complete by this point.
1753 */
1754 mb();
1755 }
1756 return req_type;
1757 }
1758
1759 /* This function may sleep*/
1760 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
1761 {
1762 u32 req_type = 0;
1763
1764 req_type = __sdhci_msm_check_write(host, val, reg);
1765 writew_relaxed(val, host->ioaddr + reg);
1766
1767 if (req_type)
1768 sdhci_msm_check_power_status(host, req_type);
1769 }
1770
1771 /* This function may sleep*/
1772 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
1773 {
1774 u32 req_type = 0;
1775
1776 req_type = __sdhci_msm_check_write(host, val, reg);
1777
1778 writeb_relaxed(val, host->ioaddr + reg);
1779
1780 if (req_type)
1781 sdhci_msm_check_power_status(host, req_type);
1782 }
1783
1784 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
1785 {
1786 struct mmc_host *mmc = msm_host->mmc;
1787 struct regulator *supply = mmc->supply.vqmmc;
1788 u32 caps = 0, config;
1789 struct sdhci_host *host = mmc_priv(mmc);
1790 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1791
1792 if (!IS_ERR(mmc->supply.vqmmc)) {
1793 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
1794 caps |= CORE_1_8V_SUPPORT;
1795 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
1796 caps |= CORE_3_0V_SUPPORT;
1797
1798 if (!caps)
1799 pr_warn("%s: 1.8/3V not supported for vqmmc\n",
1800 mmc_hostname(mmc));
1801 }
1802
1803 if (caps) {
1804 /*
1805 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
1806 * bit can be used as required later on.
1807 */
1808 u32 io_level = msm_host->curr_io_level;
1809
1810 config = readl_relaxed(host->ioaddr +
1811 msm_offset->core_vendor_spec);
1812 config |= CORE_IO_PAD_PWR_SWITCH_EN;
1813
1814 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
1815 config &= ~CORE_IO_PAD_PWR_SWITCH;
1816 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
1817 config |= CORE_IO_PAD_PWR_SWITCH;
1818
1819 writel_relaxed(config,
1820 host->ioaddr + msm_offset->core_vendor_spec);
1821 }
1822 msm_host->caps_0 |= caps;
1823 pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
1824 }
1825
1826 static void sdhci_msm_reset(struct sdhci_host *host, u8 mask)
1827 {
1828 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL))
1829 cqhci_deactivate(host->mmc);
1830 sdhci_reset(host, mask);
1831 }
1832
1833 static const struct sdhci_msm_variant_ops mci_var_ops = {
1834 .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
1835 .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
1836 };
1837
1838 static const struct sdhci_msm_variant_ops v5_var_ops = {
1839 .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
1840 .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
1841 };
1842
1843 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
1844 .var_ops = &mci_var_ops,
1845 .offset = &sdhci_msm_mci_offset,
1846 };
1847
1848 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
1849 .mci_removed = true,
1850 .var_ops = &v5_var_ops,
1851 .offset = &sdhci_msm_v5_offset,
1852 };
1853
1854 static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
1855 .mci_removed = true,
1856 .restore_dll_config = true,
1857 .var_ops = &v5_var_ops,
1858 .offset = &sdhci_msm_v5_offset,
1859 };
1860
1861 static const struct of_device_id sdhci_msm_dt_match[] = {
1862 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
1863 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
1864 {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
1865 {},
1866 };
1867
1868 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1869
1870 static const struct sdhci_ops sdhci_msm_ops = {
1871 .reset = sdhci_msm_reset,
1872 .set_clock = sdhci_msm_set_clock,
1873 .get_min_clock = sdhci_msm_get_min_clock,
1874 .get_max_clock = sdhci_msm_get_max_clock,
1875 .set_bus_width = sdhci_set_bus_width,
1876 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1877 .write_w = sdhci_msm_writew,
1878 .write_b = sdhci_msm_writeb,
1879 .irq = sdhci_msm_cqe_irq,
1880 };
1881
1882 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1883 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1884 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1885 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1886 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1887 .ops = &sdhci_msm_ops,
1888 };
1889
1890 static int sdhci_msm_probe(struct platform_device *pdev)
1891 {
1892 struct sdhci_host *host;
1893 struct sdhci_pltfm_host *pltfm_host;
1894 struct sdhci_msm_host *msm_host;
1895 struct clk *clk;
1896 int ret;
1897 u16 host_version, core_minor;
1898 u32 core_version, config;
1899 u8 core_major;
1900 const struct sdhci_msm_offset *msm_offset;
1901 const struct sdhci_msm_variant_info *var_info;
1902 struct device_node *node = pdev->dev.of_node;
1903
1904 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1905 if (IS_ERR(host))
1906 return PTR_ERR(host);
1907
1908 host->sdma_boundary = 0;
1909 pltfm_host = sdhci_priv(host);
1910 msm_host = sdhci_pltfm_priv(pltfm_host);
1911 msm_host->mmc = host->mmc;
1912 msm_host->pdev = pdev;
1913
1914 ret = mmc_of_parse(host->mmc);
1915 if (ret)
1916 goto pltfm_free;
1917
1918 /*
1919 * Based on the compatible string, load the required msm host info from
1920 * the data associated with the version info.
1921 */
1922 var_info = of_device_get_match_data(&pdev->dev);
1923
1924 msm_host->mci_removed = var_info->mci_removed;
1925 msm_host->restore_dll_config = var_info->restore_dll_config;
1926 msm_host->var_ops = var_info->var_ops;
1927 msm_host->offset = var_info->offset;
1928
1929 msm_offset = msm_host->offset;
1930
1931 sdhci_get_of_property(pdev);
1932
1933 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1934
1935 /* Setup SDCC bus voter clock. */
1936 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1937 if (!IS_ERR(msm_host->bus_clk)) {
1938 /* Vote for max. clk rate for max. performance */
1939 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1940 if (ret)
1941 goto pltfm_free;
1942 ret = clk_prepare_enable(msm_host->bus_clk);
1943 if (ret)
1944 goto pltfm_free;
1945 }
1946
1947 /* Setup main peripheral bus clock */
1948 clk = devm_clk_get(&pdev->dev, "iface");
1949 if (IS_ERR(clk)) {
1950 ret = PTR_ERR(clk);
1951 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1952 goto bus_clk_disable;
1953 }
1954 msm_host->bulk_clks[1].clk = clk;
1955
1956 /* Setup SDC MMC clock */
1957 clk = devm_clk_get(&pdev->dev, "core");
1958 if (IS_ERR(clk)) {
1959 ret = PTR_ERR(clk);
1960 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1961 goto bus_clk_disable;
1962 }
1963 msm_host->bulk_clks[0].clk = clk;
1964
1965 /* Vote for maximum clock rate for maximum performance */
1966 ret = clk_set_rate(clk, INT_MAX);
1967 if (ret)
1968 dev_warn(&pdev->dev, "core clock boost failed\n");
1969
1970 clk = devm_clk_get(&pdev->dev, "cal");
1971 if (IS_ERR(clk))
1972 clk = NULL;
1973 msm_host->bulk_clks[2].clk = clk;
1974
1975 clk = devm_clk_get(&pdev->dev, "sleep");
1976 if (IS_ERR(clk))
1977 clk = NULL;
1978 msm_host->bulk_clks[3].clk = clk;
1979
1980 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1981 msm_host->bulk_clks);
1982 if (ret)
1983 goto bus_clk_disable;
1984
1985 /*
1986 * xo clock is needed for FLL feature of cm_dll.
1987 * In case if xo clock is not mentioned in DT, warn and proceed.
1988 */
1989 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1990 if (IS_ERR(msm_host->xo_clk)) {
1991 ret = PTR_ERR(msm_host->xo_clk);
1992 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1993 }
1994
1995 if (!msm_host->mci_removed) {
1996 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1);
1997 if (IS_ERR(msm_host->core_mem)) {
1998 ret = PTR_ERR(msm_host->core_mem);
1999 goto clk_disable;
2000 }
2001 }
2002
2003 /* Reset the vendor spec register to power on reset state */
2004 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
2005 host->ioaddr + msm_offset->core_vendor_spec);
2006
2007 if (!msm_host->mci_removed) {
2008 /* Set HC_MODE_EN bit in HC_MODE register */
2009 msm_host_writel(msm_host, HC_MODE_EN, host,
2010 msm_offset->core_hc_mode);
2011 config = msm_host_readl(msm_host, host,
2012 msm_offset->core_hc_mode);
2013 config |= FF_CLK_SW_RST_DIS;
2014 msm_host_writel(msm_host, config, host,
2015 msm_offset->core_hc_mode);
2016 }
2017
2018 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
2019 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
2020 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
2021 SDHCI_VENDOR_VER_SHIFT));
2022
2023 core_version = msm_host_readl(msm_host, host,
2024 msm_offset->core_mci_version);
2025 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
2026 CORE_VERSION_MAJOR_SHIFT;
2027 core_minor = core_version & CORE_VERSION_MINOR_MASK;
2028 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
2029 core_version, core_major, core_minor);
2030
2031 if (core_major == 1 && core_minor >= 0x42)
2032 msm_host->use_14lpp_dll_reset = true;
2033
2034 /*
2035 * SDCC 5 controller with major version 1, minor version 0x34 and later
2036 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
2037 */
2038 if (core_major == 1 && core_minor < 0x34)
2039 msm_host->use_cdclp533 = true;
2040
2041 /*
2042 * Support for some capabilities is not advertised by newer
2043 * controller versions and must be explicitly enabled.
2044 */
2045 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
2046 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
2047 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
2048 writel_relaxed(config, host->ioaddr +
2049 msm_offset->core_vendor_spec_capabilities0);
2050 }
2051
2052 if (core_major == 1 && core_minor >= 0x49)
2053 msm_host->updated_ddr_cfg = true;
2054
2055 /*
2056 * Power on reset state may trigger power irq if previous status of
2057 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
2058 * interrupt in GIC, any pending power irq interrupt should be
2059 * acknowledged. Otherwise power irq interrupt handler would be
2060 * fired prematurely.
2061 */
2062 sdhci_msm_handle_pwr_irq(host, 0);
2063
2064 /*
2065 * Ensure that above writes are propogated before interrupt enablement
2066 * in GIC.
2067 */
2068 mb();
2069
2070 /* Setup IRQ for handling power/voltage tasks with PMIC */
2071 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
2072 if (msm_host->pwr_irq < 0) {
2073 ret = msm_host->pwr_irq;
2074 goto clk_disable;
2075 }
2076
2077 sdhci_msm_init_pwr_irq_wait(msm_host);
2078 /* Enable pwr irq interrupts */
2079 msm_host_writel(msm_host, INT_MASK, host,
2080 msm_offset->core_pwrctl_mask);
2081
2082 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
2083 sdhci_msm_pwr_irq, IRQF_ONESHOT,
2084 dev_name(&pdev->dev), host);
2085 if (ret) {
2086 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
2087 goto clk_disable;
2088 }
2089
2090 pm_runtime_get_noresume(&pdev->dev);
2091 pm_runtime_set_active(&pdev->dev);
2092 pm_runtime_enable(&pdev->dev);
2093 pm_runtime_set_autosuspend_delay(&pdev->dev,
2094 MSM_MMC_AUTOSUSPEND_DELAY_MS);
2095 pm_runtime_use_autosuspend(&pdev->dev);
2096
2097 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
2098 if (of_property_read_bool(node, "supports-cqe"))
2099 ret = sdhci_msm_cqe_add_host(host, pdev);
2100 else
2101 ret = sdhci_add_host(host);
2102 if (ret)
2103 goto pm_runtime_disable;
2104 sdhci_msm_set_regulator_caps(msm_host);
2105
2106 pm_runtime_mark_last_busy(&pdev->dev);
2107 pm_runtime_put_autosuspend(&pdev->dev);
2108
2109 return 0;
2110
2111 pm_runtime_disable:
2112 pm_runtime_disable(&pdev->dev);
2113 pm_runtime_set_suspended(&pdev->dev);
2114 pm_runtime_put_noidle(&pdev->dev);
2115 clk_disable:
2116 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2117 msm_host->bulk_clks);
2118 bus_clk_disable:
2119 if (!IS_ERR(msm_host->bus_clk))
2120 clk_disable_unprepare(msm_host->bus_clk);
2121 pltfm_free:
2122 sdhci_pltfm_free(pdev);
2123 return ret;
2124 }
2125
2126 static int sdhci_msm_remove(struct platform_device *pdev)
2127 {
2128 struct sdhci_host *host = platform_get_drvdata(pdev);
2129 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2130 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2131 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
2132 0xffffffff);
2133
2134 sdhci_remove_host(host, dead);
2135
2136 pm_runtime_get_sync(&pdev->dev);
2137 pm_runtime_disable(&pdev->dev);
2138 pm_runtime_put_noidle(&pdev->dev);
2139
2140 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2141 msm_host->bulk_clks);
2142 if (!IS_ERR(msm_host->bus_clk))
2143 clk_disable_unprepare(msm_host->bus_clk);
2144 sdhci_pltfm_free(pdev);
2145 return 0;
2146 }
2147
2148 static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
2149 {
2150 struct sdhci_host *host = dev_get_drvdata(dev);
2151 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2152 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2153
2154 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2155 msm_host->bulk_clks);
2156
2157 return 0;
2158 }
2159
2160 static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
2161 {
2162 struct sdhci_host *host = dev_get_drvdata(dev);
2163 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2164 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2165 int ret;
2166
2167 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2168 msm_host->bulk_clks);
2169 if (ret)
2170 return ret;
2171 /*
2172 * Whenever core-clock is gated dynamically, it's needed to
2173 * restore the SDR DLL settings when the clock is ungated.
2174 */
2175 if (msm_host->restore_dll_config && msm_host->clk_rate)
2176 return sdhci_msm_restore_sdr_dll_config(host);
2177
2178 return 0;
2179 }
2180
2181 static const struct dev_pm_ops sdhci_msm_pm_ops = {
2182 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2183 pm_runtime_force_resume)
2184 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
2185 sdhci_msm_runtime_resume,
2186 NULL)
2187 };
2188
2189 static struct platform_driver sdhci_msm_driver = {
2190 .probe = sdhci_msm_probe,
2191 .remove = sdhci_msm_remove,
2192 .driver = {
2193 .name = "sdhci_msm",
2194 .of_match_table = sdhci_msm_dt_match,
2195 .pm = &sdhci_msm_pm_ops,
2196 },
2197 };
2198
2199 module_platform_driver(sdhci_msm_driver);
2200
2201 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2202 MODULE_LICENSE("GPL v2");
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