]> git.ipfire.org Git - thirdparty/kernel/linux.git/blob - drivers/mmc/host/sdhci.c
projects / thirdparty / kernel / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mmc: sdhci: fix the timeout check window for clock and reset
[thirdparty/kernel/linux.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/ktime.h>
18 #include <linux/highmem.h>
19 #include <linux/io.h>
20 #include <linux/module.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/slab.h>
23 #include <linux/scatterlist.h>
24 #include <linux/sizes.h>
25 #include <linux/swiotlb.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/of.h>
29
30 #include <linux/leds.h>
31
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/card.h>
35 #include <linux/mmc/sdio.h>
36 #include <linux/mmc/slot-gpio.h>
37
38 #include "sdhci.h"
39
40 #define DRIVER_NAME "sdhci"
41
42 #define DBG(f, x...) \
43 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45 #define SDHCI_DUMP(f, x...) \
46 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
47
48 #define MAX_TUNING_LOOP 40
49
50 static unsigned int debug_quirks = 0;
51 static unsigned int debug_quirks2;
52
53 static void sdhci_finish_data(struct sdhci_host *);
54
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56
57 void sdhci_dumpregs(struct sdhci_host *host)
58 {
59 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
60
61 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
62 sdhci_readl(host, SDHCI_DMA_ADDRESS),
63 sdhci_readw(host, SDHCI_HOST_VERSION));
64 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
65 sdhci_readw(host, SDHCI_BLOCK_SIZE),
66 sdhci_readw(host, SDHCI_BLOCK_COUNT));
67 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
68 sdhci_readl(host, SDHCI_ARGUMENT),
69 sdhci_readw(host, SDHCI_TRANSFER_MODE));
70 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
71 sdhci_readl(host, SDHCI_PRESENT_STATE),
72 sdhci_readb(host, SDHCI_HOST_CONTROL));
73 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
74 sdhci_readb(host, SDHCI_POWER_CONTROL),
75 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
76 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
77 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
78 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
79 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
80 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
81 sdhci_readl(host, SDHCI_INT_STATUS));
82 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
83 sdhci_readl(host, SDHCI_INT_ENABLE),
84 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
85 SDHCI_DUMP("AC12 err: 0x%08x | Slot int: 0x%08x\n",
86 sdhci_readw(host, SDHCI_ACMD12_ERR),
87 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
88 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
89 sdhci_readl(host, SDHCI_CAPABILITIES),
90 sdhci_readl(host, SDHCI_CAPABILITIES_1));
91 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
92 sdhci_readw(host, SDHCI_COMMAND),
93 sdhci_readl(host, SDHCI_MAX_CURRENT));
94 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE),
96 sdhci_readl(host, SDHCI_RESPONSE + 4));
97 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
98 sdhci_readl(host, SDHCI_RESPONSE + 8),
99 sdhci_readl(host, SDHCI_RESPONSE + 12));
100 SDHCI_DUMP("Host ctl2: 0x%08x\n",
101 sdhci_readw(host, SDHCI_HOST_CONTROL2));
102
103 if (host->flags & SDHCI_USE_ADMA) {
104 if (host->flags & SDHCI_USE_64_BIT_DMA) {
105 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
106 sdhci_readl(host, SDHCI_ADMA_ERROR),
107 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
108 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
109 } else {
110 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
111 sdhci_readl(host, SDHCI_ADMA_ERROR),
112 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
113 }
114 }
115
116 SDHCI_DUMP("============================================\n");
117 }
118 EXPORT_SYMBOL_GPL(sdhci_dumpregs);
119
120 /*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124 \*****************************************************************************/
125
126 static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
127 {
128 u16 ctrl2;
129
130 ctrl2 = sdhci_readb(host, SDHCI_HOST_CONTROL2);
131 if (ctrl2 & SDHCI_CTRL_V4_MODE)
132 return;
133
134 ctrl2 |= SDHCI_CTRL_V4_MODE;
135 sdhci_writeb(host, ctrl2, SDHCI_HOST_CONTROL);
136 }
137
138 /*
139 * This can be called before sdhci_add_host() by Vendor's host controller
140 * driver to enable v4 mode if supported.
141 */
142 void sdhci_enable_v4_mode(struct sdhci_host *host)
143 {
144 host->v4_mode = true;
145 sdhci_do_enable_v4_mode(host);
146 }
147 EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
148
149 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
150 {
151 return cmd->data || cmd->flags & MMC_RSP_BUSY;
152 }
153
154 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
155 {
156 u32 present;
157
158 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
159 !mmc_card_is_removable(host->mmc))
160 return;
161
162 if (enable) {
163 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
164 SDHCI_CARD_PRESENT;
165
166 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
167 SDHCI_INT_CARD_INSERT;
168 } else {
169 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
170 }
171
172 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
173 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
174 }
175
176 static void sdhci_enable_card_detection(struct sdhci_host *host)
177 {
178 sdhci_set_card_detection(host, true);
179 }
180
181 static void sdhci_disable_card_detection(struct sdhci_host *host)
182 {
183 sdhci_set_card_detection(host, false);
184 }
185
186 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
187 {
188 if (host->bus_on)
189 return;
190 host->bus_on = true;
191 pm_runtime_get_noresume(host->mmc->parent);
192 }
193
194 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
195 {
196 if (!host->bus_on)
197 return;
198 host->bus_on = false;
199 pm_runtime_put_noidle(host->mmc->parent);
200 }
201
202 void sdhci_reset(struct sdhci_host *host, u8 mask)
203 {
204 ktime_t timeout;
205
206 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
207
208 if (mask & SDHCI_RESET_ALL) {
209 host->clock = 0;
210 /* Reset-all turns off SD Bus Power */
211 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
212 sdhci_runtime_pm_bus_off(host);
213 }
214
215 /* Wait max 100 ms */
216 timeout = ktime_add_ms(ktime_get(), 100);
217
218 /* hw clears the bit when it's done */
219 while (1) {
220 bool timedout = ktime_after(ktime_get(), timeout);
221
222 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
223 break;
224 if (timedout) {
225 pr_err("%s: Reset 0x%x never completed.\n",
226 mmc_hostname(host->mmc), (int)mask);
227 sdhci_dumpregs(host);
228 return;
229 }
230 udelay(10);
231 }
232 }
233 EXPORT_SYMBOL_GPL(sdhci_reset);
234
235 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
236 {
237 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
238 struct mmc_host *mmc = host->mmc;
239
240 if (!mmc->ops->get_cd(mmc))
241 return;
242 }
243
244 host->ops->reset(host, mask);
245
246 if (mask & SDHCI_RESET_ALL) {
247 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
248 if (host->ops->enable_dma)
249 host->ops->enable_dma(host);
250 }
251
252 /* Resetting the controller clears many */
253 host->preset_enabled = false;
254 }
255 }
256
257 static void sdhci_set_default_irqs(struct sdhci_host *host)
258 {
259 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
260 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
261 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
262 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
263 SDHCI_INT_RESPONSE;
264
265 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
266 host->tuning_mode == SDHCI_TUNING_MODE_3)
267 host->ier |= SDHCI_INT_RETUNE;
268
269 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
270 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
271 }
272
273 static void sdhci_config_dma(struct sdhci_host *host)
274 {
275 u8 ctrl;
276 u16 ctrl2;
277
278 if (host->version < SDHCI_SPEC_200)
279 return;
280
281 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
282
283 /*
284 * Always adjust the DMA selection as some controllers
285 * (e.g. JMicron) can't do PIO properly when the selection
286 * is ADMA.
287 */
288 ctrl &= ~SDHCI_CTRL_DMA_MASK;
289 if (!(host->flags & SDHCI_REQ_USE_DMA))
290 goto out;
291
292 /* Note if DMA Select is zero then SDMA is selected */
293 if (host->flags & SDHCI_USE_ADMA)
294 ctrl |= SDHCI_CTRL_ADMA32;
295
296 if (host->flags & SDHCI_USE_64_BIT_DMA) {
297 /*
298 * If v4 mode, all supported DMA can be 64-bit addressing if
299 * controller supports 64-bit system address, otherwise only
300 * ADMA can support 64-bit addressing.
301 */
302 if (host->v4_mode) {
303 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
304 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
305 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
306 } else if (host->flags & SDHCI_USE_ADMA) {
307 /*
308 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
309 * set SDHCI_CTRL_ADMA64.
310 */
311 ctrl |= SDHCI_CTRL_ADMA64;
312 }
313 }
314
315 out:
316 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
317 }
318
319 static void sdhci_init(struct sdhci_host *host, int soft)
320 {
321 struct mmc_host *mmc = host->mmc;
322
323 if (soft)
324 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
325 else
326 sdhci_do_reset(host, SDHCI_RESET_ALL);
327
328 if (host->v4_mode)
329 sdhci_do_enable_v4_mode(host);
330
331 sdhci_set_default_irqs(host);
332
333 host->cqe_on = false;
334
335 if (soft) {
336 /* force clock reconfiguration */
337 host->clock = 0;
338 mmc->ops->set_ios(mmc, &mmc->ios);
339 }
340 }
341
342 static void sdhci_reinit(struct sdhci_host *host)
343 {
344 sdhci_init(host, 0);
345 sdhci_enable_card_detection(host);
346 }
347
348 static void __sdhci_led_activate(struct sdhci_host *host)
349 {
350 u8 ctrl;
351
352 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
353 ctrl |= SDHCI_CTRL_LED;
354 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
355 }
356
357 static void __sdhci_led_deactivate(struct sdhci_host *host)
358 {
359 u8 ctrl;
360
361 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
362 ctrl &= ~SDHCI_CTRL_LED;
363 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
364 }
365
366 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
367 static void sdhci_led_control(struct led_classdev *led,
368 enum led_brightness brightness)
369 {
370 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
371 unsigned long flags;
372
373 spin_lock_irqsave(&host->lock, flags);
374
375 if (host->runtime_suspended)
376 goto out;
377
378 if (brightness == LED_OFF)
379 __sdhci_led_deactivate(host);
380 else
381 __sdhci_led_activate(host);
382 out:
383 spin_unlock_irqrestore(&host->lock, flags);
384 }
385
386 static int sdhci_led_register(struct sdhci_host *host)
387 {
388 struct mmc_host *mmc = host->mmc;
389
390 snprintf(host->led_name, sizeof(host->led_name),
391 "%s::", mmc_hostname(mmc));
392
393 host->led.name = host->led_name;
394 host->led.brightness = LED_OFF;
395 host->led.default_trigger = mmc_hostname(mmc);
396 host->led.brightness_set = sdhci_led_control;
397
398 return led_classdev_register(mmc_dev(mmc), &host->led);
399 }
400
401 static void sdhci_led_unregister(struct sdhci_host *host)
402 {
403 led_classdev_unregister(&host->led);
404 }
405
406 static inline void sdhci_led_activate(struct sdhci_host *host)
407 {
408 }
409
410 static inline void sdhci_led_deactivate(struct sdhci_host *host)
411 {
412 }
413
414 #else
415
416 static inline int sdhci_led_register(struct sdhci_host *host)
417 {
418 return 0;
419 }
420
421 static inline void sdhci_led_unregister(struct sdhci_host *host)
422 {
423 }
424
425 static inline void sdhci_led_activate(struct sdhci_host *host)
426 {
427 __sdhci_led_activate(host);
428 }
429
430 static inline void sdhci_led_deactivate(struct sdhci_host *host)
431 {
432 __sdhci_led_deactivate(host);
433 }
434
435 #endif
436
437 /*****************************************************************************\
438 * *
439 * Core functions *
440 * *
441 \*****************************************************************************/
442
443 static void sdhci_read_block_pio(struct sdhci_host *host)
444 {
445 unsigned long flags;
446 size_t blksize, len, chunk;
447 u32 uninitialized_var(scratch);
448 u8 *buf;
449
450 DBG("PIO reading\n");
451
452 blksize = host->data->blksz;
453 chunk = 0;
454
455 local_irq_save(flags);
456
457 while (blksize) {
458 BUG_ON(!sg_miter_next(&host->sg_miter));
459
460 len = min(host->sg_miter.length, blksize);
461
462 blksize -= len;
463 host->sg_miter.consumed = len;
464
465 buf = host->sg_miter.addr;
466
467 while (len) {
468 if (chunk == 0) {
469 scratch = sdhci_readl(host, SDHCI_BUFFER);
470 chunk = 4;
471 }
472
473 *buf = scratch & 0xFF;
474
475 buf++;
476 scratch >>= 8;
477 chunk--;
478 len--;
479 }
480 }
481
482 sg_miter_stop(&host->sg_miter);
483
484 local_irq_restore(flags);
485 }
486
487 static void sdhci_write_block_pio(struct sdhci_host *host)
488 {
489 unsigned long flags;
490 size_t blksize, len, chunk;
491 u32 scratch;
492 u8 *buf;
493
494 DBG("PIO writing\n");
495
496 blksize = host->data->blksz;
497 chunk = 0;
498 scratch = 0;
499
500 local_irq_save(flags);
501
502 while (blksize) {
503 BUG_ON(!sg_miter_next(&host->sg_miter));
504
505 len = min(host->sg_miter.length, blksize);
506
507 blksize -= len;
508 host->sg_miter.consumed = len;
509
510 buf = host->sg_miter.addr;
511
512 while (len) {
513 scratch |= (u32)*buf << (chunk * 8);
514
515 buf++;
516 chunk++;
517 len--;
518
519 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
520 sdhci_writel(host, scratch, SDHCI_BUFFER);
521 chunk = 0;
522 scratch = 0;
523 }
524 }
525 }
526
527 sg_miter_stop(&host->sg_miter);
528
529 local_irq_restore(flags);
530 }
531
532 static void sdhci_transfer_pio(struct sdhci_host *host)
533 {
534 u32 mask;
535
536 if (host->blocks == 0)
537 return;
538
539 if (host->data->flags & MMC_DATA_READ)
540 mask = SDHCI_DATA_AVAILABLE;
541 else
542 mask = SDHCI_SPACE_AVAILABLE;
543
544 /*
545 * Some controllers (JMicron JMB38x) mess up the buffer bits
546 * for transfers < 4 bytes. As long as it is just one block,
547 * we can ignore the bits.
548 */
549 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
550 (host->data->blocks == 1))
551 mask = ~0;
552
553 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
554 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
555 udelay(100);
556
557 if (host->data->flags & MMC_DATA_READ)
558 sdhci_read_block_pio(host);
559 else
560 sdhci_write_block_pio(host);
561
562 host->blocks--;
563 if (host->blocks == 0)
564 break;
565 }
566
567 DBG("PIO transfer complete.\n");
568 }
569
570 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
571 struct mmc_data *data, int cookie)
572 {
573 int sg_count;
574
575 /*
576 * If the data buffers are already mapped, return the previous
577 * dma_map_sg() result.
578 */
579 if (data->host_cookie == COOKIE_PRE_MAPPED)
580 return data->sg_count;
581
582 /* Bounce write requests to the bounce buffer */
583 if (host->bounce_buffer) {
584 unsigned int length = data->blksz * data->blocks;
585
586 if (length > host->bounce_buffer_size) {
587 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
588 mmc_hostname(host->mmc), length,
589 host->bounce_buffer_size);
590 return -EIO;
591 }
592 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
593 /* Copy the data to the bounce buffer */
594 sg_copy_to_buffer(data->sg, data->sg_len,
595 host->bounce_buffer,
596 length);
597 }
598 /* Switch ownership to the DMA */
599 dma_sync_single_for_device(host->mmc->parent,
600 host->bounce_addr,
601 host->bounce_buffer_size,
602 mmc_get_dma_dir(data));
603 /* Just a dummy value */
604 sg_count = 1;
605 } else {
606 /* Just access the data directly from memory */
607 sg_count = dma_map_sg(mmc_dev(host->mmc),
608 data->sg, data->sg_len,
609 mmc_get_dma_dir(data));
610 }
611
612 if (sg_count == 0)
613 return -ENOSPC;
614
615 data->sg_count = sg_count;
616 data->host_cookie = cookie;
617
618 return sg_count;
619 }
620
621 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
622 {
623 local_irq_save(*flags);
624 return kmap_atomic(sg_page(sg)) + sg->offset;
625 }
626
627 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
628 {
629 kunmap_atomic(buffer);
630 local_irq_restore(*flags);
631 }
632
633 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
634 dma_addr_t addr, int len, unsigned int cmd)
635 {
636 struct sdhci_adma2_64_desc *dma_desc = *desc;
637
638 /* 32-bit and 64-bit descriptors have these members in same position */
639 dma_desc->cmd = cpu_to_le16(cmd);
640 dma_desc->len = cpu_to_le16(len);
641 dma_desc->addr_lo = cpu_to_le32((u32)addr);
642
643 if (host->flags & SDHCI_USE_64_BIT_DMA)
644 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
645
646 *desc += host->desc_sz;
647 }
648 EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
649
650 static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
651 void **desc, dma_addr_t addr,
652 int len, unsigned int cmd)
653 {
654 if (host->ops->adma_write_desc)
655 host->ops->adma_write_desc(host, desc, addr, len, cmd);
656 else
657 sdhci_adma_write_desc(host, desc, addr, len, cmd);
658 }
659
660 static void sdhci_adma_mark_end(void *desc)
661 {
662 struct sdhci_adma2_64_desc *dma_desc = desc;
663
664 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
665 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
666 }
667
668 static void sdhci_adma_table_pre(struct sdhci_host *host,
669 struct mmc_data *data, int sg_count)
670 {
671 struct scatterlist *sg;
672 unsigned long flags;
673 dma_addr_t addr, align_addr;
674 void *desc, *align;
675 char *buffer;
676 int len, offset, i;
677
678 /*
679 * The spec does not specify endianness of descriptor table.
680 * We currently guess that it is LE.
681 */
682
683 host->sg_count = sg_count;
684
685 desc = host->adma_table;
686 align = host->align_buffer;
687
688 align_addr = host->align_addr;
689
690 for_each_sg(data->sg, sg, host->sg_count, i) {
691 addr = sg_dma_address(sg);
692 len = sg_dma_len(sg);
693
694 /*
695 * The SDHCI specification states that ADMA addresses must
696 * be 32-bit aligned. If they aren't, then we use a bounce
697 * buffer for the (up to three) bytes that screw up the
698 * alignment.
699 */
700 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
701 SDHCI_ADMA2_MASK;
702 if (offset) {
703 if (data->flags & MMC_DATA_WRITE) {
704 buffer = sdhci_kmap_atomic(sg, &flags);
705 memcpy(align, buffer, offset);
706 sdhci_kunmap_atomic(buffer, &flags);
707 }
708
709 /* tran, valid */
710 __sdhci_adma_write_desc(host, &desc, align_addr,
711 offset, ADMA2_TRAN_VALID);
712
713 BUG_ON(offset > 65536);
714
715 align += SDHCI_ADMA2_ALIGN;
716 align_addr += SDHCI_ADMA2_ALIGN;
717
718 addr += offset;
719 len -= offset;
720 }
721
722 BUG_ON(len > 65536);
723
724 /* tran, valid */
725 if (len)
726 __sdhci_adma_write_desc(host, &desc, addr, len,
727 ADMA2_TRAN_VALID);
728
729 /*
730 * If this triggers then we have a calculation bug
731 * somewhere. :/
732 */
733 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
734 }
735
736 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
737 /* Mark the last descriptor as the terminating descriptor */
738 if (desc != host->adma_table) {
739 desc -= host->desc_sz;
740 sdhci_adma_mark_end(desc);
741 }
742 } else {
743 /* Add a terminating entry - nop, end, valid */
744 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
745 }
746 }
747
748 static void sdhci_adma_table_post(struct sdhci_host *host,
749 struct mmc_data *data)
750 {
751 struct scatterlist *sg;
752 int i, size;
753 void *align;
754 char *buffer;
755 unsigned long flags;
756
757 if (data->flags & MMC_DATA_READ) {
758 bool has_unaligned = false;
759
760 /* Do a quick scan of the SG list for any unaligned mappings */
761 for_each_sg(data->sg, sg, host->sg_count, i)
762 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
763 has_unaligned = true;
764 break;
765 }
766
767 if (has_unaligned) {
768 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
769 data->sg_len, DMA_FROM_DEVICE);
770
771 align = host->align_buffer;
772
773 for_each_sg(data->sg, sg, host->sg_count, i) {
774 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
775 size = SDHCI_ADMA2_ALIGN -
776 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
777
778 buffer = sdhci_kmap_atomic(sg, &flags);
779 memcpy(buffer, align, size);
780 sdhci_kunmap_atomic(buffer, &flags);
781
782 align += SDHCI_ADMA2_ALIGN;
783 }
784 }
785 }
786 }
787 }
788
789 static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
790 {
791 if (host->bounce_buffer)
792 return host->bounce_addr;
793 else
794 return sg_dma_address(host->data->sg);
795 }
796
797 static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
798 {
799 if (host->v4_mode) {
800 sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS);
801 if (host->flags & SDHCI_USE_64_BIT_DMA)
802 sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI);
803 } else {
804 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
805 }
806 }
807
808 static unsigned int sdhci_target_timeout(struct sdhci_host *host,
809 struct mmc_command *cmd,
810 struct mmc_data *data)
811 {
812 unsigned int target_timeout;
813
814 /* timeout in us */
815 if (!data) {
816 target_timeout = cmd->busy_timeout * 1000;
817 } else {
818 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
819 if (host->clock && data->timeout_clks) {
820 unsigned long long val;
821
822 /*
823 * data->timeout_clks is in units of clock cycles.
824 * host->clock is in Hz. target_timeout is in us.
825 * Hence, us = 1000000 * cycles / Hz. Round up.
826 */
827 val = 1000000ULL * data->timeout_clks;
828 if (do_div(val, host->clock))
829 target_timeout++;
830 target_timeout += val;
831 }
832 }
833
834 return target_timeout;
835 }
836
837 static void sdhci_calc_sw_timeout(struct sdhci_host *host,
838 struct mmc_command *cmd)
839 {
840 struct mmc_data *data = cmd->data;
841 struct mmc_host *mmc = host->mmc;
842 struct mmc_ios *ios = &mmc->ios;
843 unsigned char bus_width = 1 << ios->bus_width;
844 unsigned int blksz;
845 unsigned int freq;
846 u64 target_timeout;
847 u64 transfer_time;
848
849 target_timeout = sdhci_target_timeout(host, cmd, data);
850 target_timeout *= NSEC_PER_USEC;
851
852 if (data) {
853 blksz = data->blksz;
854 freq = host->mmc->actual_clock ? : host->clock;
855 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
856 do_div(transfer_time, freq);
857 /* multiply by '2' to account for any unknowns */
858 transfer_time = transfer_time * 2;
859 /* calculate timeout for the entire data */
860 host->data_timeout = data->blocks * target_timeout +
861 transfer_time;
862 } else {
863 host->data_timeout = target_timeout;
864 }
865
866 if (host->data_timeout)
867 host->data_timeout += MMC_CMD_TRANSFER_TIME;
868 }
869
870 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
871 bool *too_big)
872 {
873 u8 count;
874 struct mmc_data *data = cmd->data;
875 unsigned target_timeout, current_timeout;
876
877 *too_big = true;
878
879 /*
880 * If the host controller provides us with an incorrect timeout
881 * value, just skip the check and use 0xE. The hardware may take
882 * longer to time out, but that's much better than having a too-short
883 * timeout value.
884 */
885 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
886 return 0xE;
887
888 /* Unspecified timeout, assume max */
889 if (!data && !cmd->busy_timeout)
890 return 0xE;
891
892 /* timeout in us */
893 target_timeout = sdhci_target_timeout(host, cmd, data);
894
895 /*
896 * Figure out needed cycles.
897 * We do this in steps in order to fit inside a 32 bit int.
898 * The first step is the minimum timeout, which will have a
899 * minimum resolution of 6 bits:
900 * (1) 2^13*1000 > 2^22,
901 * (2) host->timeout_clk < 2^16
902 * =>
903 * (1) / (2) > 2^6
904 */
905 count = 0;
906 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
907 while (current_timeout < target_timeout) {
908 count++;
909 current_timeout <<= 1;
910 if (count >= 0xF)
911 break;
912 }
913
914 if (count >= 0xF) {
915 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
916 DBG("Too large timeout 0x%x requested for CMD%d!\n",
917 count, cmd->opcode);
918 count = 0xE;
919 } else {
920 *too_big = false;
921 }
922
923 return count;
924 }
925
926 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
927 {
928 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
929 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
930
931 if (host->flags & SDHCI_REQ_USE_DMA)
932 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
933 else
934 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
935
936 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
937 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
938 }
939
940 static void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
941 {
942 if (enable)
943 host->ier |= SDHCI_INT_DATA_TIMEOUT;
944 else
945 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
946 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
947 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
948 }
949
950 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
951 {
952 u8 count;
953
954 if (host->ops->set_timeout) {
955 host->ops->set_timeout(host, cmd);
956 } else {
957 bool too_big = false;
958
959 count = sdhci_calc_timeout(host, cmd, &too_big);
960
961 if (too_big &&
962 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
963 sdhci_calc_sw_timeout(host, cmd);
964 sdhci_set_data_timeout_irq(host, false);
965 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
966 sdhci_set_data_timeout_irq(host, true);
967 }
968
969 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
970 }
971 }
972
973 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
974 {
975 struct mmc_data *data = cmd->data;
976
977 host->data_timeout = 0;
978
979 if (sdhci_data_line_cmd(cmd))
980 sdhci_set_timeout(host, cmd);
981
982 if (!data)
983 return;
984
985 WARN_ON(host->data);
986
987 /* Sanity checks */
988 BUG_ON(data->blksz * data->blocks > 524288);
989 BUG_ON(data->blksz > host->mmc->max_blk_size);
990 BUG_ON(data->blocks > 65535);
991
992 host->data = data;
993 host->data_early = 0;
994 host->data->bytes_xfered = 0;
995
996 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
997 struct scatterlist *sg;
998 unsigned int length_mask, offset_mask;
999 int i;
1000
1001 host->flags |= SDHCI_REQ_USE_DMA;
1002
1003 /*
1004 * FIXME: This doesn't account for merging when mapping the
1005 * scatterlist.
1006 *
1007 * The assumption here being that alignment and lengths are
1008 * the same after DMA mapping to device address space.
1009 */
1010 length_mask = 0;
1011 offset_mask = 0;
1012 if (host->flags & SDHCI_USE_ADMA) {
1013 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1014 length_mask = 3;
1015 /*
1016 * As we use up to 3 byte chunks to work
1017 * around alignment problems, we need to
1018 * check the offset as well.
1019 */
1020 offset_mask = 3;
1021 }
1022 } else {
1023 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1024 length_mask = 3;
1025 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1026 offset_mask = 3;
1027 }
1028
1029 if (unlikely(length_mask | offset_mask)) {
1030 for_each_sg(data->sg, sg, data->sg_len, i) {
1031 if (sg->length & length_mask) {
1032 DBG("Reverting to PIO because of transfer size (%d)\n",
1033 sg->length);
1034 host->flags &= ~SDHCI_REQ_USE_DMA;
1035 break;
1036 }
1037 if (sg->offset & offset_mask) {
1038 DBG("Reverting to PIO because of bad alignment\n");
1039 host->flags &= ~SDHCI_REQ_USE_DMA;
1040 break;
1041 }
1042 }
1043 }
1044 }
1045
1046 if (host->flags & SDHCI_REQ_USE_DMA) {
1047 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1048
1049 if (sg_cnt <= 0) {
1050 /*
1051 * This only happens when someone fed
1052 * us an invalid request.
1053 */
1054 WARN_ON(1);
1055 host->flags &= ~SDHCI_REQ_USE_DMA;
1056 } else if (host->flags & SDHCI_USE_ADMA) {
1057 sdhci_adma_table_pre(host, data, sg_cnt);
1058
1059 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
1060 if (host->flags & SDHCI_USE_64_BIT_DMA)
1061 sdhci_writel(host,
1062 (u64)host->adma_addr >> 32,
1063 SDHCI_ADMA_ADDRESS_HI);
1064 } else {
1065 WARN_ON(sg_cnt != 1);
1066 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1067 }
1068 }
1069
1070 sdhci_config_dma(host);
1071
1072 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1073 int flags;
1074
1075 flags = SG_MITER_ATOMIC;
1076 if (host->data->flags & MMC_DATA_READ)
1077 flags |= SG_MITER_TO_SG;
1078 else
1079 flags |= SG_MITER_FROM_SG;
1080 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1081 host->blocks = data->blocks;
1082 }
1083
1084 sdhci_set_transfer_irqs(host);
1085
1086 /* Set the DMA boundary value and block size */
1087 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1088 SDHCI_BLOCK_SIZE);
1089
1090 /*
1091 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1092 * can be supported, in that case 16-bit block count register must be 0.
1093 */
1094 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1095 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1096 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1097 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1098 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1099 } else {
1100 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1101 }
1102 }
1103
1104 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1105 struct mmc_request *mrq)
1106 {
1107 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1108 !mrq->cap_cmd_during_tfr;
1109 }
1110
1111 static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1112 struct mmc_command *cmd,
1113 u16 *mode)
1114 {
1115 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1116 (cmd->opcode != SD_IO_RW_EXTENDED);
1117 bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1118 u16 ctrl2;
1119
1120 /*
1121 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1122 * Select' is recommended rather than use of 'Auto CMD12
1123 * Enable' or 'Auto CMD23 Enable'.
1124 */
1125 if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) {
1126 *mode |= SDHCI_TRNS_AUTO_SEL;
1127
1128 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1129 if (use_cmd23)
1130 ctrl2 |= SDHCI_CMD23_ENABLE;
1131 else
1132 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1133 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1134
1135 return;
1136 }
1137
1138 /*
1139 * If we are sending CMD23, CMD12 never gets sent
1140 * on successful completion (so no Auto-CMD12).
1141 */
1142 if (use_cmd12)
1143 *mode |= SDHCI_TRNS_AUTO_CMD12;
1144 else if (use_cmd23)
1145 *mode |= SDHCI_TRNS_AUTO_CMD23;
1146 }
1147
1148 static void sdhci_set_transfer_mode(struct sdhci_host *host,
1149 struct mmc_command *cmd)
1150 {
1151 u16 mode = 0;
1152 struct mmc_data *data = cmd->data;
1153
1154 if (data == NULL) {
1155 if (host->quirks2 &
1156 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1157 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1158 if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1159 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1160 } else {
1161 /* clear Auto CMD settings for no data CMDs */
1162 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1163 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1164 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1165 }
1166 return;
1167 }
1168
1169 WARN_ON(!host->data);
1170
1171 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1172 mode = SDHCI_TRNS_BLK_CNT_EN;
1173
1174 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1175 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1176 sdhci_auto_cmd_select(host, cmd, &mode);
1177 if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23))
1178 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1179 }
1180
1181 if (data->flags & MMC_DATA_READ)
1182 mode |= SDHCI_TRNS_READ;
1183 if (host->flags & SDHCI_REQ_USE_DMA)
1184 mode |= SDHCI_TRNS_DMA;
1185
1186 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1187 }
1188
1189 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1190 {
1191 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1192 ((mrq->cmd && mrq->cmd->error) ||
1193 (mrq->sbc && mrq->sbc->error) ||
1194 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
1195 (mrq->data->stop && mrq->data->stop->error))) ||
1196 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1197 }
1198
1199 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1200 {
1201 int i;
1202
1203 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1204 if (host->mrqs_done[i] == mrq) {
1205 WARN_ON(1);
1206 return;
1207 }
1208 }
1209
1210 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1211 if (!host->mrqs_done[i]) {
1212 host->mrqs_done[i] = mrq;
1213 break;
1214 }
1215 }
1216
1217 WARN_ON(i >= SDHCI_MAX_MRQS);
1218
1219 tasklet_schedule(&host->finish_tasklet);
1220 }
1221
1222 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1223 {
1224 if (host->cmd && host->cmd->mrq == mrq)
1225 host->cmd = NULL;
1226
1227 if (host->data_cmd && host->data_cmd->mrq == mrq)
1228 host->data_cmd = NULL;
1229
1230 if (host->data && host->data->mrq == mrq)
1231 host->data = NULL;
1232
1233 if (sdhci_needs_reset(host, mrq))
1234 host->pending_reset = true;
1235
1236 __sdhci_finish_mrq(host, mrq);
1237 }
1238
1239 static void sdhci_finish_data(struct sdhci_host *host)
1240 {
1241 struct mmc_command *data_cmd = host->data_cmd;
1242 struct mmc_data *data = host->data;
1243
1244 host->data = NULL;
1245 host->data_cmd = NULL;
1246
1247 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1248 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1249 sdhci_adma_table_post(host, data);
1250
1251 /*
1252 * The specification states that the block count register must
1253 * be updated, but it does not specify at what point in the
1254 * data flow. That makes the register entirely useless to read
1255 * back so we have to assume that nothing made it to the card
1256 * in the event of an error.
1257 */
1258 if (data->error)
1259 data->bytes_xfered = 0;
1260 else
1261 data->bytes_xfered = data->blksz * data->blocks;
1262
1263 /*
1264 * Need to send CMD12 if -
1265 * a) open-ended multiblock transfer (no CMD23)
1266 * b) error in multiblock transfer
1267 */
1268 if (data->stop &&
1269 (data->error ||
1270 !data->mrq->sbc)) {
1271
1272 /*
1273 * The controller needs a reset of internal state machines
1274 * upon error conditions.
1275 */
1276 if (data->error) {
1277 if (!host->cmd || host->cmd == data_cmd)
1278 sdhci_do_reset(host, SDHCI_RESET_CMD);
1279 sdhci_do_reset(host, SDHCI_RESET_DATA);
1280 }
1281
1282 /*
1283 * 'cap_cmd_during_tfr' request must not use the command line
1284 * after mmc_command_done() has been called. It is upper layer's
1285 * responsibility to send the stop command if required.
1286 */
1287 if (data->mrq->cap_cmd_during_tfr) {
1288 sdhci_finish_mrq(host, data->mrq);
1289 } else {
1290 /* Avoid triggering warning in sdhci_send_command() */
1291 host->cmd = NULL;
1292 sdhci_send_command(host, data->stop);
1293 }
1294 } else {
1295 sdhci_finish_mrq(host, data->mrq);
1296 }
1297 }
1298
1299 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1300 unsigned long timeout)
1301 {
1302 if (sdhci_data_line_cmd(mrq->cmd))
1303 mod_timer(&host->data_timer, timeout);
1304 else
1305 mod_timer(&host->timer, timeout);
1306 }
1307
1308 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1309 {
1310 if (sdhci_data_line_cmd(mrq->cmd))
1311 del_timer(&host->data_timer);
1312 else
1313 del_timer(&host->timer);
1314 }
1315
1316 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1317 {
1318 int flags;
1319 u32 mask;
1320 unsigned long timeout;
1321
1322 WARN_ON(host->cmd);
1323
1324 /* Initially, a command has no error */
1325 cmd->error = 0;
1326
1327 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1328 cmd->opcode == MMC_STOP_TRANSMISSION)
1329 cmd->flags |= MMC_RSP_BUSY;
1330
1331 /* Wait max 10 ms */
1332 timeout = 10;
1333
1334 mask = SDHCI_CMD_INHIBIT;
1335 if (sdhci_data_line_cmd(cmd))
1336 mask |= SDHCI_DATA_INHIBIT;
1337
1338 /* We shouldn't wait for data inihibit for stop commands, even
1339 though they might use busy signaling */
1340 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1341 mask &= ~SDHCI_DATA_INHIBIT;
1342
1343 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1344 if (timeout == 0) {
1345 pr_err("%s: Controller never released inhibit bit(s).\n",
1346 mmc_hostname(host->mmc));
1347 sdhci_dumpregs(host);
1348 cmd->error = -EIO;
1349 sdhci_finish_mrq(host, cmd->mrq);
1350 return;
1351 }
1352 timeout--;
1353 mdelay(1);
1354 }
1355
1356 host->cmd = cmd;
1357 if (sdhci_data_line_cmd(cmd)) {
1358 WARN_ON(host->data_cmd);
1359 host->data_cmd = cmd;
1360 }
1361
1362 sdhci_prepare_data(host, cmd);
1363
1364 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1365
1366 sdhci_set_transfer_mode(host, cmd);
1367
1368 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1369 pr_err("%s: Unsupported response type!\n",
1370 mmc_hostname(host->mmc));
1371 cmd->error = -EINVAL;
1372 sdhci_finish_mrq(host, cmd->mrq);
1373 return;
1374 }
1375
1376 if (!(cmd->flags & MMC_RSP_PRESENT))
1377 flags = SDHCI_CMD_RESP_NONE;
1378 else if (cmd->flags & MMC_RSP_136)
1379 flags = SDHCI_CMD_RESP_LONG;
1380 else if (cmd->flags & MMC_RSP_BUSY)
1381 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1382 else
1383 flags = SDHCI_CMD_RESP_SHORT;
1384
1385 if (cmd->flags & MMC_RSP_CRC)
1386 flags |= SDHCI_CMD_CRC;
1387 if (cmd->flags & MMC_RSP_OPCODE)
1388 flags |= SDHCI_CMD_INDEX;
1389
1390 /* CMD19 is special in that the Data Present Select should be set */
1391 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1392 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1393 flags |= SDHCI_CMD_DATA;
1394
1395 timeout = jiffies;
1396 if (host->data_timeout)
1397 timeout += nsecs_to_jiffies(host->data_timeout);
1398 else if (!cmd->data && cmd->busy_timeout > 9000)
1399 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1400 else
1401 timeout += 10 * HZ;
1402 sdhci_mod_timer(host, cmd->mrq, timeout);
1403
1404 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1405 }
1406 EXPORT_SYMBOL_GPL(sdhci_send_command);
1407
1408 static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1409 {
1410 int i, reg;
1411
1412 for (i = 0; i < 4; i++) {
1413 reg = SDHCI_RESPONSE + (3 - i) * 4;
1414 cmd->resp[i] = sdhci_readl(host, reg);
1415 }
1416
1417 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1418 return;
1419
1420 /* CRC is stripped so we need to do some shifting */
1421 for (i = 0; i < 4; i++) {
1422 cmd->resp[i] <<= 8;
1423 if (i != 3)
1424 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1425 }
1426 }
1427
1428 static void sdhci_finish_command(struct sdhci_host *host)
1429 {
1430 struct mmc_command *cmd = host->cmd;
1431
1432 host->cmd = NULL;
1433
1434 if (cmd->flags & MMC_RSP_PRESENT) {
1435 if (cmd->flags & MMC_RSP_136) {
1436 sdhci_read_rsp_136(host, cmd);
1437 } else {
1438 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1439 }
1440 }
1441
1442 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1443 mmc_command_done(host->mmc, cmd->mrq);
1444
1445 /*
1446 * The host can send and interrupt when the busy state has
1447 * ended, allowing us to wait without wasting CPU cycles.
1448 * The busy signal uses DAT0 so this is similar to waiting
1449 * for data to complete.
1450 *
1451 * Note: The 1.0 specification is a bit ambiguous about this
1452 * feature so there might be some problems with older
1453 * controllers.
1454 */
1455 if (cmd->flags & MMC_RSP_BUSY) {
1456 if (cmd->data) {
1457 DBG("Cannot wait for busy signal when also doing a data transfer");
1458 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1459 cmd == host->data_cmd) {
1460 /* Command complete before busy is ended */
1461 return;
1462 }
1463 }
1464
1465 /* Finished CMD23, now send actual command. */
1466 if (cmd == cmd->mrq->sbc) {
1467 sdhci_send_command(host, cmd->mrq->cmd);
1468 } else {
1469
1470 /* Processed actual command. */
1471 if (host->data && host->data_early)
1472 sdhci_finish_data(host);
1473
1474 if (!cmd->data)
1475 sdhci_finish_mrq(host, cmd->mrq);
1476 }
1477 }
1478
1479 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1480 {
1481 u16 preset = 0;
1482
1483 switch (host->timing) {
1484 case MMC_TIMING_UHS_SDR12:
1485 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1486 break;
1487 case MMC_TIMING_UHS_SDR25:
1488 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1489 break;
1490 case MMC_TIMING_UHS_SDR50:
1491 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1492 break;
1493 case MMC_TIMING_UHS_SDR104:
1494 case MMC_TIMING_MMC_HS200:
1495 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1496 break;
1497 case MMC_TIMING_UHS_DDR50:
1498 case MMC_TIMING_MMC_DDR52:
1499 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1500 break;
1501 case MMC_TIMING_MMC_HS400:
1502 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1503 break;
1504 default:
1505 pr_warn("%s: Invalid UHS-I mode selected\n",
1506 mmc_hostname(host->mmc));
1507 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1508 break;
1509 }
1510 return preset;
1511 }
1512
1513 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1514 unsigned int *actual_clock)
1515 {
1516 int div = 0; /* Initialized for compiler warning */
1517 int real_div = div, clk_mul = 1;
1518 u16 clk = 0;
1519 bool switch_base_clk = false;
1520
1521 if (host->version >= SDHCI_SPEC_300) {
1522 if (host->preset_enabled) {
1523 u16 pre_val;
1524
1525 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1526 pre_val = sdhci_get_preset_value(host);
1527 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1528 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1529 if (host->clk_mul &&
1530 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1531 clk = SDHCI_PROG_CLOCK_MODE;
1532 real_div = div + 1;
1533 clk_mul = host->clk_mul;
1534 } else {
1535 real_div = max_t(int, 1, div << 1);
1536 }
1537 goto clock_set;
1538 }
1539
1540 /*
1541 * Check if the Host Controller supports Programmable Clock
1542 * Mode.
1543 */
1544 if (host->clk_mul) {
1545 for (div = 1; div <= 1024; div++) {
1546 if ((host->max_clk * host->clk_mul / div)
1547 <= clock)
1548 break;
1549 }
1550 if ((host->max_clk * host->clk_mul / div) <= clock) {
1551 /*
1552 * Set Programmable Clock Mode in the Clock
1553 * Control register.
1554 */
1555 clk = SDHCI_PROG_CLOCK_MODE;
1556 real_div = div;
1557 clk_mul = host->clk_mul;
1558 div--;
1559 } else {
1560 /*
1561 * Divisor can be too small to reach clock
1562 * speed requirement. Then use the base clock.
1563 */
1564 switch_base_clk = true;
1565 }
1566 }
1567
1568 if (!host->clk_mul || switch_base_clk) {
1569 /* Version 3.00 divisors must be a multiple of 2. */
1570 if (host->max_clk <= clock)
1571 div = 1;
1572 else {
1573 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1574 div += 2) {
1575 if ((host->max_clk / div) <= clock)
1576 break;
1577 }
1578 }
1579 real_div = div;
1580 div >>= 1;
1581 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1582 && !div && host->max_clk <= 25000000)
1583 div = 1;
1584 }
1585 } else {
1586 /* Version 2.00 divisors must be a power of 2. */
1587 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1588 if ((host->max_clk / div) <= clock)
1589 break;
1590 }
1591 real_div = div;
1592 div >>= 1;
1593 }
1594
1595 clock_set:
1596 if (real_div)
1597 *actual_clock = (host->max_clk * clk_mul) / real_div;
1598 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1599 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1600 << SDHCI_DIVIDER_HI_SHIFT;
1601
1602 return clk;
1603 }
1604 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1605
1606 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1607 {
1608 ktime_t timeout;
1609
1610 clk |= SDHCI_CLOCK_INT_EN;
1611 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1612
1613 /* Wait max 20 ms */
1614 timeout = ktime_add_ms(ktime_get(), 20);
1615 while (1) {
1616 bool timedout = ktime_after(ktime_get(), timeout);
1617
1618 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1619 if (clk & SDHCI_CLOCK_INT_STABLE)
1620 break;
1621 if (timedout) {
1622 pr_err("%s: Internal clock never stabilised.\n",
1623 mmc_hostname(host->mmc));
1624 sdhci_dumpregs(host);
1625 return;
1626 }
1627 udelay(10);
1628 }
1629
1630 clk |= SDHCI_CLOCK_CARD_EN;
1631 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1632 }
1633 EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1634
1635 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1636 {
1637 u16 clk;
1638
1639 host->mmc->actual_clock = 0;
1640
1641 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1642
1643 if (clock == 0)
1644 return;
1645
1646 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1647 sdhci_enable_clk(host, clk);
1648 }
1649 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1650
1651 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1652 unsigned short vdd)
1653 {
1654 struct mmc_host *mmc = host->mmc;
1655
1656 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1657
1658 if (mode != MMC_POWER_OFF)
1659 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1660 else
1661 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1662 }
1663
1664 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1665 unsigned short vdd)
1666 {
1667 u8 pwr = 0;
1668
1669 if (mode != MMC_POWER_OFF) {
1670 switch (1 << vdd) {
1671 case MMC_VDD_165_195:
1672 /*
1673 * Without a regulator, SDHCI does not support 2.0v
1674 * so we only get here if the driver deliberately
1675 * added the 2.0v range to ocr_avail. Map it to 1.8v
1676 * for the purpose of turning on the power.
1677 */
1678 case MMC_VDD_20_21:
1679 pwr = SDHCI_POWER_180;
1680 break;
1681 case MMC_VDD_29_30:
1682 case MMC_VDD_30_31:
1683 pwr = SDHCI_POWER_300;
1684 break;
1685 case MMC_VDD_32_33:
1686 case MMC_VDD_33_34:
1687 pwr = SDHCI_POWER_330;
1688 break;
1689 default:
1690 WARN(1, "%s: Invalid vdd %#x\n",
1691 mmc_hostname(host->mmc), vdd);
1692 break;
1693 }
1694 }
1695
1696 if (host->pwr == pwr)
1697 return;
1698
1699 host->pwr = pwr;
1700
1701 if (pwr == 0) {
1702 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1703 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1704 sdhci_runtime_pm_bus_off(host);
1705 } else {
1706 /*
1707 * Spec says that we should clear the power reg before setting
1708 * a new value. Some controllers don't seem to like this though.
1709 */
1710 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1711 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1712
1713 /*
1714 * At least the Marvell CaFe chip gets confused if we set the
1715 * voltage and set turn on power at the same time, so set the
1716 * voltage first.
1717 */
1718 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1719 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1720
1721 pwr |= SDHCI_POWER_ON;
1722
1723 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1724
1725 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1726 sdhci_runtime_pm_bus_on(host);
1727
1728 /*
1729 * Some controllers need an extra 10ms delay of 10ms before
1730 * they can apply clock after applying power
1731 */
1732 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1733 mdelay(10);
1734 }
1735 }
1736 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1737
1738 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1739 unsigned short vdd)
1740 {
1741 if (IS_ERR(host->mmc->supply.vmmc))
1742 sdhci_set_power_noreg(host, mode, vdd);
1743 else
1744 sdhci_set_power_reg(host, mode, vdd);
1745 }
1746 EXPORT_SYMBOL_GPL(sdhci_set_power);
1747
1748 /*****************************************************************************\
1749 * *
1750 * MMC callbacks *
1751 * *
1752 \*****************************************************************************/
1753
1754 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1755 {
1756 struct sdhci_host *host;
1757 int present;
1758 unsigned long flags;
1759
1760 host = mmc_priv(mmc);
1761
1762 /* Firstly check card presence */
1763 present = mmc->ops->get_cd(mmc);
1764
1765 spin_lock_irqsave(&host->lock, flags);
1766
1767 sdhci_led_activate(host);
1768
1769 /*
1770 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1771 * requests if Auto-CMD12 is enabled.
1772 */
1773 if (sdhci_auto_cmd12(host, mrq)) {
1774 if (mrq->stop) {
1775 mrq->data->stop = NULL;
1776 mrq->stop = NULL;
1777 }
1778 }
1779
1780 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1781 mrq->cmd->error = -ENOMEDIUM;
1782 sdhci_finish_mrq(host, mrq);
1783 } else {
1784 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1785 sdhci_send_command(host, mrq->sbc);
1786 else
1787 sdhci_send_command(host, mrq->cmd);
1788 }
1789
1790 mmiowb();
1791 spin_unlock_irqrestore(&host->lock, flags);
1792 }
1793 EXPORT_SYMBOL_GPL(sdhci_request);
1794
1795 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1796 {
1797 u8 ctrl;
1798
1799 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1800 if (width == MMC_BUS_WIDTH_8) {
1801 ctrl &= ~SDHCI_CTRL_4BITBUS;
1802 ctrl |= SDHCI_CTRL_8BITBUS;
1803 } else {
1804 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
1805 ctrl &= ~SDHCI_CTRL_8BITBUS;
1806 if (width == MMC_BUS_WIDTH_4)
1807 ctrl |= SDHCI_CTRL_4BITBUS;
1808 else
1809 ctrl &= ~SDHCI_CTRL_4BITBUS;
1810 }
1811 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1812 }
1813 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1814
1815 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1816 {
1817 u16 ctrl_2;
1818
1819 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1820 /* Select Bus Speed Mode for host */
1821 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1822 if ((timing == MMC_TIMING_MMC_HS200) ||
1823 (timing == MMC_TIMING_UHS_SDR104))
1824 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1825 else if (timing == MMC_TIMING_UHS_SDR12)
1826 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1827 else if (timing == MMC_TIMING_UHS_SDR25)
1828 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1829 else if (timing == MMC_TIMING_UHS_SDR50)
1830 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1831 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1832 (timing == MMC_TIMING_MMC_DDR52))
1833 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1834 else if (timing == MMC_TIMING_MMC_HS400)
1835 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1836 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1837 }
1838 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1839
1840 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1841 {
1842 struct sdhci_host *host = mmc_priv(mmc);
1843 u8 ctrl;
1844
1845 if (ios->power_mode == MMC_POWER_UNDEFINED)
1846 return;
1847
1848 if (host->flags & SDHCI_DEVICE_DEAD) {
1849 if (!IS_ERR(mmc->supply.vmmc) &&
1850 ios->power_mode == MMC_POWER_OFF)
1851 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1852 return;
1853 }
1854
1855 /*
1856 * Reset the chip on each power off.
1857 * Should clear out any weird states.
1858 */
1859 if (ios->power_mode == MMC_POWER_OFF) {
1860 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1861 sdhci_reinit(host);
1862 }
1863
1864 if (host->version >= SDHCI_SPEC_300 &&
1865 (ios->power_mode == MMC_POWER_UP) &&
1866 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1867 sdhci_enable_preset_value(host, false);
1868
1869 if (!ios->clock || ios->clock != host->clock) {
1870 host->ops->set_clock(host, ios->clock);
1871 host->clock = ios->clock;
1872
1873 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1874 host->clock) {
1875 host->timeout_clk = host->mmc->actual_clock ?
1876 host->mmc->actual_clock / 1000 :
1877 host->clock / 1000;
1878 host->mmc->max_busy_timeout =
1879 host->ops->get_max_timeout_count ?
1880 host->ops->get_max_timeout_count(host) :
1881 1 << 27;
1882 host->mmc->max_busy_timeout /= host->timeout_clk;
1883 }
1884 }
1885
1886 if (host->ops->set_power)
1887 host->ops->set_power(host, ios->power_mode, ios->vdd);
1888 else
1889 sdhci_set_power(host, ios->power_mode, ios->vdd);
1890
1891 if (host->ops->platform_send_init_74_clocks)
1892 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1893
1894 host->ops->set_bus_width(host, ios->bus_width);
1895
1896 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1897
1898 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
1899 if (ios->timing == MMC_TIMING_SD_HS ||
1900 ios->timing == MMC_TIMING_MMC_HS ||
1901 ios->timing == MMC_TIMING_MMC_HS400 ||
1902 ios->timing == MMC_TIMING_MMC_HS200 ||
1903 ios->timing == MMC_TIMING_MMC_DDR52 ||
1904 ios->timing == MMC_TIMING_UHS_SDR50 ||
1905 ios->timing == MMC_TIMING_UHS_SDR104 ||
1906 ios->timing == MMC_TIMING_UHS_DDR50 ||
1907 ios->timing == MMC_TIMING_UHS_SDR25)
1908 ctrl |= SDHCI_CTRL_HISPD;
1909 else
1910 ctrl &= ~SDHCI_CTRL_HISPD;
1911 }
1912
1913 if (host->version >= SDHCI_SPEC_300) {
1914 u16 clk, ctrl_2;
1915
1916 if (!host->preset_enabled) {
1917 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1918 /*
1919 * We only need to set Driver Strength if the
1920 * preset value enable is not set.
1921 */
1922 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1923 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1924 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1925 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1926 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1927 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1928 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1929 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1930 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1931 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1932 else {
1933 pr_warn("%s: invalid driver type, default to driver type B\n",
1934 mmc_hostname(mmc));
1935 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1936 }
1937
1938 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1939 } else {
1940 /*
1941 * According to SDHC Spec v3.00, if the Preset Value
1942 * Enable in the Host Control 2 register is set, we
1943 * need to reset SD Clock Enable before changing High
1944 * Speed Enable to avoid generating clock gliches.
1945 */
1946
1947 /* Reset SD Clock Enable */
1948 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1949 clk &= ~SDHCI_CLOCK_CARD_EN;
1950 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1951
1952 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1953
1954 /* Re-enable SD Clock */
1955 host->ops->set_clock(host, host->clock);
1956 }
1957
1958 /* Reset SD Clock Enable */
1959 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1960 clk &= ~SDHCI_CLOCK_CARD_EN;
1961 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1962
1963 host->ops->set_uhs_signaling(host, ios->timing);
1964 host->timing = ios->timing;
1965
1966 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1967 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1968 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1969 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1970 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1971 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1972 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1973 u16 preset;
1974
1975 sdhci_enable_preset_value(host, true);
1976 preset = sdhci_get_preset_value(host);
1977 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1978 >> SDHCI_PRESET_DRV_SHIFT;
1979 }
1980
1981 /* Re-enable SD Clock */
1982 host->ops->set_clock(host, host->clock);
1983 } else
1984 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1985
1986 /*
1987 * Some (ENE) controllers go apeshit on some ios operation,
1988 * signalling timeout and CRC errors even on CMD0. Resetting
1989 * it on each ios seems to solve the problem.
1990 */
1991 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1992 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1993
1994 mmiowb();
1995 }
1996 EXPORT_SYMBOL_GPL(sdhci_set_ios);
1997
1998 static int sdhci_get_cd(struct mmc_host *mmc)
1999 {
2000 struct sdhci_host *host = mmc_priv(mmc);
2001 int gpio_cd = mmc_gpio_get_cd(mmc);
2002
2003 if (host->flags & SDHCI_DEVICE_DEAD)
2004 return 0;
2005
2006 /* If nonremovable, assume that the card is always present. */
2007 if (!mmc_card_is_removable(host->mmc))
2008 return 1;
2009
2010 /*
2011 * Try slot gpio detect, if defined it take precedence
2012 * over build in controller functionality
2013 */
2014 if (gpio_cd >= 0)
2015 return !!gpio_cd;
2016
2017 /* If polling, assume that the card is always present. */
2018 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2019 return 1;
2020
2021 /* Host native card detect */
2022 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2023 }
2024
2025 static int sdhci_check_ro(struct sdhci_host *host)
2026 {
2027 unsigned long flags;
2028 int is_readonly;
2029
2030 spin_lock_irqsave(&host->lock, flags);
2031
2032 if (host->flags & SDHCI_DEVICE_DEAD)
2033 is_readonly = 0;
2034 else if (host->ops->get_ro)
2035 is_readonly = host->ops->get_ro(host);
2036 else
2037 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2038 & SDHCI_WRITE_PROTECT);
2039
2040 spin_unlock_irqrestore(&host->lock, flags);
2041
2042 /* This quirk needs to be replaced by a callback-function later */
2043 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2044 !is_readonly : is_readonly;
2045 }
2046
2047 #define SAMPLE_COUNT 5
2048
2049 static int sdhci_get_ro(struct mmc_host *mmc)
2050 {
2051 struct sdhci_host *host = mmc_priv(mmc);
2052 int i, ro_count;
2053
2054 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2055 return sdhci_check_ro(host);
2056
2057 ro_count = 0;
2058 for (i = 0; i < SAMPLE_COUNT; i++) {
2059 if (sdhci_check_ro(host)) {
2060 if (++ro_count > SAMPLE_COUNT / 2)
2061 return 1;
2062 }
2063 msleep(30);
2064 }
2065 return 0;
2066 }
2067
2068 static void sdhci_hw_reset(struct mmc_host *mmc)
2069 {
2070 struct sdhci_host *host = mmc_priv(mmc);
2071
2072 if (host->ops && host->ops->hw_reset)
2073 host->ops->hw_reset(host);
2074 }
2075
2076 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2077 {
2078 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2079 if (enable)
2080 host->ier |= SDHCI_INT_CARD_INT;
2081 else
2082 host->ier &= ~SDHCI_INT_CARD_INT;
2083
2084 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2085 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2086 mmiowb();
2087 }
2088 }
2089
2090 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2091 {
2092 struct sdhci_host *host = mmc_priv(mmc);
2093 unsigned long flags;
2094
2095 if (enable)
2096 pm_runtime_get_noresume(host->mmc->parent);
2097
2098 spin_lock_irqsave(&host->lock, flags);
2099 if (enable)
2100 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
2101 else
2102 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
2103
2104 sdhci_enable_sdio_irq_nolock(host, enable);
2105 spin_unlock_irqrestore(&host->lock, flags);
2106
2107 if (!enable)
2108 pm_runtime_put_noidle(host->mmc->parent);
2109 }
2110 EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2111
2112 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2113 struct mmc_ios *ios)
2114 {
2115 struct sdhci_host *host = mmc_priv(mmc);
2116 u16 ctrl;
2117 int ret;
2118
2119 /*
2120 * Signal Voltage Switching is only applicable for Host Controllers
2121 * v3.00 and above.
2122 */
2123 if (host->version < SDHCI_SPEC_300)
2124 return 0;
2125
2126 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2127
2128 switch (ios->signal_voltage) {
2129 case MMC_SIGNAL_VOLTAGE_330:
2130 if (!(host->flags & SDHCI_SIGNALING_330))
2131 return -EINVAL;
2132 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2133 ctrl &= ~SDHCI_CTRL_VDD_180;
2134 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2135
2136 if (!IS_ERR(mmc->supply.vqmmc)) {
2137 ret = mmc_regulator_set_vqmmc(mmc, ios);
2138 if (ret) {
2139 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2140 mmc_hostname(mmc));
2141 return -EIO;
2142 }
2143 }
2144 /* Wait for 5ms */
2145 usleep_range(5000, 5500);
2146
2147 /* 3.3V regulator output should be stable within 5 ms */
2148 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2149 if (!(ctrl & SDHCI_CTRL_VDD_180))
2150 return 0;
2151
2152 pr_warn("%s: 3.3V regulator output did not became stable\n",
2153 mmc_hostname(mmc));
2154
2155 return -EAGAIN;
2156 case MMC_SIGNAL_VOLTAGE_180:
2157 if (!(host->flags & SDHCI_SIGNALING_180))
2158 return -EINVAL;
2159 if (!IS_ERR(mmc->supply.vqmmc)) {
2160 ret = mmc_regulator_set_vqmmc(mmc, ios);
2161 if (ret) {
2162 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2163 mmc_hostname(mmc));
2164 return -EIO;
2165 }
2166 }
2167
2168 /*
2169 * Enable 1.8V Signal Enable in the Host Control2
2170 * register
2171 */
2172 ctrl |= SDHCI_CTRL_VDD_180;
2173 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2174
2175 /* Some controller need to do more when switching */
2176 if (host->ops->voltage_switch)
2177 host->ops->voltage_switch(host);
2178
2179 /* 1.8V regulator output should be stable within 5 ms */
2180 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2181 if (ctrl & SDHCI_CTRL_VDD_180)
2182 return 0;
2183
2184 pr_warn("%s: 1.8V regulator output did not became stable\n",
2185 mmc_hostname(mmc));
2186
2187 return -EAGAIN;
2188 case MMC_SIGNAL_VOLTAGE_120:
2189 if (!(host->flags & SDHCI_SIGNALING_120))
2190 return -EINVAL;
2191 if (!IS_ERR(mmc->supply.vqmmc)) {
2192 ret = mmc_regulator_set_vqmmc(mmc, ios);
2193 if (ret) {
2194 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2195 mmc_hostname(mmc));
2196 return -EIO;
2197 }
2198 }
2199 return 0;
2200 default:
2201 /* No signal voltage switch required */
2202 return 0;
2203 }
2204 }
2205 EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2206
2207 static int sdhci_card_busy(struct mmc_host *mmc)
2208 {
2209 struct sdhci_host *host = mmc_priv(mmc);
2210 u32 present_state;
2211
2212 /* Check whether DAT[0] is 0 */
2213 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2214
2215 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2216 }
2217
2218 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2219 {
2220 struct sdhci_host *host = mmc_priv(mmc);
2221 unsigned long flags;
2222
2223 spin_lock_irqsave(&host->lock, flags);
2224 host->flags |= SDHCI_HS400_TUNING;
2225 spin_unlock_irqrestore(&host->lock, flags);
2226
2227 return 0;
2228 }
2229
2230 void sdhci_start_tuning(struct sdhci_host *host)
2231 {
2232 u16 ctrl;
2233
2234 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2235 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2236 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2237 ctrl |= SDHCI_CTRL_TUNED_CLK;
2238 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2239
2240 /*
2241 * As per the Host Controller spec v3.00, tuning command
2242 * generates Buffer Read Ready interrupt, so enable that.
2243 *
2244 * Note: The spec clearly says that when tuning sequence
2245 * is being performed, the controller does not generate
2246 * interrupts other than Buffer Read Ready interrupt. But
2247 * to make sure we don't hit a controller bug, we _only_
2248 * enable Buffer Read Ready interrupt here.
2249 */
2250 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2251 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2252 }
2253 EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2254
2255 void sdhci_end_tuning(struct sdhci_host *host)
2256 {
2257 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2258 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2259 }
2260 EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2261
2262 void sdhci_reset_tuning(struct sdhci_host *host)
2263 {
2264 u16 ctrl;
2265
2266 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2267 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2268 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2269 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2270 }
2271 EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2272
2273 static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2274 {
2275 sdhci_reset_tuning(host);
2276
2277 sdhci_do_reset(host, SDHCI_RESET_CMD);
2278 sdhci_do_reset(host, SDHCI_RESET_DATA);
2279
2280 sdhci_end_tuning(host);
2281
2282 mmc_abort_tuning(host->mmc, opcode);
2283 }
2284
2285 /*
2286 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2287 * tuning command does not have a data payload (or rather the hardware does it
2288 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2289 * interrupt setup is different to other commands and there is no timeout
2290 * interrupt so special handling is needed.
2291 */
2292 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2293 {
2294 struct mmc_host *mmc = host->mmc;
2295 struct mmc_command cmd = {};
2296 struct mmc_request mrq = {};
2297 unsigned long flags;
2298 u32 b = host->sdma_boundary;
2299
2300 spin_lock_irqsave(&host->lock, flags);
2301
2302 cmd.opcode = opcode;
2303 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2304 cmd.mrq = &mrq;
2305
2306 mrq.cmd = &cmd;
2307 /*
2308 * In response to CMD19, the card sends 64 bytes of tuning
2309 * block to the Host Controller. So we set the block size
2310 * to 64 here.
2311 */
2312 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2313 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2314 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2315 else
2316 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2317
2318 /*
2319 * The tuning block is sent by the card to the host controller.
2320 * So we set the TRNS_READ bit in the Transfer Mode register.
2321 * This also takes care of setting DMA Enable and Multi Block
2322 * Select in the same register to 0.
2323 */
2324 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2325
2326 sdhci_send_command(host, &cmd);
2327
2328 host->cmd = NULL;
2329
2330 sdhci_del_timer(host, &mrq);
2331
2332 host->tuning_done = 0;
2333
2334 mmiowb();
2335 spin_unlock_irqrestore(&host->lock, flags);
2336
2337 /* Wait for Buffer Read Ready interrupt */
2338 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2339 msecs_to_jiffies(50));
2340
2341 }
2342 EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2343
2344 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2345 {
2346 int i;
2347
2348 /*
2349 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2350 * of loops reaches 40 times.
2351 */
2352 for (i = 0; i < MAX_TUNING_LOOP; i++) {
2353 u16 ctrl;
2354
2355 sdhci_send_tuning(host, opcode);
2356
2357 if (!host->tuning_done) {
2358 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2359 mmc_hostname(host->mmc));
2360 sdhci_abort_tuning(host, opcode);
2361 return -ETIMEDOUT;
2362 }
2363
2364 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2365 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2366 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2367 return 0; /* Success! */
2368 break;
2369 }
2370
2371 /* Spec does not require a delay between tuning cycles */
2372 if (host->tuning_delay > 0)
2373 mdelay(host->tuning_delay);
2374 }
2375
2376 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2377 mmc_hostname(host->mmc));
2378 sdhci_reset_tuning(host);
2379 return -EAGAIN;
2380 }
2381
2382 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2383 {
2384 struct sdhci_host *host = mmc_priv(mmc);
2385 int err = 0;
2386 unsigned int tuning_count = 0;
2387 bool hs400_tuning;
2388
2389 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2390
2391 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2392 tuning_count = host->tuning_count;
2393
2394 /*
2395 * The Host Controller needs tuning in case of SDR104 and DDR50
2396 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2397 * the Capabilities register.
2398 * If the Host Controller supports the HS200 mode then the
2399 * tuning function has to be executed.
2400 */
2401 switch (host->timing) {
2402 /* HS400 tuning is done in HS200 mode */
2403 case MMC_TIMING_MMC_HS400:
2404 err = -EINVAL;
2405 goto out;
2406
2407 case MMC_TIMING_MMC_HS200:
2408 /*
2409 * Periodic re-tuning for HS400 is not expected to be needed, so
2410 * disable it here.
2411 */
2412 if (hs400_tuning)
2413 tuning_count = 0;
2414 break;
2415
2416 case MMC_TIMING_UHS_SDR104:
2417 case MMC_TIMING_UHS_DDR50:
2418 break;
2419
2420 case MMC_TIMING_UHS_SDR50:
2421 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2422 break;
2423 /* FALLTHROUGH */
2424
2425 default:
2426 goto out;
2427 }
2428
2429 if (host->ops->platform_execute_tuning) {
2430 err = host->ops->platform_execute_tuning(host, opcode);
2431 goto out;
2432 }
2433
2434 host->mmc->retune_period = tuning_count;
2435
2436 if (host->tuning_delay < 0)
2437 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2438
2439 sdhci_start_tuning(host);
2440
2441 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2442
2443 sdhci_end_tuning(host);
2444 out:
2445 host->flags &= ~SDHCI_HS400_TUNING;
2446
2447 return err;
2448 }
2449 EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2450
2451 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2452 {
2453 /* Host Controller v3.00 defines preset value registers */
2454 if (host->version < SDHCI_SPEC_300)
2455 return;
2456
2457 /*
2458 * We only enable or disable Preset Value if they are not already
2459 * enabled or disabled respectively. Otherwise, we bail out.
2460 */
2461 if (host->preset_enabled != enable) {
2462 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2463
2464 if (enable)
2465 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2466 else
2467 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2468
2469 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2470
2471 if (enable)
2472 host->flags |= SDHCI_PV_ENABLED;
2473 else
2474 host->flags &= ~SDHCI_PV_ENABLED;
2475
2476 host->preset_enabled = enable;
2477 }
2478 }
2479
2480 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2481 int err)
2482 {
2483 struct sdhci_host *host = mmc_priv(mmc);
2484 struct mmc_data *data = mrq->data;
2485
2486 if (data->host_cookie != COOKIE_UNMAPPED)
2487 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2488 mmc_get_dma_dir(data));
2489
2490 data->host_cookie = COOKIE_UNMAPPED;
2491 }
2492
2493 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2494 {
2495 struct sdhci_host *host = mmc_priv(mmc);
2496
2497 mrq->data->host_cookie = COOKIE_UNMAPPED;
2498
2499 /*
2500 * No pre-mapping in the pre hook if we're using the bounce buffer,
2501 * for that we would need two bounce buffers since one buffer is
2502 * in flight when this is getting called.
2503 */
2504 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2505 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2506 }
2507
2508 static inline bool sdhci_has_requests(struct sdhci_host *host)
2509 {
2510 return host->cmd || host->data_cmd;
2511 }
2512
2513 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2514 {
2515 if (host->data_cmd) {
2516 host->data_cmd->error = err;
2517 sdhci_finish_mrq(host, host->data_cmd->mrq);
2518 }
2519
2520 if (host->cmd) {
2521 host->cmd->error = err;
2522 sdhci_finish_mrq(host, host->cmd->mrq);
2523 }
2524 }
2525
2526 static void sdhci_card_event(struct mmc_host *mmc)
2527 {
2528 struct sdhci_host *host = mmc_priv(mmc);
2529 unsigned long flags;
2530 int present;
2531
2532 /* First check if client has provided their own card event */
2533 if (host->ops->card_event)
2534 host->ops->card_event(host);
2535
2536 present = mmc->ops->get_cd(mmc);
2537
2538 spin_lock_irqsave(&host->lock, flags);
2539
2540 /* Check sdhci_has_requests() first in case we are runtime suspended */
2541 if (sdhci_has_requests(host) && !present) {
2542 pr_err("%s: Card removed during transfer!\n",
2543 mmc_hostname(host->mmc));
2544 pr_err("%s: Resetting controller.\n",
2545 mmc_hostname(host->mmc));
2546
2547 sdhci_do_reset(host, SDHCI_RESET_CMD);
2548 sdhci_do_reset(host, SDHCI_RESET_DATA);
2549
2550 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2551 }
2552
2553 spin_unlock_irqrestore(&host->lock, flags);
2554 }
2555
2556 static const struct mmc_host_ops sdhci_ops = {
2557 .request = sdhci_request,
2558 .post_req = sdhci_post_req,
2559 .pre_req = sdhci_pre_req,
2560 .set_ios = sdhci_set_ios,
2561 .get_cd = sdhci_get_cd,
2562 .get_ro = sdhci_get_ro,
2563 .hw_reset = sdhci_hw_reset,
2564 .enable_sdio_irq = sdhci_enable_sdio_irq,
2565 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2566 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2567 .execute_tuning = sdhci_execute_tuning,
2568 .card_event = sdhci_card_event,
2569 .card_busy = sdhci_card_busy,
2570 };
2571
2572 /*****************************************************************************\
2573 * *
2574 * Tasklets *
2575 * *
2576 \*****************************************************************************/
2577
2578 static bool sdhci_request_done(struct sdhci_host *host)
2579 {
2580 unsigned long flags;
2581 struct mmc_request *mrq;
2582 int i;
2583
2584 spin_lock_irqsave(&host->lock, flags);
2585
2586 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2587 mrq = host->mrqs_done[i];
2588 if (mrq)
2589 break;
2590 }
2591
2592 if (!mrq) {
2593 spin_unlock_irqrestore(&host->lock, flags);
2594 return true;
2595 }
2596
2597 sdhci_del_timer(host, mrq);
2598
2599 /*
2600 * Always unmap the data buffers if they were mapped by
2601 * sdhci_prepare_data() whenever we finish with a request.
2602 * This avoids leaking DMA mappings on error.
2603 */
2604 if (host->flags & SDHCI_REQ_USE_DMA) {
2605 struct mmc_data *data = mrq->data;
2606
2607 if (data && data->host_cookie == COOKIE_MAPPED) {
2608 if (host->bounce_buffer) {
2609 /*
2610 * On reads, copy the bounced data into the
2611 * sglist
2612 */
2613 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
2614 unsigned int length = data->bytes_xfered;
2615
2616 if (length > host->bounce_buffer_size) {
2617 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
2618 mmc_hostname(host->mmc),
2619 host->bounce_buffer_size,
2620 data->bytes_xfered);
2621 /* Cap it down and continue */
2622 length = host->bounce_buffer_size;
2623 }
2624 dma_sync_single_for_cpu(
2625 host->mmc->parent,
2626 host->bounce_addr,
2627 host->bounce_buffer_size,
2628 DMA_FROM_DEVICE);
2629 sg_copy_from_buffer(data->sg,
2630 data->sg_len,
2631 host->bounce_buffer,
2632 length);
2633 } else {
2634 /* No copying, just switch ownership */
2635 dma_sync_single_for_cpu(
2636 host->mmc->parent,
2637 host->bounce_addr,
2638 host->bounce_buffer_size,
2639 mmc_get_dma_dir(data));
2640 }
2641 } else {
2642 /* Unmap the raw data */
2643 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
2644 data->sg_len,
2645 mmc_get_dma_dir(data));
2646 }
2647 data->host_cookie = COOKIE_UNMAPPED;
2648 }
2649 }
2650
2651 /*
2652 * The controller needs a reset of internal state machines
2653 * upon error conditions.
2654 */
2655 if (sdhci_needs_reset(host, mrq)) {
2656 /*
2657 * Do not finish until command and data lines are available for
2658 * reset. Note there can only be one other mrq, so it cannot
2659 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2660 * would both be null.
2661 */
2662 if (host->cmd || host->data_cmd) {
2663 spin_unlock_irqrestore(&host->lock, flags);
2664 return true;
2665 }
2666
2667 /* Some controllers need this kick or reset won't work here */
2668 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2669 /* This is to force an update */
2670 host->ops->set_clock(host, host->clock);
2671
2672 /* Spec says we should do both at the same time, but Ricoh
2673 controllers do not like that. */
2674 sdhci_do_reset(host, SDHCI_RESET_CMD);
2675 sdhci_do_reset(host, SDHCI_RESET_DATA);
2676
2677 host->pending_reset = false;
2678 }
2679
2680 if (!sdhci_has_requests(host))
2681 sdhci_led_deactivate(host);
2682
2683 host->mrqs_done[i] = NULL;
2684
2685 mmiowb();
2686 spin_unlock_irqrestore(&host->lock, flags);
2687
2688 mmc_request_done(host->mmc, mrq);
2689
2690 return false;
2691 }
2692
2693 static void sdhci_tasklet_finish(unsigned long param)
2694 {
2695 struct sdhci_host *host = (struct sdhci_host *)param;
2696
2697 while (!sdhci_request_done(host))
2698 ;
2699 }
2700
2701 static void sdhci_timeout_timer(struct timer_list *t)
2702 {
2703 struct sdhci_host *host;
2704 unsigned long flags;
2705
2706 host = from_timer(host, t, timer);
2707
2708 spin_lock_irqsave(&host->lock, flags);
2709
2710 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2711 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2712 mmc_hostname(host->mmc));
2713 sdhci_dumpregs(host);
2714
2715 host->cmd->error = -ETIMEDOUT;
2716 sdhci_finish_mrq(host, host->cmd->mrq);
2717 }
2718
2719 mmiowb();
2720 spin_unlock_irqrestore(&host->lock, flags);
2721 }
2722
2723 static void sdhci_timeout_data_timer(struct timer_list *t)
2724 {
2725 struct sdhci_host *host;
2726 unsigned long flags;
2727
2728 host = from_timer(host, t, data_timer);
2729
2730 spin_lock_irqsave(&host->lock, flags);
2731
2732 if (host->data || host->data_cmd ||
2733 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2734 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2735 mmc_hostname(host->mmc));
2736 sdhci_dumpregs(host);
2737
2738 if (host->data) {
2739 host->data->error = -ETIMEDOUT;
2740 sdhci_finish_data(host);
2741 } else if (host->data_cmd) {
2742 host->data_cmd->error = -ETIMEDOUT;
2743 sdhci_finish_mrq(host, host->data_cmd->mrq);
2744 } else {
2745 host->cmd->error = -ETIMEDOUT;
2746 sdhci_finish_mrq(host, host->cmd->mrq);
2747 }
2748 }
2749
2750 mmiowb();
2751 spin_unlock_irqrestore(&host->lock, flags);
2752 }
2753
2754 /*****************************************************************************\
2755 * *
2756 * Interrupt handling *
2757 * *
2758 \*****************************************************************************/
2759
2760 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2761 {
2762 if (!host->cmd) {
2763 /*
2764 * SDHCI recovers from errors by resetting the cmd and data
2765 * circuits. Until that is done, there very well might be more
2766 * interrupts, so ignore them in that case.
2767 */
2768 if (host->pending_reset)
2769 return;
2770 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2771 mmc_hostname(host->mmc), (unsigned)intmask);
2772 sdhci_dumpregs(host);
2773 return;
2774 }
2775
2776 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2777 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2778 if (intmask & SDHCI_INT_TIMEOUT)
2779 host->cmd->error = -ETIMEDOUT;
2780 else
2781 host->cmd->error = -EILSEQ;
2782
2783 /*
2784 * If this command initiates a data phase and a response
2785 * CRC error is signalled, the card can start transferring
2786 * data - the card may have received the command without
2787 * error. We must not terminate the mmc_request early.
2788 *
2789 * If the card did not receive the command or returned an
2790 * error which prevented it sending data, the data phase
2791 * will time out.
2792 */
2793 if (host->cmd->data &&
2794 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2795 SDHCI_INT_CRC) {
2796 host->cmd = NULL;
2797 return;
2798 }
2799
2800 sdhci_finish_mrq(host, host->cmd->mrq);
2801 return;
2802 }
2803
2804 if (intmask & SDHCI_INT_RESPONSE)
2805 sdhci_finish_command(host);
2806 }
2807
2808 static void sdhci_adma_show_error(struct sdhci_host *host)
2809 {
2810 void *desc = host->adma_table;
2811
2812 sdhci_dumpregs(host);
2813
2814 while (true) {
2815 struct sdhci_adma2_64_desc *dma_desc = desc;
2816
2817 if (host->flags & SDHCI_USE_64_BIT_DMA)
2818 DBG("%p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2819 desc, le32_to_cpu(dma_desc->addr_hi),
2820 le32_to_cpu(dma_desc->addr_lo),
2821 le16_to_cpu(dma_desc->len),
2822 le16_to_cpu(dma_desc->cmd));
2823 else
2824 DBG("%p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2825 desc, le32_to_cpu(dma_desc->addr_lo),
2826 le16_to_cpu(dma_desc->len),
2827 le16_to_cpu(dma_desc->cmd));
2828
2829 desc += host->desc_sz;
2830
2831 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2832 break;
2833 }
2834 }
2835
2836 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2837 {
2838 u32 command;
2839
2840 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2841 if (intmask & SDHCI_INT_DATA_AVAIL) {
2842 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2843 if (command == MMC_SEND_TUNING_BLOCK ||
2844 command == MMC_SEND_TUNING_BLOCK_HS200) {
2845 host->tuning_done = 1;
2846 wake_up(&host->buf_ready_int);
2847 return;
2848 }
2849 }
2850
2851 if (!host->data) {
2852 struct mmc_command *data_cmd = host->data_cmd;
2853
2854 /*
2855 * The "data complete" interrupt is also used to
2856 * indicate that a busy state has ended. See comment
2857 * above in sdhci_cmd_irq().
2858 */
2859 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2860 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2861 host->data_cmd = NULL;
2862 data_cmd->error = -ETIMEDOUT;
2863 sdhci_finish_mrq(host, data_cmd->mrq);
2864 return;
2865 }
2866 if (intmask & SDHCI_INT_DATA_END) {
2867 host->data_cmd = NULL;
2868 /*
2869 * Some cards handle busy-end interrupt
2870 * before the command completed, so make
2871 * sure we do things in the proper order.
2872 */
2873 if (host->cmd == data_cmd)
2874 return;
2875
2876 sdhci_finish_mrq(host, data_cmd->mrq);
2877 return;
2878 }
2879 }
2880
2881 /*
2882 * SDHCI recovers from errors by resetting the cmd and data
2883 * circuits. Until that is done, there very well might be more
2884 * interrupts, so ignore them in that case.
2885 */
2886 if (host->pending_reset)
2887 return;
2888
2889 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2890 mmc_hostname(host->mmc), (unsigned)intmask);
2891 sdhci_dumpregs(host);
2892
2893 return;
2894 }
2895
2896 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2897 host->data->error = -ETIMEDOUT;
2898 else if (intmask & SDHCI_INT_DATA_END_BIT)
2899 host->data->error = -EILSEQ;
2900 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2901 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2902 != MMC_BUS_TEST_R)
2903 host->data->error = -EILSEQ;
2904 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2905 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2906 sdhci_adma_show_error(host);
2907 host->data->error = -EIO;
2908 if (host->ops->adma_workaround)
2909 host->ops->adma_workaround(host, intmask);
2910 }
2911
2912 if (host->data->error)
2913 sdhci_finish_data(host);
2914 else {
2915 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2916 sdhci_transfer_pio(host);
2917
2918 /*
2919 * We currently don't do anything fancy with DMA
2920 * boundaries, but as we can't disable the feature
2921 * we need to at least restart the transfer.
2922 *
2923 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2924 * should return a valid address to continue from, but as
2925 * some controllers are faulty, don't trust them.
2926 */
2927 if (intmask & SDHCI_INT_DMA_END) {
2928 dma_addr_t dmastart, dmanow;
2929
2930 dmastart = sdhci_sdma_address(host);
2931 dmanow = dmastart + host->data->bytes_xfered;
2932 /*
2933 * Force update to the next DMA block boundary.
2934 */
2935 dmanow = (dmanow &
2936 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2937 SDHCI_DEFAULT_BOUNDARY_SIZE;
2938 host->data->bytes_xfered = dmanow - dmastart;
2939 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
2940 &dmastart, host->data->bytes_xfered, &dmanow);
2941 sdhci_set_sdma_addr(host, dmanow);
2942 }
2943
2944 if (intmask & SDHCI_INT_DATA_END) {
2945 if (host->cmd == host->data_cmd) {
2946 /*
2947 * Data managed to finish before the
2948 * command completed. Make sure we do
2949 * things in the proper order.
2950 */
2951 host->data_early = 1;
2952 } else {
2953 sdhci_finish_data(host);
2954 }
2955 }
2956 }
2957 }
2958
2959 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2960 {
2961 irqreturn_t result = IRQ_NONE;
2962 struct sdhci_host *host = dev_id;
2963 u32 intmask, mask, unexpected = 0;
2964 int max_loops = 16;
2965
2966 spin_lock(&host->lock);
2967
2968 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2969 spin_unlock(&host->lock);
2970 return IRQ_NONE;
2971 }
2972
2973 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2974 if (!intmask || intmask == 0xffffffff) {
2975 result = IRQ_NONE;
2976 goto out;
2977 }
2978
2979 do {
2980 DBG("IRQ status 0x%08x\n", intmask);
2981
2982 if (host->ops->irq) {
2983 intmask = host->ops->irq(host, intmask);
2984 if (!intmask)
2985 goto cont;
2986 }
2987
2988 /* Clear selected interrupts. */
2989 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2990 SDHCI_INT_BUS_POWER);
2991 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2992
2993 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2994 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2995 SDHCI_CARD_PRESENT;
2996
2997 /*
2998 * There is a observation on i.mx esdhc. INSERT
2999 * bit will be immediately set again when it gets
3000 * cleared, if a card is inserted. We have to mask
3001 * the irq to prevent interrupt storm which will
3002 * freeze the system. And the REMOVE gets the
3003 * same situation.
3004 *
3005 * More testing are needed here to ensure it works
3006 * for other platforms though.
3007 */
3008 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3009 SDHCI_INT_CARD_REMOVE);
3010 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3011 SDHCI_INT_CARD_INSERT;
3012 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3013 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3014
3015 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3016 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3017
3018 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3019 SDHCI_INT_CARD_REMOVE);
3020 result = IRQ_WAKE_THREAD;
3021 }
3022
3023 if (intmask & SDHCI_INT_CMD_MASK)
3024 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
3025
3026 if (intmask & SDHCI_INT_DATA_MASK)
3027 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3028
3029 if (intmask & SDHCI_INT_BUS_POWER)
3030 pr_err("%s: Card is consuming too much power!\n",
3031 mmc_hostname(host->mmc));
3032
3033 if (intmask & SDHCI_INT_RETUNE)
3034 mmc_retune_needed(host->mmc);
3035
3036 if ((intmask & SDHCI_INT_CARD_INT) &&
3037 (host->ier & SDHCI_INT_CARD_INT)) {
3038 sdhci_enable_sdio_irq_nolock(host, false);
3039 host->thread_isr |= SDHCI_INT_CARD_INT;
3040 result = IRQ_WAKE_THREAD;
3041 }
3042
3043 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3044 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3045 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3046 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3047
3048 if (intmask) {
3049 unexpected |= intmask;
3050 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3051 }
3052 cont:
3053 if (result == IRQ_NONE)
3054 result = IRQ_HANDLED;
3055
3056 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3057 } while (intmask && --max_loops);
3058 out:
3059 spin_unlock(&host->lock);
3060
3061 if (unexpected) {
3062 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3063 mmc_hostname(host->mmc), unexpected);
3064 sdhci_dumpregs(host);
3065 }
3066
3067 return result;
3068 }
3069
3070 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3071 {
3072 struct sdhci_host *host = dev_id;
3073 unsigned long flags;
3074 u32 isr;
3075
3076 spin_lock_irqsave(&host->lock, flags);
3077 isr = host->thread_isr;
3078 host->thread_isr = 0;
3079 spin_unlock_irqrestore(&host->lock, flags);
3080
3081 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3082 struct mmc_host *mmc = host->mmc;
3083
3084 mmc->ops->card_event(mmc);
3085 mmc_detect_change(mmc, msecs_to_jiffies(200));
3086 }
3087
3088 if (isr & SDHCI_INT_CARD_INT) {
3089 sdio_run_irqs(host->mmc);
3090
3091 spin_lock_irqsave(&host->lock, flags);
3092 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3093 sdhci_enable_sdio_irq_nolock(host, true);
3094 spin_unlock_irqrestore(&host->lock, flags);
3095 }
3096
3097 return isr ? IRQ_HANDLED : IRQ_NONE;
3098 }
3099
3100 /*****************************************************************************\
3101 * *
3102 * Suspend/resume *
3103 * *
3104 \*****************************************************************************/
3105
3106 #ifdef CONFIG_PM
3107
3108 static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3109 {
3110 return mmc_card_is_removable(host->mmc) &&
3111 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3112 !mmc_can_gpio_cd(host->mmc);
3113 }
3114
3115 /*
3116 * To enable wakeup events, the corresponding events have to be enabled in
3117 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3118 * Table' in the SD Host Controller Standard Specification.
3119 * It is useless to restore SDHCI_INT_ENABLE state in
3120 * sdhci_disable_irq_wakeups() since it will be set by
3121 * sdhci_enable_card_detection() or sdhci_init().
3122 */
3123 static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3124 {
3125 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3126 SDHCI_WAKE_ON_INT;
3127 u32 irq_val = 0;
3128 u8 wake_val = 0;
3129 u8 val;
3130
3131 if (sdhci_cd_irq_can_wakeup(host)) {
3132 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3133 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3134 }
3135
3136 if (mmc_card_wake_sdio_irq(host->mmc)) {
3137 wake_val |= SDHCI_WAKE_ON_INT;
3138 irq_val |= SDHCI_INT_CARD_INT;
3139 }
3140
3141 if (!irq_val)
3142 return false;
3143
3144 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3145 val &= ~mask;
3146 val |= wake_val;
3147 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3148
3149 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3150
3151 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3152
3153 return host->irq_wake_enabled;
3154 }
3155
3156 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3157 {
3158 u8 val;
3159 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3160 | SDHCI_WAKE_ON_INT;
3161
3162 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3163 val &= ~mask;
3164 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3165
3166 disable_irq_wake(host->irq);
3167
3168 host->irq_wake_enabled = false;
3169 }
3170
3171 int sdhci_suspend_host(struct sdhci_host *host)
3172 {
3173 sdhci_disable_card_detection(host);
3174
3175 mmc_retune_timer_stop(host->mmc);
3176
3177 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3178 !sdhci_enable_irq_wakeups(host)) {
3179 host->ier = 0;
3180 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3181 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3182 free_irq(host->irq, host);
3183 }
3184
3185 return 0;
3186 }
3187
3188 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3189
3190 int sdhci_resume_host(struct sdhci_host *host)
3191 {
3192 struct mmc_host *mmc = host->mmc;
3193 int ret = 0;
3194
3195 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3196 if (host->ops->enable_dma)
3197 host->ops->enable_dma(host);
3198 }
3199
3200 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3201 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3202 /* Card keeps power but host controller does not */
3203 sdhci_init(host, 0);
3204 host->pwr = 0;
3205 host->clock = 0;
3206 mmc->ops->set_ios(mmc, &mmc->ios);
3207 } else {
3208 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3209 mmiowb();
3210 }
3211
3212 if (host->irq_wake_enabled) {
3213 sdhci_disable_irq_wakeups(host);
3214 } else {
3215 ret = request_threaded_irq(host->irq, sdhci_irq,
3216 sdhci_thread_irq, IRQF_SHARED,
3217 mmc_hostname(host->mmc), host);
3218 if (ret)
3219 return ret;
3220 }
3221
3222 sdhci_enable_card_detection(host);
3223
3224 return ret;
3225 }
3226
3227 EXPORT_SYMBOL_GPL(sdhci_resume_host);
3228
3229 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3230 {
3231 unsigned long flags;
3232
3233 mmc_retune_timer_stop(host->mmc);
3234
3235 spin_lock_irqsave(&host->lock, flags);
3236 host->ier &= SDHCI_INT_CARD_INT;
3237 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3238 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3239 spin_unlock_irqrestore(&host->lock, flags);
3240
3241 synchronize_hardirq(host->irq);
3242
3243 spin_lock_irqsave(&host->lock, flags);
3244 host->runtime_suspended = true;
3245 spin_unlock_irqrestore(&host->lock, flags);
3246
3247 return 0;
3248 }
3249 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3250
3251 int sdhci_runtime_resume_host(struct sdhci_host *host)
3252 {
3253 struct mmc_host *mmc = host->mmc;
3254 unsigned long flags;
3255 int host_flags = host->flags;
3256
3257 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3258 if (host->ops->enable_dma)
3259 host->ops->enable_dma(host);
3260 }
3261
3262 sdhci_init(host, 0);
3263
3264 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3265 mmc->ios.power_mode != MMC_POWER_OFF) {
3266 /* Force clock and power re-program */
3267 host->pwr = 0;
3268 host->clock = 0;
3269 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3270 mmc->ops->set_ios(mmc, &mmc->ios);
3271
3272 if ((host_flags & SDHCI_PV_ENABLED) &&
3273 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3274 spin_lock_irqsave(&host->lock, flags);
3275 sdhci_enable_preset_value(host, true);
3276 spin_unlock_irqrestore(&host->lock, flags);
3277 }
3278
3279 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3280 mmc->ops->hs400_enhanced_strobe)
3281 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3282 }
3283
3284 spin_lock_irqsave(&host->lock, flags);
3285
3286 host->runtime_suspended = false;
3287
3288 /* Enable SDIO IRQ */
3289 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3290 sdhci_enable_sdio_irq_nolock(host, true);
3291
3292 /* Enable Card Detection */
3293 sdhci_enable_card_detection(host);
3294
3295 spin_unlock_irqrestore(&host->lock, flags);
3296
3297 return 0;
3298 }
3299 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3300
3301 #endif /* CONFIG_PM */
3302
3303 /*****************************************************************************\
3304 * *
3305 * Command Queue Engine (CQE) helpers *
3306 * *
3307 \*****************************************************************************/
3308
3309 void sdhci_cqe_enable(struct mmc_host *mmc)
3310 {
3311 struct sdhci_host *host = mmc_priv(mmc);
3312 unsigned long flags;
3313 u8 ctrl;
3314
3315 spin_lock_irqsave(&host->lock, flags);
3316
3317 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3318 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3319 if (host->flags & SDHCI_USE_64_BIT_DMA)
3320 ctrl |= SDHCI_CTRL_ADMA64;
3321 else
3322 ctrl |= SDHCI_CTRL_ADMA32;
3323 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3324
3325 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3326 SDHCI_BLOCK_SIZE);
3327
3328 /* Set maximum timeout */
3329 sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
3330
3331 host->ier = host->cqe_ier;
3332
3333 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3334 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3335
3336 host->cqe_on = true;
3337
3338 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3339 mmc_hostname(mmc), host->ier,
3340 sdhci_readl(host, SDHCI_INT_STATUS));
3341
3342 mmiowb();
3343 spin_unlock_irqrestore(&host->lock, flags);
3344 }
3345 EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3346
3347 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3348 {
3349 struct sdhci_host *host = mmc_priv(mmc);
3350 unsigned long flags;
3351
3352 spin_lock_irqsave(&host->lock, flags);
3353
3354 sdhci_set_default_irqs(host);
3355
3356 host->cqe_on = false;
3357
3358 if (recovery) {
3359 sdhci_do_reset(host, SDHCI_RESET_CMD);
3360 sdhci_do_reset(host, SDHCI_RESET_DATA);
3361 }
3362
3363 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3364 mmc_hostname(mmc), host->ier,
3365 sdhci_readl(host, SDHCI_INT_STATUS));
3366
3367 mmiowb();
3368 spin_unlock_irqrestore(&host->lock, flags);
3369 }
3370 EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3371
3372 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3373 int *data_error)
3374 {
3375 u32 mask;
3376
3377 if (!host->cqe_on)
3378 return false;
3379
3380 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3381 *cmd_error = -EILSEQ;
3382 else if (intmask & SDHCI_INT_TIMEOUT)
3383 *cmd_error = -ETIMEDOUT;
3384 else
3385 *cmd_error = 0;
3386
3387 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3388 *data_error = -EILSEQ;
3389 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3390 *data_error = -ETIMEDOUT;
3391 else if (intmask & SDHCI_INT_ADMA_ERROR)
3392 *data_error = -EIO;
3393 else
3394 *data_error = 0;
3395
3396 /* Clear selected interrupts. */
3397 mask = intmask & host->cqe_ier;
3398 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3399
3400 if (intmask & SDHCI_INT_BUS_POWER)
3401 pr_err("%s: Card is consuming too much power!\n",
3402 mmc_hostname(host->mmc));
3403
3404 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3405 if (intmask) {
3406 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3407 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3408 mmc_hostname(host->mmc), intmask);
3409 sdhci_dumpregs(host);
3410 }
3411
3412 return true;
3413 }
3414 EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3415
3416 /*****************************************************************************\
3417 * *
3418 * Device allocation/registration *
3419 * *
3420 \*****************************************************************************/
3421
3422 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3423 size_t priv_size)
3424 {
3425 struct mmc_host *mmc;
3426 struct sdhci_host *host;
3427
3428 WARN_ON(dev == NULL);
3429
3430 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3431 if (!mmc)
3432 return ERR_PTR(-ENOMEM);
3433
3434 host = mmc_priv(mmc);
3435 host->mmc = mmc;
3436 host->mmc_host_ops = sdhci_ops;
3437 mmc->ops = &host->mmc_host_ops;
3438
3439 host->flags = SDHCI_SIGNALING_330;
3440
3441 host->cqe_ier = SDHCI_CQE_INT_MASK;
3442 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3443
3444 host->tuning_delay = -1;
3445
3446 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3447
3448 /*
3449 * The DMA table descriptor count is calculated as the maximum
3450 * number of segments times 2, to allow for an alignment
3451 * descriptor for each segment, plus 1 for a nop end descriptor.
3452 */
3453 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3454
3455 return host;
3456 }
3457
3458 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3459
3460 static int sdhci_set_dma_mask(struct sdhci_host *host)
3461 {
3462 struct mmc_host *mmc = host->mmc;
3463 struct device *dev = mmc_dev(mmc);
3464 int ret = -EINVAL;
3465
3466 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3467 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3468
3469 /* Try 64-bit mask if hardware is capable of it */
3470 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3471 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3472 if (ret) {
3473 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3474 mmc_hostname(mmc));
3475 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3476 }
3477 }
3478
3479 /* 32-bit mask as default & fallback */
3480 if (ret) {
3481 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3482 if (ret)
3483 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3484 mmc_hostname(mmc));
3485 }
3486
3487 return ret;
3488 }
3489
3490 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3491 {
3492 u16 v;
3493 u64 dt_caps_mask = 0;
3494 u64 dt_caps = 0;
3495
3496 if (host->read_caps)
3497 return;
3498
3499 host->read_caps = true;
3500
3501 if (debug_quirks)
3502 host->quirks = debug_quirks;
3503
3504 if (debug_quirks2)
3505 host->quirks2 = debug_quirks2;
3506
3507 sdhci_do_reset(host, SDHCI_RESET_ALL);
3508
3509 if (host->v4_mode)
3510 sdhci_do_enable_v4_mode(host);
3511
3512 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3513 "sdhci-caps-mask", &dt_caps_mask);
3514 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3515 "sdhci-caps", &dt_caps);
3516
3517 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3518 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3519
3520 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3521 return;
3522
3523 if (caps) {
3524 host->caps = *caps;
3525 } else {
3526 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3527 host->caps &= ~lower_32_bits(dt_caps_mask);
3528 host->caps |= lower_32_bits(dt_caps);
3529 }
3530
3531 if (host->version < SDHCI_SPEC_300)
3532 return;
3533
3534 if (caps1) {
3535 host->caps1 = *caps1;
3536 } else {
3537 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3538 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3539 host->caps1 |= upper_32_bits(dt_caps);
3540 }
3541 }
3542 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3543
3544 static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3545 {
3546 struct mmc_host *mmc = host->mmc;
3547 unsigned int max_blocks;
3548 unsigned int bounce_size;
3549 int ret;
3550
3551 /*
3552 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
3553 * has diminishing returns, this is probably because SD/MMC
3554 * cards are usually optimized to handle this size of requests.
3555 */
3556 bounce_size = SZ_64K;
3557 /*
3558 * Adjust downwards to maximum request size if this is less
3559 * than our segment size, else hammer down the maximum
3560 * request size to the maximum buffer size.
3561 */
3562 if (mmc->max_req_size < bounce_size)
3563 bounce_size = mmc->max_req_size;
3564 max_blocks = bounce_size / 512;
3565
3566 /*
3567 * When we just support one segment, we can get significant
3568 * speedups by the help of a bounce buffer to group scattered
3569 * reads/writes together.
3570 */
3571 host->bounce_buffer = devm_kmalloc(mmc->parent,
3572 bounce_size,
3573 GFP_KERNEL);
3574 if (!host->bounce_buffer) {
3575 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
3576 mmc_hostname(mmc),
3577 bounce_size);
3578 /*
3579 * Exiting with zero here makes sure we proceed with
3580 * mmc->max_segs == 1.
3581 */
3582 return 0;
3583 }
3584
3585 host->bounce_addr = dma_map_single(mmc->parent,
3586 host->bounce_buffer,
3587 bounce_size,
3588 DMA_BIDIRECTIONAL);
3589 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3590 if (ret)
3591 /* Again fall back to max_segs == 1 */
3592 return 0;
3593 host->bounce_buffer_size = bounce_size;
3594
3595 /* Lie about this since we're bouncing */
3596 mmc->max_segs = max_blocks;
3597 mmc->max_seg_size = bounce_size;
3598 mmc->max_req_size = bounce_size;
3599
3600 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3601 mmc_hostname(mmc), max_blocks, bounce_size);
3602
3603 return 0;
3604 }
3605
3606 static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
3607 {
3608 /*
3609 * According to SD Host Controller spec v4.10, bit[27] added from
3610 * version 4.10 in Capabilities Register is used as 64-bit System
3611 * Address support for V4 mode.
3612 */
3613 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
3614 return host->caps & SDHCI_CAN_64BIT_V4;
3615
3616 return host->caps & SDHCI_CAN_64BIT;
3617 }
3618
3619 int sdhci_setup_host(struct sdhci_host *host)
3620 {
3621 struct mmc_host *mmc;
3622 u32 max_current_caps;
3623 unsigned int ocr_avail;
3624 unsigned int override_timeout_clk;
3625 u32 max_clk;
3626 int ret;
3627
3628 WARN_ON(host == NULL);
3629 if (host == NULL)
3630 return -EINVAL;
3631
3632 mmc = host->mmc;
3633
3634 /*
3635 * If there are external regulators, get them. Note this must be done
3636 * early before resetting the host and reading the capabilities so that
3637 * the host can take the appropriate action if regulators are not
3638 * available.
3639 */
3640 ret = mmc_regulator_get_supply(mmc);
3641 if (ret)
3642 return ret;
3643
3644 DBG("Version: 0x%08x | Present: 0x%08x\n",
3645 sdhci_readw(host, SDHCI_HOST_VERSION),
3646 sdhci_readl(host, SDHCI_PRESENT_STATE));
3647 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
3648 sdhci_readl(host, SDHCI_CAPABILITIES),
3649 sdhci_readl(host, SDHCI_CAPABILITIES_1));
3650
3651 sdhci_read_caps(host);
3652
3653 override_timeout_clk = host->timeout_clk;
3654
3655 if (host->version > SDHCI_SPEC_420) {
3656 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3657 mmc_hostname(mmc), host->version);
3658 }
3659
3660 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3661 host->flags |= SDHCI_USE_SDMA;
3662 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3663 DBG("Controller doesn't have SDMA capability\n");
3664 else
3665 host->flags |= SDHCI_USE_SDMA;
3666
3667 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3668 (host->flags & SDHCI_USE_SDMA)) {
3669 DBG("Disabling DMA as it is marked broken\n");
3670 host->flags &= ~SDHCI_USE_SDMA;
3671 }
3672
3673 if ((host->version >= SDHCI_SPEC_200) &&
3674 (host->caps & SDHCI_CAN_DO_ADMA2))
3675 host->flags |= SDHCI_USE_ADMA;
3676
3677 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3678 (host->flags & SDHCI_USE_ADMA)) {
3679 DBG("Disabling ADMA as it is marked broken\n");
3680 host->flags &= ~SDHCI_USE_ADMA;
3681 }
3682
3683 /*
3684 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3685 * and *must* do 64-bit DMA. A driver has the opportunity to change
3686 * that during the first call to ->enable_dma(). Similarly
3687 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3688 * implement.
3689 */
3690 if (sdhci_can_64bit_dma(host))
3691 host->flags |= SDHCI_USE_64_BIT_DMA;
3692
3693 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3694 ret = sdhci_set_dma_mask(host);
3695
3696 if (!ret && host->ops->enable_dma)
3697 ret = host->ops->enable_dma(host);
3698
3699 if (ret) {
3700 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3701 mmc_hostname(mmc));
3702 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3703
3704 ret = 0;
3705 }
3706 }
3707
3708 /* SDMA does not support 64-bit DMA if v4 mode not set */
3709 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
3710 host->flags &= ~SDHCI_USE_SDMA;
3711
3712 if (host->flags & SDHCI_USE_ADMA) {
3713 dma_addr_t dma;
3714 void *buf;
3715
3716 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3717 host->adma_table_sz = host->adma_table_cnt *
3718 SDHCI_ADMA2_64_DESC_SZ(host);
3719 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
3720 } else {
3721 host->adma_table_sz = host->adma_table_cnt *
3722 SDHCI_ADMA2_32_DESC_SZ;
3723 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3724 }
3725
3726 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3727 /*
3728 * Use zalloc to zero the reserved high 32-bits of 128-bit
3729 * descriptors so that they never need to be written.
3730 */
3731 buf = dma_zalloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3732 host->adma_table_sz, &dma, GFP_KERNEL);
3733 if (!buf) {
3734 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3735 mmc_hostname(mmc));
3736 host->flags &= ~SDHCI_USE_ADMA;
3737 } else if ((dma + host->align_buffer_sz) &
3738 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3739 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3740 mmc_hostname(mmc));
3741 host->flags &= ~SDHCI_USE_ADMA;
3742 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3743 host->adma_table_sz, buf, dma);
3744 } else {
3745 host->align_buffer = buf;
3746 host->align_addr = dma;
3747
3748 host->adma_table = buf + host->align_buffer_sz;
3749 host->adma_addr = dma + host->align_buffer_sz;
3750 }
3751 }
3752
3753 /*
3754 * If we use DMA, then it's up to the caller to set the DMA
3755 * mask, but PIO does not need the hw shim so we set a new
3756 * mask here in that case.
3757 */
3758 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3759 host->dma_mask = DMA_BIT_MASK(64);
3760 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3761 }
3762
3763 if (host->version >= SDHCI_SPEC_300)
3764 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3765 >> SDHCI_CLOCK_BASE_SHIFT;
3766 else
3767 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3768 >> SDHCI_CLOCK_BASE_SHIFT;
3769
3770 host->max_clk *= 1000000;
3771 if (host->max_clk == 0 || host->quirks &
3772 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3773 if (!host->ops->get_max_clock) {
3774 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3775 mmc_hostname(mmc));
3776 ret = -ENODEV;
3777 goto undma;
3778 }
3779 host->max_clk = host->ops->get_max_clock(host);
3780 }
3781
3782 /*
3783 * In case of Host Controller v3.00, find out whether clock
3784 * multiplier is supported.
3785 */
3786 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3787 SDHCI_CLOCK_MUL_SHIFT;
3788
3789 /*
3790 * In case the value in Clock Multiplier is 0, then programmable
3791 * clock mode is not supported, otherwise the actual clock
3792 * multiplier is one more than the value of Clock Multiplier
3793 * in the Capabilities Register.
3794 */
3795 if (host->clk_mul)
3796 host->clk_mul += 1;
3797
3798 /*
3799 * Set host parameters.
3800 */
3801 max_clk = host->max_clk;
3802
3803 if (host->ops->get_min_clock)
3804 mmc->f_min = host->ops->get_min_clock(host);
3805 else if (host->version >= SDHCI_SPEC_300) {
3806 if (host->clk_mul) {
3807 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3808 max_clk = host->max_clk * host->clk_mul;
3809 } else
3810 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3811 } else
3812 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3813
3814 if (!mmc->f_max || mmc->f_max > max_clk)
3815 mmc->f_max = max_clk;
3816
3817 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3818 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3819 SDHCI_TIMEOUT_CLK_SHIFT;
3820
3821 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3822 host->timeout_clk *= 1000;
3823
3824 if (host->timeout_clk == 0) {
3825 if (!host->ops->get_timeout_clock) {
3826 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3827 mmc_hostname(mmc));
3828 ret = -ENODEV;
3829 goto undma;
3830 }
3831
3832 host->timeout_clk =
3833 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
3834 1000);
3835 }
3836
3837 if (override_timeout_clk)
3838 host->timeout_clk = override_timeout_clk;
3839
3840 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3841 host->ops->get_max_timeout_count(host) : 1 << 27;
3842 mmc->max_busy_timeout /= host->timeout_clk;
3843 }
3844
3845 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
3846 !host->ops->get_max_timeout_count)
3847 mmc->max_busy_timeout = 0;
3848
3849 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3850 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3851
3852 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3853 host->flags |= SDHCI_AUTO_CMD12;
3854
3855 /*
3856 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
3857 * For v4 mode, SDMA may use Auto-CMD23 as well.
3858 */
3859 if ((host->version >= SDHCI_SPEC_300) &&
3860 ((host->flags & SDHCI_USE_ADMA) ||
3861 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
3862 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3863 host->flags |= SDHCI_AUTO_CMD23;
3864 DBG("Auto-CMD23 available\n");
3865 } else {
3866 DBG("Auto-CMD23 unavailable\n");
3867 }
3868
3869 /*
3870 * A controller may support 8-bit width, but the board itself
3871 * might not have the pins brought out. Boards that support
3872 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3873 * their platform code before calling sdhci_add_host(), and we
3874 * won't assume 8-bit width for hosts without that CAP.
3875 */
3876 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3877 mmc->caps |= MMC_CAP_4_BIT_DATA;
3878
3879 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3880 mmc->caps &= ~MMC_CAP_CMD23;
3881
3882 if (host->caps & SDHCI_CAN_DO_HISPD)
3883 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3884
3885 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3886 mmc_card_is_removable(mmc) &&
3887 mmc_gpio_get_cd(host->mmc) < 0)
3888 mmc->caps |= MMC_CAP_NEEDS_POLL;
3889
3890 if (!IS_ERR(mmc->supply.vqmmc)) {
3891 ret = regulator_enable(mmc->supply.vqmmc);
3892
3893 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
3894 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3895 1950000))
3896 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3897 SDHCI_SUPPORT_SDR50 |
3898 SDHCI_SUPPORT_DDR50);
3899
3900 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
3901 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
3902 3600000))
3903 host->flags &= ~SDHCI_SIGNALING_330;
3904
3905 if (ret) {
3906 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3907 mmc_hostname(mmc), ret);
3908 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3909 }
3910 }
3911
3912 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3913 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3914 SDHCI_SUPPORT_DDR50);
3915 /*
3916 * The SDHCI controller in a SoC might support HS200/HS400
3917 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
3918 * but if the board is modeled such that the IO lines are not
3919 * connected to 1.8v then HS200/HS400 cannot be supported.
3920 * Disable HS200/HS400 if the board does not have 1.8v connected
3921 * to the IO lines. (Applicable for other modes in 1.8v)
3922 */
3923 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
3924 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
3925 }
3926
3927 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3928 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3929 SDHCI_SUPPORT_DDR50))
3930 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3931
3932 /* SDR104 supports also implies SDR50 support */
3933 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3934 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3935 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3936 * field can be promoted to support HS200.
3937 */
3938 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3939 mmc->caps2 |= MMC_CAP2_HS200;
3940 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3941 mmc->caps |= MMC_CAP_UHS_SDR50;
3942 }
3943
3944 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3945 (host->caps1 & SDHCI_SUPPORT_HS400))
3946 mmc->caps2 |= MMC_CAP2_HS400;
3947
3948 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3949 (IS_ERR(mmc->supply.vqmmc) ||
3950 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3951 1300000)))
3952 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3953
3954 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3955 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3956 mmc->caps |= MMC_CAP_UHS_DDR50;
3957
3958 /* Does the host need tuning for SDR50? */
3959 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3960 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3961
3962 /* Driver Type(s) (A, C, D) supported by the host */
3963 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3964 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3965 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3966 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3967 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3968 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3969
3970 /* Initial value for re-tuning timer count */
3971 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3972 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3973
3974 /*
3975 * In case Re-tuning Timer is not disabled, the actual value of
3976 * re-tuning timer will be 2 ^ (n - 1).
3977 */
3978 if (host->tuning_count)
3979 host->tuning_count = 1 << (host->tuning_count - 1);
3980
3981 /* Re-tuning mode supported by the Host Controller */
3982 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3983 SDHCI_RETUNING_MODE_SHIFT;
3984
3985 ocr_avail = 0;
3986
3987 /*
3988 * According to SD Host Controller spec v3.00, if the Host System
3989 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3990 * the value is meaningful only if Voltage Support in the Capabilities
3991 * register is set. The actual current value is 4 times the register
3992 * value.
3993 */
3994 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3995 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3996 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3997 if (curr > 0) {
3998
3999 /* convert to SDHCI_MAX_CURRENT format */
4000 curr = curr/1000; /* convert to mA */
4001 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4002
4003 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4004 max_current_caps =
4005 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
4006 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
4007 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
4008 }
4009 }
4010
4011 if (host->caps & SDHCI_CAN_VDD_330) {
4012 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4013
4014 mmc->max_current_330 = ((max_current_caps &
4015 SDHCI_MAX_CURRENT_330_MASK) >>
4016 SDHCI_MAX_CURRENT_330_SHIFT) *
4017 SDHCI_MAX_CURRENT_MULTIPLIER;
4018 }
4019 if (host->caps & SDHCI_CAN_VDD_300) {
4020 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4021
4022 mmc->max_current_300 = ((max_current_caps &
4023 SDHCI_MAX_CURRENT_300_MASK) >>
4024 SDHCI_MAX_CURRENT_300_SHIFT) *
4025 SDHCI_MAX_CURRENT_MULTIPLIER;
4026 }
4027 if (host->caps & SDHCI_CAN_VDD_180) {
4028 ocr_avail |= MMC_VDD_165_195;
4029
4030 mmc->max_current_180 = ((max_current_caps &
4031 SDHCI_MAX_CURRENT_180_MASK) >>
4032 SDHCI_MAX_CURRENT_180_SHIFT) *
4033 SDHCI_MAX_CURRENT_MULTIPLIER;
4034 }
4035
4036 /* If OCR set by host, use it instead. */
4037 if (host->ocr_mask)
4038 ocr_avail = host->ocr_mask;
4039
4040 /* If OCR set by external regulators, give it highest prio. */
4041 if (mmc->ocr_avail)
4042 ocr_avail = mmc->ocr_avail;
4043
4044 mmc->ocr_avail = ocr_avail;
4045 mmc->ocr_avail_sdio = ocr_avail;
4046 if (host->ocr_avail_sdio)
4047 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4048 mmc->ocr_avail_sd = ocr_avail;
4049 if (host->ocr_avail_sd)
4050 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4051 else /* normal SD controllers don't support 1.8V */
4052 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4053 mmc->ocr_avail_mmc = ocr_avail;
4054 if (host->ocr_avail_mmc)
4055 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4056
4057 if (mmc->ocr_avail == 0) {
4058 pr_err("%s: Hardware doesn't report any support voltages.\n",
4059 mmc_hostname(mmc));
4060 ret = -ENODEV;
4061 goto unreg;
4062 }
4063
4064 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4065 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4066 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4067 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4068 host->flags |= SDHCI_SIGNALING_180;
4069
4070 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4071 host->flags |= SDHCI_SIGNALING_120;
4072
4073 spin_lock_init(&host->lock);
4074
4075 /*
4076 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4077 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4078 * is less anyway.
4079 */
4080 mmc->max_req_size = 524288;
4081
4082 /*
4083 * Maximum number of segments. Depends on if the hardware
4084 * can do scatter/gather or not.
4085 */
4086 if (host->flags & SDHCI_USE_ADMA) {
4087 mmc->max_segs = SDHCI_MAX_SEGS;
4088 } else if (host->flags & SDHCI_USE_SDMA) {
4089 mmc->max_segs = 1;
4090 if (swiotlb_max_segment()) {
4091 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
4092 IO_TLB_SEGSIZE;
4093 mmc->max_req_size = min(mmc->max_req_size,
4094 max_req_size);
4095 }
4096 } else { /* PIO */
4097 mmc->max_segs = SDHCI_MAX_SEGS;
4098 }
4099
4100 /*
4101 * Maximum segment size. Could be one segment with the maximum number
4102 * of bytes. When doing hardware scatter/gather, each entry cannot
4103 * be larger than 64 KiB though.
4104 */
4105 if (host->flags & SDHCI_USE_ADMA) {
4106 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4107 mmc->max_seg_size = 65535;
4108 else
4109 mmc->max_seg_size = 65536;
4110 } else {
4111 mmc->max_seg_size = mmc->max_req_size;
4112 }
4113
4114 /*
4115 * Maximum block size. This varies from controller to controller and
4116 * is specified in the capabilities register.
4117 */
4118 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4119 mmc->max_blk_size = 2;
4120 } else {
4121 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4122 SDHCI_MAX_BLOCK_SHIFT;
4123 if (mmc->max_blk_size >= 3) {
4124 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4125 mmc_hostname(mmc));
4126 mmc->max_blk_size = 0;
4127 }
4128 }
4129
4130 mmc->max_blk_size = 512 << mmc->max_blk_size;
4131
4132 /*
4133 * Maximum block count.
4134 */
4135 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4136
4137 if (mmc->max_segs == 1) {
4138 /* This may alter mmc->*_blk_* parameters */
4139 ret = sdhci_allocate_bounce_buffer(host);
4140 if (ret)
4141 return ret;
4142 }
4143
4144 return 0;
4145
4146 unreg:
4147 if (!IS_ERR(mmc->supply.vqmmc))
4148 regulator_disable(mmc->supply.vqmmc);
4149 undma:
4150 if (host->align_buffer)
4151 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4152 host->adma_table_sz, host->align_buffer,
4153 host->align_addr);
4154 host->adma_table = NULL;
4155 host->align_buffer = NULL;
4156
4157 return ret;
4158 }
4159 EXPORT_SYMBOL_GPL(sdhci_setup_host);
4160
4161 void sdhci_cleanup_host(struct sdhci_host *host)
4162 {
4163 struct mmc_host *mmc = host->mmc;
4164
4165 if (!IS_ERR(mmc->supply.vqmmc))
4166 regulator_disable(mmc->supply.vqmmc);
4167
4168 if (host->align_buffer)
4169 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4170 host->adma_table_sz, host->align_buffer,
4171 host->align_addr);
4172 host->adma_table = NULL;
4173 host->align_buffer = NULL;
4174 }
4175 EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4176
4177 int __sdhci_add_host(struct sdhci_host *host)
4178 {
4179 struct mmc_host *mmc = host->mmc;
4180 int ret;
4181
4182 /*
4183 * Init tasklets.
4184 */
4185 tasklet_init(&host->finish_tasklet,
4186 sdhci_tasklet_finish, (unsigned long)host);
4187
4188 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4189 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4190
4191 init_waitqueue_head(&host->buf_ready_int);
4192
4193 sdhci_init(host, 0);
4194
4195 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4196 IRQF_SHARED, mmc_hostname(mmc), host);
4197 if (ret) {
4198 pr_err("%s: Failed to request IRQ %d: %d\n",
4199 mmc_hostname(mmc), host->irq, ret);
4200 goto untasklet;
4201 }
4202
4203 ret = sdhci_led_register(host);
4204 if (ret) {
4205 pr_err("%s: Failed to register LED device: %d\n",
4206 mmc_hostname(mmc), ret);
4207 goto unirq;
4208 }
4209
4210 mmiowb();
4211
4212 ret = mmc_add_host(mmc);
4213 if (ret)
4214 goto unled;
4215
4216 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4217 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4218 (host->flags & SDHCI_USE_ADMA) ?
4219 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4220 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4221
4222 sdhci_enable_card_detection(host);
4223
4224 return 0;
4225
4226 unled:
4227 sdhci_led_unregister(host);
4228 unirq:
4229 sdhci_do_reset(host, SDHCI_RESET_ALL);
4230 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4231 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4232 free_irq(host->irq, host);
4233 untasklet:
4234 tasklet_kill(&host->finish_tasklet);
4235
4236 return ret;
4237 }
4238 EXPORT_SYMBOL_GPL(__sdhci_add_host);
4239
4240 int sdhci_add_host(struct sdhci_host *host)
4241 {
4242 int ret;
4243
4244 ret = sdhci_setup_host(host);
4245 if (ret)
4246 return ret;
4247
4248 ret = __sdhci_add_host(host);
4249 if (ret)
4250 goto cleanup;
4251
4252 return 0;
4253
4254 cleanup:
4255 sdhci_cleanup_host(host);
4256
4257 return ret;
4258 }
4259 EXPORT_SYMBOL_GPL(sdhci_add_host);
4260
4261 void sdhci_remove_host(struct sdhci_host *host, int dead)
4262 {
4263 struct mmc_host *mmc = host->mmc;
4264 unsigned long flags;
4265
4266 if (dead) {
4267 spin_lock_irqsave(&host->lock, flags);
4268
4269 host->flags |= SDHCI_DEVICE_DEAD;
4270
4271 if (sdhci_has_requests(host)) {
4272 pr_err("%s: Controller removed during "
4273 " transfer!\n", mmc_hostname(mmc));
4274 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4275 }
4276
4277 spin_unlock_irqrestore(&host->lock, flags);
4278 }
4279
4280 sdhci_disable_card_detection(host);
4281
4282 mmc_remove_host(mmc);
4283
4284 sdhci_led_unregister(host);
4285
4286 if (!dead)
4287 sdhci_do_reset(host, SDHCI_RESET_ALL);
4288
4289 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4290 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4291 free_irq(host->irq, host);
4292
4293 del_timer_sync(&host->timer);
4294 del_timer_sync(&host->data_timer);
4295
4296 tasklet_kill(&host->finish_tasklet);
4297
4298 if (!IS_ERR(mmc->supply.vqmmc))
4299 regulator_disable(mmc->supply.vqmmc);
4300
4301 if (host->align_buffer)
4302 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4303 host->adma_table_sz, host->align_buffer,
4304 host->align_addr);
4305
4306 host->adma_table = NULL;
4307 host->align_buffer = NULL;
4308 }
4309
4310 EXPORT_SYMBOL_GPL(sdhci_remove_host);
4311
4312 void sdhci_free_host(struct sdhci_host *host)
4313 {
4314 mmc_free_host(host->mmc);
4315 }
4316
4317 EXPORT_SYMBOL_GPL(sdhci_free_host);
4318
4319 /*****************************************************************************\
4320 * *
4321 * Driver init/exit *
4322 * *
4323 \*****************************************************************************/
4324
4325 static int __init sdhci_drv_init(void)
4326 {
4327 pr_info(DRIVER_NAME
4328 ": Secure Digital Host Controller Interface driver\n");
4329 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4330
4331 return 0;
4332 }
4333
4334 static void __exit sdhci_drv_exit(void)
4335 {
4336 }
4337
4338 module_init(sdhci_drv_init);
4339 module_exit(sdhci_drv_exit);
4340
4341 module_param(debug_quirks, uint, 0444);
4342 module_param(debug_quirks2, uint, 0444);
4343
4344 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4345 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4346 MODULE_LICENSE("GPL");
4347
4348 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4349 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
A mirror of Linus' kernel repository