2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
18 #include <power/regulator.h>
21 #include <linux/list.h>
23 #include "mmc_private.h"
25 static const unsigned int sd_au_size
[] = {
26 0, SZ_16K
/ 512, SZ_32K
/ 512,
27 SZ_64K
/ 512, SZ_128K
/ 512, SZ_256K
/ 512,
28 SZ_512K
/ 512, SZ_1M
/ 512, SZ_2M
/ 512,
29 SZ_4M
/ 512, SZ_8M
/ 512, (SZ_8M
+ SZ_4M
) / 512,
30 SZ_16M
/ 512, (SZ_16M
+ SZ_8M
) / 512, SZ_32M
/ 512, SZ_64M
/ 512,
33 #if CONFIG_IS_ENABLED(MMC_TINY)
34 static struct mmc mmc_static
;
35 struct mmc
*find_mmc_device(int dev_num
)
40 void mmc_do_preinit(void)
42 struct mmc
*m
= &mmc_static
;
43 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
44 mmc_set_preinit(m
, 1);
50 struct blk_desc
*mmc_get_blk_desc(struct mmc
*mmc
)
52 return &mmc
->block_dev
;
56 #if !CONFIG_IS_ENABLED(DM_MMC)
57 __weak
int board_mmc_getwp(struct mmc
*mmc
)
62 int mmc_getwp(struct mmc
*mmc
)
66 wp
= board_mmc_getwp(mmc
);
69 if (mmc
->cfg
->ops
->getwp
)
70 wp
= mmc
->cfg
->ops
->getwp(mmc
);
78 __weak
int board_mmc_getcd(struct mmc
*mmc
)
84 #ifdef CONFIG_MMC_TRACE
85 void mmmc_trace_before_send(struct mmc
*mmc
, struct mmc_cmd
*cmd
)
87 printf("CMD_SEND:%d\n", cmd
->cmdidx
);
88 printf("\t\tARG\t\t\t 0x%08X\n", cmd
->cmdarg
);
91 void mmmc_trace_after_send(struct mmc
*mmc
, struct mmc_cmd
*cmd
, int ret
)
97 printf("\t\tRET\t\t\t %d\n", ret
);
99 switch (cmd
->resp_type
) {
101 printf("\t\tMMC_RSP_NONE\n");
104 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
108 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
112 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
114 printf("\t\t \t\t 0x%08X \n",
116 printf("\t\t \t\t 0x%08X \n",
118 printf("\t\t \t\t 0x%08X \n",
121 printf("\t\t\t\t\tDUMPING DATA\n");
122 for (i
= 0; i
< 4; i
++) {
124 printf("\t\t\t\t\t%03d - ", i
*4);
125 ptr
= (u8
*)&cmd
->response
[i
];
127 for (j
= 0; j
< 4; j
++)
128 printf("%02X ", *ptr
--);
133 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
137 printf("\t\tERROR MMC rsp not supported\n");
143 void mmc_trace_state(struct mmc
*mmc
, struct mmc_cmd
*cmd
)
147 status
= (cmd
->response
[0] & MMC_STATUS_CURR_STATE
) >> 9;
148 printf("CURR STATE:%d\n", status
);
152 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
153 const char *mmc_mode_name(enum bus_mode mode
)
155 static const char *const names
[] = {
156 [MMC_LEGACY
] = "MMC legacy",
157 [SD_LEGACY
] = "SD Legacy",
158 [MMC_HS
] = "MMC High Speed (26MHz)",
159 [SD_HS
] = "SD High Speed (50MHz)",
160 [UHS_SDR12
] = "UHS SDR12 (25MHz)",
161 [UHS_SDR25
] = "UHS SDR25 (50MHz)",
162 [UHS_SDR50
] = "UHS SDR50 (100MHz)",
163 [UHS_SDR104
] = "UHS SDR104 (208MHz)",
164 [UHS_DDR50
] = "UHS DDR50 (50MHz)",
165 [MMC_HS_52
] = "MMC High Speed (52MHz)",
166 [MMC_DDR_52
] = "MMC DDR52 (52MHz)",
167 [MMC_HS_200
] = "HS200 (200MHz)",
170 if (mode
>= MMC_MODES_END
)
171 return "Unknown mode";
177 static uint
mmc_mode2freq(struct mmc
*mmc
, enum bus_mode mode
)
179 static const int freqs
[] = {
180 [SD_LEGACY
] = 25000000,
183 [UHS_SDR12
] = 25000000,
184 [UHS_SDR25
] = 50000000,
185 [UHS_SDR50
] = 100000000,
186 [UHS_SDR104
] = 208000000,
187 [UHS_DDR50
] = 50000000,
188 [MMC_HS_52
] = 52000000,
189 [MMC_DDR_52
] = 52000000,
190 [MMC_HS_200
] = 200000000,
193 if (mode
== MMC_LEGACY
)
194 return mmc
->legacy_speed
;
195 else if (mode
>= MMC_MODES_END
)
201 static int mmc_select_mode(struct mmc
*mmc
, enum bus_mode mode
)
203 mmc
->selected_mode
= mode
;
204 mmc
->tran_speed
= mmc_mode2freq(mmc
, mode
);
205 mmc
->ddr_mode
= mmc_is_mode_ddr(mode
);
206 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode
),
207 mmc
->tran_speed
/ 1000000);
211 #if !CONFIG_IS_ENABLED(DM_MMC)
212 int mmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
, struct mmc_data
*data
)
216 mmmc_trace_before_send(mmc
, cmd
);
217 ret
= mmc
->cfg
->ops
->send_cmd(mmc
, cmd
, data
);
218 mmmc_trace_after_send(mmc
, cmd
, ret
);
224 int mmc_send_status(struct mmc
*mmc
, int timeout
)
227 int err
, retries
= 5;
229 cmd
.cmdidx
= MMC_CMD_SEND_STATUS
;
230 cmd
.resp_type
= MMC_RSP_R1
;
231 if (!mmc_host_is_spi(mmc
))
232 cmd
.cmdarg
= mmc
->rca
<< 16;
235 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
237 if ((cmd
.response
[0] & MMC_STATUS_RDY_FOR_DATA
) &&
238 (cmd
.response
[0] & MMC_STATUS_CURR_STATE
) !=
242 if (cmd
.response
[0] & MMC_STATUS_MASK
) {
243 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
244 printf("Status Error: 0x%08X\n",
249 } else if (--retries
< 0)
258 mmc_trace_state(mmc
, &cmd
);
260 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
261 printf("Timeout waiting card ready\n");
269 int mmc_set_blocklen(struct mmc
*mmc
, int len
)
276 cmd
.cmdidx
= MMC_CMD_SET_BLOCKLEN
;
277 cmd
.resp_type
= MMC_RSP_R1
;
280 return mmc_send_cmd(mmc
, &cmd
, NULL
);
283 static int mmc_read_blocks(struct mmc
*mmc
, void *dst
, lbaint_t start
,
287 struct mmc_data data
;
290 cmd
.cmdidx
= MMC_CMD_READ_MULTIPLE_BLOCK
;
292 cmd
.cmdidx
= MMC_CMD_READ_SINGLE_BLOCK
;
294 if (mmc
->high_capacity
)
297 cmd
.cmdarg
= start
* mmc
->read_bl_len
;
299 cmd
.resp_type
= MMC_RSP_R1
;
302 data
.blocks
= blkcnt
;
303 data
.blocksize
= mmc
->read_bl_len
;
304 data
.flags
= MMC_DATA_READ
;
306 if (mmc_send_cmd(mmc
, &cmd
, &data
))
310 cmd
.cmdidx
= MMC_CMD_STOP_TRANSMISSION
;
312 cmd
.resp_type
= MMC_RSP_R1b
;
313 if (mmc_send_cmd(mmc
, &cmd
, NULL
)) {
314 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
315 printf("mmc fail to send stop cmd\n");
324 #if CONFIG_IS_ENABLED(BLK)
325 ulong
mmc_bread(struct udevice
*dev
, lbaint_t start
, lbaint_t blkcnt
, void *dst
)
327 ulong
mmc_bread(struct blk_desc
*block_dev
, lbaint_t start
, lbaint_t blkcnt
,
331 #if CONFIG_IS_ENABLED(BLK)
332 struct blk_desc
*block_dev
= dev_get_uclass_platdata(dev
);
334 int dev_num
= block_dev
->devnum
;
336 lbaint_t cur
, blocks_todo
= blkcnt
;
341 struct mmc
*mmc
= find_mmc_device(dev_num
);
345 if (CONFIG_IS_ENABLED(MMC_TINY
))
346 err
= mmc_switch_part(mmc
, block_dev
->hwpart
);
348 err
= blk_dselect_hwpart(block_dev
, block_dev
->hwpart
);
353 if ((start
+ blkcnt
) > block_dev
->lba
) {
354 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
355 printf("MMC: block number 0x" LBAF
" exceeds max(0x" LBAF
")\n",
356 start
+ blkcnt
, block_dev
->lba
);
361 if (mmc_set_blocklen(mmc
, mmc
->read_bl_len
)) {
362 debug("%s: Failed to set blocklen\n", __func__
);
367 cur
= (blocks_todo
> mmc
->cfg
->b_max
) ?
368 mmc
->cfg
->b_max
: blocks_todo
;
369 if (mmc_read_blocks(mmc
, dst
, start
, cur
) != cur
) {
370 debug("%s: Failed to read blocks\n", __func__
);
375 dst
+= cur
* mmc
->read_bl_len
;
376 } while (blocks_todo
> 0);
381 static int mmc_go_idle(struct mmc
*mmc
)
388 cmd
.cmdidx
= MMC_CMD_GO_IDLE_STATE
;
390 cmd
.resp_type
= MMC_RSP_NONE
;
392 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
402 static int sd_send_op_cond(struct mmc
*mmc
)
409 cmd
.cmdidx
= MMC_CMD_APP_CMD
;
410 cmd
.resp_type
= MMC_RSP_R1
;
413 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
418 cmd
.cmdidx
= SD_CMD_APP_SEND_OP_COND
;
419 cmd
.resp_type
= MMC_RSP_R3
;
422 * Most cards do not answer if some reserved bits
423 * in the ocr are set. However, Some controller
424 * can set bit 7 (reserved for low voltages), but
425 * how to manage low voltages SD card is not yet
428 cmd
.cmdarg
= mmc_host_is_spi(mmc
) ? 0 :
429 (mmc
->cfg
->voltages
& 0xff8000);
431 if (mmc
->version
== SD_VERSION_2
)
432 cmd
.cmdarg
|= OCR_HCS
;
434 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
439 if (cmd
.response
[0] & OCR_BUSY
)
448 if (mmc
->version
!= SD_VERSION_2
)
449 mmc
->version
= SD_VERSION_1_0
;
451 if (mmc_host_is_spi(mmc
)) { /* read OCR for spi */
452 cmd
.cmdidx
= MMC_CMD_SPI_READ_OCR
;
453 cmd
.resp_type
= MMC_RSP_R3
;
456 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
462 mmc
->ocr
= cmd
.response
[0];
464 mmc
->high_capacity
= ((mmc
->ocr
& OCR_HCS
) == OCR_HCS
);
470 static int mmc_send_op_cond_iter(struct mmc
*mmc
, int use_arg
)
475 cmd
.cmdidx
= MMC_CMD_SEND_OP_COND
;
476 cmd
.resp_type
= MMC_RSP_R3
;
478 if (use_arg
&& !mmc_host_is_spi(mmc
))
479 cmd
.cmdarg
= OCR_HCS
|
480 (mmc
->cfg
->voltages
&
481 (mmc
->ocr
& OCR_VOLTAGE_MASK
)) |
482 (mmc
->ocr
& OCR_ACCESS_MODE
);
484 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
487 mmc
->ocr
= cmd
.response
[0];
491 static int mmc_send_op_cond(struct mmc
*mmc
)
495 /* Some cards seem to need this */
498 /* Asking to the card its capabilities */
499 for (i
= 0; i
< 2; i
++) {
500 err
= mmc_send_op_cond_iter(mmc
, i
!= 0);
504 /* exit if not busy (flag seems to be inverted) */
505 if (mmc
->ocr
& OCR_BUSY
)
508 mmc
->op_cond_pending
= 1;
512 static int mmc_complete_op_cond(struct mmc
*mmc
)
519 mmc
->op_cond_pending
= 0;
520 if (!(mmc
->ocr
& OCR_BUSY
)) {
521 /* Some cards seem to need this */
524 start
= get_timer(0);
526 err
= mmc_send_op_cond_iter(mmc
, 1);
529 if (mmc
->ocr
& OCR_BUSY
)
531 if (get_timer(start
) > timeout
)
537 if (mmc_host_is_spi(mmc
)) { /* read OCR for spi */
538 cmd
.cmdidx
= MMC_CMD_SPI_READ_OCR
;
539 cmd
.resp_type
= MMC_RSP_R3
;
542 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
547 mmc
->ocr
= cmd
.response
[0];
550 mmc
->version
= MMC_VERSION_UNKNOWN
;
552 mmc
->high_capacity
= ((mmc
->ocr
& OCR_HCS
) == OCR_HCS
);
559 static int mmc_send_ext_csd(struct mmc
*mmc
, u8
*ext_csd
)
562 struct mmc_data data
;
565 /* Get the Card Status Register */
566 cmd
.cmdidx
= MMC_CMD_SEND_EXT_CSD
;
567 cmd
.resp_type
= MMC_RSP_R1
;
570 data
.dest
= (char *)ext_csd
;
572 data
.blocksize
= MMC_MAX_BLOCK_LEN
;
573 data
.flags
= MMC_DATA_READ
;
575 err
= mmc_send_cmd(mmc
, &cmd
, &data
);
580 int mmc_switch(struct mmc
*mmc
, u8 set
, u8 index
, u8 value
)
587 cmd
.cmdidx
= MMC_CMD_SWITCH
;
588 cmd
.resp_type
= MMC_RSP_R1b
;
589 cmd
.cmdarg
= (MMC_SWITCH_MODE_WRITE_BYTE
<< 24) |
593 while (retries
> 0) {
594 ret
= mmc_send_cmd(mmc
, &cmd
, NULL
);
596 /* Waiting for the ready status */
598 ret
= mmc_send_status(mmc
, timeout
);
609 static int mmc_set_card_speed(struct mmc
*mmc
, enum bus_mode mode
)
614 ALLOC_CACHE_ALIGN_BUFFER(u8
, test_csd
, MMC_MAX_BLOCK_LEN
);
620 speed_bits
= EXT_CSD_TIMING_HS
;
622 speed_bits
= EXT_CSD_TIMING_LEGACY
;
627 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
, EXT_CSD_HS_TIMING
,
632 if ((mode
== MMC_HS
) || (mode
== MMC_HS_52
)) {
633 /* Now check to see that it worked */
634 err
= mmc_send_ext_csd(mmc
, test_csd
);
638 /* No high-speed support */
639 if (!test_csd
[EXT_CSD_HS_TIMING
])
646 static int mmc_get_capabilities(struct mmc
*mmc
)
648 u8
*ext_csd
= mmc
->ext_csd
;
651 mmc
->card_caps
= MMC_MODE_1BIT
;
653 if (mmc_host_is_spi(mmc
))
656 /* Only version 4 supports high-speed */
657 if (mmc
->version
< MMC_VERSION_4
)
661 printf("No ext_csd found!\n"); /* this should enver happen */
665 mmc
->card_caps
|= MMC_MODE_4BIT
| MMC_MODE_8BIT
;
667 cardtype
= ext_csd
[EXT_CSD_CARD_TYPE
] & 0xf;
669 /* High Speed is set, there are two types: 52MHz and 26MHz */
670 if (cardtype
& EXT_CSD_CARD_TYPE_52
) {
671 if (cardtype
& EXT_CSD_CARD_TYPE_DDR_52
)
672 mmc
->card_caps
|= MMC_MODE_DDR_52MHz
;
673 mmc
->card_caps
|= MMC_MODE_HS_52MHz
;
675 if (cardtype
& EXT_CSD_CARD_TYPE_26
)
676 mmc
->card_caps
|= MMC_MODE_HS
;
681 static int mmc_set_capacity(struct mmc
*mmc
, int part_num
)
685 mmc
->capacity
= mmc
->capacity_user
;
689 mmc
->capacity
= mmc
->capacity_boot
;
692 mmc
->capacity
= mmc
->capacity_rpmb
;
698 mmc
->capacity
= mmc
->capacity_gp
[part_num
- 4];
704 mmc_get_blk_desc(mmc
)->lba
= lldiv(mmc
->capacity
, mmc
->read_bl_len
);
709 int mmc_switch_part(struct mmc
*mmc
, unsigned int part_num
)
713 ret
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
, EXT_CSD_PART_CONF
,
714 (mmc
->part_config
& ~PART_ACCESS_MASK
)
715 | (part_num
& PART_ACCESS_MASK
));
718 * Set the capacity if the switch succeeded or was intended
719 * to return to representing the raw device.
721 if ((ret
== 0) || ((ret
== -ENODEV
) && (part_num
== 0))) {
722 ret
= mmc_set_capacity(mmc
, part_num
);
723 mmc_get_blk_desc(mmc
)->hwpart
= part_num
;
729 int mmc_hwpart_config(struct mmc
*mmc
,
730 const struct mmc_hwpart_conf
*conf
,
731 enum mmc_hwpart_conf_mode mode
)
737 u32 max_enh_size_mult
;
738 u32 tot_enh_size_mult
= 0;
741 ALLOC_CACHE_ALIGN_BUFFER(u8
, ext_csd
, MMC_MAX_BLOCK_LEN
);
743 if (mode
< MMC_HWPART_CONF_CHECK
|| mode
> MMC_HWPART_CONF_COMPLETE
)
746 if (IS_SD(mmc
) || (mmc
->version
< MMC_VERSION_4_41
)) {
747 printf("eMMC >= 4.4 required for enhanced user data area\n");
751 if (!(mmc
->part_support
& PART_SUPPORT
)) {
752 printf("Card does not support partitioning\n");
756 if (!mmc
->hc_wp_grp_size
) {
757 printf("Card does not define HC WP group size\n");
761 /* check partition alignment and total enhanced size */
762 if (conf
->user
.enh_size
) {
763 if (conf
->user
.enh_size
% mmc
->hc_wp_grp_size
||
764 conf
->user
.enh_start
% mmc
->hc_wp_grp_size
) {
765 printf("User data enhanced area not HC WP group "
769 part_attrs
|= EXT_CSD_ENH_USR
;
770 enh_size_mult
= conf
->user
.enh_size
/ mmc
->hc_wp_grp_size
;
771 if (mmc
->high_capacity
) {
772 enh_start_addr
= conf
->user
.enh_start
;
774 enh_start_addr
= (conf
->user
.enh_start
<< 9);
780 tot_enh_size_mult
+= enh_size_mult
;
782 for (pidx
= 0; pidx
< 4; pidx
++) {
783 if (conf
->gp_part
[pidx
].size
% mmc
->hc_wp_grp_size
) {
784 printf("GP%i partition not HC WP group size "
785 "aligned\n", pidx
+1);
788 gp_size_mult
[pidx
] = conf
->gp_part
[pidx
].size
/ mmc
->hc_wp_grp_size
;
789 if (conf
->gp_part
[pidx
].size
&& conf
->gp_part
[pidx
].enhanced
) {
790 part_attrs
|= EXT_CSD_ENH_GP(pidx
);
791 tot_enh_size_mult
+= gp_size_mult
[pidx
];
795 if (part_attrs
&& ! (mmc
->part_support
& ENHNCD_SUPPORT
)) {
796 printf("Card does not support enhanced attribute\n");
800 err
= mmc_send_ext_csd(mmc
, ext_csd
);
805 (ext_csd
[EXT_CSD_MAX_ENH_SIZE_MULT
+2] << 16) +
806 (ext_csd
[EXT_CSD_MAX_ENH_SIZE_MULT
+1] << 8) +
807 ext_csd
[EXT_CSD_MAX_ENH_SIZE_MULT
];
808 if (tot_enh_size_mult
> max_enh_size_mult
) {
809 printf("Total enhanced size exceeds maximum (%u > %u)\n",
810 tot_enh_size_mult
, max_enh_size_mult
);
814 /* The default value of EXT_CSD_WR_REL_SET is device
815 * dependent, the values can only be changed if the
816 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
817 * changed only once and before partitioning is completed. */
818 wr_rel_set
= ext_csd
[EXT_CSD_WR_REL_SET
];
819 if (conf
->user
.wr_rel_change
) {
820 if (conf
->user
.wr_rel_set
)
821 wr_rel_set
|= EXT_CSD_WR_DATA_REL_USR
;
823 wr_rel_set
&= ~EXT_CSD_WR_DATA_REL_USR
;
825 for (pidx
= 0; pidx
< 4; pidx
++) {
826 if (conf
->gp_part
[pidx
].wr_rel_change
) {
827 if (conf
->gp_part
[pidx
].wr_rel_set
)
828 wr_rel_set
|= EXT_CSD_WR_DATA_REL_GP(pidx
);
830 wr_rel_set
&= ~EXT_CSD_WR_DATA_REL_GP(pidx
);
834 if (wr_rel_set
!= ext_csd
[EXT_CSD_WR_REL_SET
] &&
835 !(ext_csd
[EXT_CSD_WR_REL_PARAM
] & EXT_CSD_HS_CTRL_REL
)) {
836 puts("Card does not support host controlled partition write "
837 "reliability settings\n");
841 if (ext_csd
[EXT_CSD_PARTITION_SETTING
] &
842 EXT_CSD_PARTITION_SETTING_COMPLETED
) {
843 printf("Card already partitioned\n");
847 if (mode
== MMC_HWPART_CONF_CHECK
)
850 /* Partitioning requires high-capacity size definitions */
851 if (!(ext_csd
[EXT_CSD_ERASE_GROUP_DEF
] & 0x01)) {
852 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
853 EXT_CSD_ERASE_GROUP_DEF
, 1);
858 ext_csd
[EXT_CSD_ERASE_GROUP_DEF
] = 1;
860 /* update erase group size to be high-capacity */
861 mmc
->erase_grp_size
=
862 ext_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
] * 1024;
866 /* all OK, write the configuration */
867 for (i
= 0; i
< 4; i
++) {
868 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
869 EXT_CSD_ENH_START_ADDR
+i
,
870 (enh_start_addr
>> (i
*8)) & 0xFF);
874 for (i
= 0; i
< 3; i
++) {
875 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
876 EXT_CSD_ENH_SIZE_MULT
+i
,
877 (enh_size_mult
>> (i
*8)) & 0xFF);
881 for (pidx
= 0; pidx
< 4; pidx
++) {
882 for (i
= 0; i
< 3; i
++) {
883 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
884 EXT_CSD_GP_SIZE_MULT
+pidx
*3+i
,
885 (gp_size_mult
[pidx
] >> (i
*8)) & 0xFF);
890 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
891 EXT_CSD_PARTITIONS_ATTRIBUTE
, part_attrs
);
895 if (mode
== MMC_HWPART_CONF_SET
)
898 /* The WR_REL_SET is a write-once register but shall be
899 * written before setting PART_SETTING_COMPLETED. As it is
900 * write-once we can only write it when completing the
902 if (wr_rel_set
!= ext_csd
[EXT_CSD_WR_REL_SET
]) {
903 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
904 EXT_CSD_WR_REL_SET
, wr_rel_set
);
909 /* Setting PART_SETTING_COMPLETED confirms the partition
910 * configuration but it only becomes effective after power
911 * cycle, so we do not adjust the partition related settings
912 * in the mmc struct. */
914 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
915 EXT_CSD_PARTITION_SETTING
,
916 EXT_CSD_PARTITION_SETTING_COMPLETED
);
923 #if !CONFIG_IS_ENABLED(DM_MMC)
924 int mmc_getcd(struct mmc
*mmc
)
928 cd
= board_mmc_getcd(mmc
);
931 if (mmc
->cfg
->ops
->getcd
)
932 cd
= mmc
->cfg
->ops
->getcd(mmc
);
941 static int sd_switch(struct mmc
*mmc
, int mode
, int group
, u8 value
, u8
*resp
)
944 struct mmc_data data
;
946 /* Switch the frequency */
947 cmd
.cmdidx
= SD_CMD_SWITCH_FUNC
;
948 cmd
.resp_type
= MMC_RSP_R1
;
949 cmd
.cmdarg
= (mode
<< 31) | 0xffffff;
950 cmd
.cmdarg
&= ~(0xf << (group
* 4));
951 cmd
.cmdarg
|= value
<< (group
* 4);
953 data
.dest
= (char *)resp
;
956 data
.flags
= MMC_DATA_READ
;
958 return mmc_send_cmd(mmc
, &cmd
, &data
);
962 static int sd_get_capabilities(struct mmc
*mmc
)
966 ALLOC_CACHE_ALIGN_BUFFER(__be32
, scr
, 2);
967 ALLOC_CACHE_ALIGN_BUFFER(__be32
, switch_status
, 16);
968 struct mmc_data data
;
971 mmc
->card_caps
= MMC_MODE_1BIT
;
973 if (mmc_host_is_spi(mmc
))
976 /* Read the SCR to find out if this card supports higher speeds */
977 cmd
.cmdidx
= MMC_CMD_APP_CMD
;
978 cmd
.resp_type
= MMC_RSP_R1
;
979 cmd
.cmdarg
= mmc
->rca
<< 16;
981 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
986 cmd
.cmdidx
= SD_CMD_APP_SEND_SCR
;
987 cmd
.resp_type
= MMC_RSP_R1
;
993 data
.dest
= (char *)scr
;
996 data
.flags
= MMC_DATA_READ
;
998 err
= mmc_send_cmd(mmc
, &cmd
, &data
);
1007 mmc
->scr
[0] = __be32_to_cpu(scr
[0]);
1008 mmc
->scr
[1] = __be32_to_cpu(scr
[1]);
1010 switch ((mmc
->scr
[0] >> 24) & 0xf) {
1012 mmc
->version
= SD_VERSION_1_0
;
1015 mmc
->version
= SD_VERSION_1_10
;
1018 mmc
->version
= SD_VERSION_2
;
1019 if ((mmc
->scr
[0] >> 15) & 0x1)
1020 mmc
->version
= SD_VERSION_3
;
1023 mmc
->version
= SD_VERSION_1_0
;
1027 if (mmc
->scr
[0] & SD_DATA_4BIT
)
1028 mmc
->card_caps
|= MMC_MODE_4BIT
;
1030 /* Version 1.0 doesn't support switching */
1031 if (mmc
->version
== SD_VERSION_1_0
)
1036 err
= sd_switch(mmc
, SD_SWITCH_CHECK
, 0, 1,
1037 (u8
*)switch_status
);
1042 /* The high-speed function is busy. Try again */
1043 if (!(__be32_to_cpu(switch_status
[7]) & SD_HIGHSPEED_BUSY
))
1047 /* If high-speed isn't supported, we return */
1048 if (__be32_to_cpu(switch_status
[3]) & SD_HIGHSPEED_SUPPORTED
)
1049 mmc
->card_caps
|= MMC_CAP(SD_HS
);
1054 static int sd_set_card_speed(struct mmc
*mmc
, enum bus_mode mode
)
1058 ALLOC_CACHE_ALIGN_BUFFER(uint
, switch_status
, 16);
1060 err
= sd_switch(mmc
, SD_SWITCH_SWITCH
, 0, 1, (u8
*)switch_status
);
1064 if ((__be32_to_cpu(switch_status
[4]) & 0x0f000000) != 0x01000000)
1070 int sd_select_bus_width(struct mmc
*mmc
, int w
)
1075 if ((w
!= 4) && (w
!= 1))
1078 cmd
.cmdidx
= MMC_CMD_APP_CMD
;
1079 cmd
.resp_type
= MMC_RSP_R1
;
1080 cmd
.cmdarg
= mmc
->rca
<< 16;
1082 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1086 cmd
.cmdidx
= SD_CMD_APP_SET_BUS_WIDTH
;
1087 cmd
.resp_type
= MMC_RSP_R1
;
1092 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1099 static int sd_read_ssr(struct mmc
*mmc
)
1103 ALLOC_CACHE_ALIGN_BUFFER(uint
, ssr
, 16);
1104 struct mmc_data data
;
1106 unsigned int au
, eo
, et
, es
;
1108 cmd
.cmdidx
= MMC_CMD_APP_CMD
;
1109 cmd
.resp_type
= MMC_RSP_R1
;
1110 cmd
.cmdarg
= mmc
->rca
<< 16;
1112 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1116 cmd
.cmdidx
= SD_CMD_APP_SD_STATUS
;
1117 cmd
.resp_type
= MMC_RSP_R1
;
1121 data
.dest
= (char *)ssr
;
1122 data
.blocksize
= 64;
1124 data
.flags
= MMC_DATA_READ
;
1126 err
= mmc_send_cmd(mmc
, &cmd
, &data
);
1134 for (i
= 0; i
< 16; i
++)
1135 ssr
[i
] = be32_to_cpu(ssr
[i
]);
1137 au
= (ssr
[2] >> 12) & 0xF;
1138 if ((au
<= 9) || (mmc
->version
== SD_VERSION_3
)) {
1139 mmc
->ssr
.au
= sd_au_size
[au
];
1140 es
= (ssr
[3] >> 24) & 0xFF;
1141 es
|= (ssr
[2] & 0xFF) << 8;
1142 et
= (ssr
[3] >> 18) & 0x3F;
1144 eo
= (ssr
[3] >> 16) & 0x3;
1145 mmc
->ssr
.erase_timeout
= (et
* 1000) / es
;
1146 mmc
->ssr
.erase_offset
= eo
* 1000;
1149 debug("Invalid Allocation Unit Size.\n");
1155 /* frequency bases */
1156 /* divided by 10 to be nice to platforms without floating point */
1157 static const int fbase
[] = {
1164 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1165 * to platforms without floating point.
1167 static const u8 multipliers
[] = {
1186 static inline int bus_width(uint cap
)
1188 if (cap
== MMC_MODE_8BIT
)
1190 if (cap
== MMC_MODE_4BIT
)
1192 if (cap
== MMC_MODE_1BIT
)
1194 printf("invalid bus witdh capability 0x%x\n", cap
);
1198 #if !CONFIG_IS_ENABLED(DM_MMC)
1199 static void mmc_set_ios(struct mmc
*mmc
)
1201 if (mmc
->cfg
->ops
->set_ios
)
1202 mmc
->cfg
->ops
->set_ios(mmc
);
1206 void mmc_set_clock(struct mmc
*mmc
, uint clock
)
1208 if (clock
> mmc
->cfg
->f_max
)
1209 clock
= mmc
->cfg
->f_max
;
1211 if (clock
< mmc
->cfg
->f_min
)
1212 clock
= mmc
->cfg
->f_min
;
1219 static void mmc_set_bus_width(struct mmc
*mmc
, uint width
)
1221 mmc
->bus_width
= width
;
1226 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1228 * helper function to display the capabilities in a human
1229 * friendly manner. The capabilities include bus width and
1232 void mmc_dump_capabilities(const char *text
, uint caps
)
1236 printf("%s: widths [", text
);
1237 if (caps
& MMC_MODE_8BIT
)
1239 if (caps
& MMC_MODE_4BIT
)
1241 if (caps
& MMC_MODE_1BIT
)
1243 printf("\b\b] modes [");
1244 for (mode
= MMC_LEGACY
; mode
< MMC_MODES_END
; mode
++)
1245 if (MMC_CAP(mode
) & caps
)
1246 printf("%s, ", mmc_mode_name(mode
));
1251 struct mode_width_tuning
{
1256 static const struct mode_width_tuning sd_modes_by_pref
[] = {
1259 .widths
= MMC_MODE_4BIT
| MMC_MODE_1BIT
,
1263 .widths
= MMC_MODE_4BIT
| MMC_MODE_1BIT
,
1267 #define for_each_sd_mode_by_pref(caps, mwt) \
1268 for (mwt = sd_modes_by_pref;\
1269 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1271 if (caps & MMC_CAP(mwt->mode))
1273 static int sd_select_mode_and_width(struct mmc
*mmc
)
1276 uint widths
[] = {MMC_MODE_4BIT
, MMC_MODE_1BIT
};
1277 const struct mode_width_tuning
*mwt
;
1279 err
= sd_get_capabilities(mmc
);
1282 /* Restrict card's capabilities by what the host can do */
1283 mmc
->card_caps
&= (mmc
->cfg
->host_caps
| MMC_MODE_1BIT
);
1285 for_each_sd_mode_by_pref(mmc
->card_caps
, mwt
) {
1288 for (w
= widths
; w
< widths
+ ARRAY_SIZE(widths
); w
++) {
1289 if (*w
& mmc
->card_caps
& mwt
->widths
) {
1290 debug("trying mode %s width %d (at %d MHz)\n",
1291 mmc_mode_name(mwt
->mode
),
1293 mmc_mode2freq(mmc
, mwt
->mode
) / 1000000);
1295 /* configure the bus width (card + host) */
1296 err
= sd_select_bus_width(mmc
, bus_width(*w
));
1299 mmc_set_bus_width(mmc
, bus_width(*w
));
1301 /* configure the bus mode (card) */
1302 err
= sd_set_card_speed(mmc
, mwt
->mode
);
1306 /* configure the bus mode (host) */
1307 mmc_select_mode(mmc
, mwt
->mode
);
1308 mmc_set_clock(mmc
, mmc
->tran_speed
);
1310 err
= sd_read_ssr(mmc
);
1314 printf("bad ssr\n");
1317 /* revert to a safer bus speed */
1318 mmc_select_mode(mmc
, SD_LEGACY
);
1319 mmc_set_clock(mmc
, mmc
->tran_speed
);
1324 printf("unable to select a mode\n");
1329 * read the compare the part of ext csd that is constant.
1330 * This can be used to check that the transfer is working
1333 static int mmc_read_and_compare_ext_csd(struct mmc
*mmc
)
1336 const u8
*ext_csd
= mmc
->ext_csd
;
1337 ALLOC_CACHE_ALIGN_BUFFER(u8
, test_csd
, MMC_MAX_BLOCK_LEN
);
1339 err
= mmc_send_ext_csd(mmc
, test_csd
);
1343 /* Only compare read only fields */
1344 if (ext_csd
[EXT_CSD_PARTITIONING_SUPPORT
]
1345 == test_csd
[EXT_CSD_PARTITIONING_SUPPORT
] &&
1346 ext_csd
[EXT_CSD_HC_WP_GRP_SIZE
]
1347 == test_csd
[EXT_CSD_HC_WP_GRP_SIZE
] &&
1348 ext_csd
[EXT_CSD_REV
]
1349 == test_csd
[EXT_CSD_REV
] &&
1350 ext_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
]
1351 == test_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
] &&
1352 memcmp(&ext_csd
[EXT_CSD_SEC_CNT
],
1353 &test_csd
[EXT_CSD_SEC_CNT
], 4) == 0)
1359 static const struct mode_width_tuning mmc_modes_by_pref
[] = {
1362 .widths
= MMC_MODE_8BIT
| MMC_MODE_4BIT
,
1366 .widths
= MMC_MODE_8BIT
| MMC_MODE_4BIT
,
1370 .widths
= MMC_MODE_8BIT
| MMC_MODE_4BIT
| MMC_MODE_1BIT
,
1374 .widths
= MMC_MODE_8BIT
| MMC_MODE_4BIT
| MMC_MODE_1BIT
,
1378 .widths
= MMC_MODE_8BIT
| MMC_MODE_4BIT
| MMC_MODE_1BIT
,
1382 #define for_each_mmc_mode_by_pref(caps, mwt) \
1383 for (mwt = mmc_modes_by_pref;\
1384 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1386 if (caps & MMC_CAP(mwt->mode))
1388 static const struct ext_csd_bus_width
{
1392 } ext_csd_bus_width
[] = {
1393 {MMC_MODE_8BIT
, true, EXT_CSD_DDR_BUS_WIDTH_8
},
1394 {MMC_MODE_4BIT
, true, EXT_CSD_DDR_BUS_WIDTH_4
},
1395 {MMC_MODE_8BIT
, false, EXT_CSD_BUS_WIDTH_8
},
1396 {MMC_MODE_4BIT
, false, EXT_CSD_BUS_WIDTH_4
},
1397 {MMC_MODE_1BIT
, false, EXT_CSD_BUS_WIDTH_1
},
1400 #define for_each_supported_width(caps, ddr, ecbv) \
1401 for (ecbv = ext_csd_bus_width;\
1402 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1404 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1406 static int mmc_select_mode_and_width(struct mmc
*mmc
)
1409 const struct mode_width_tuning
*mwt
;
1410 const struct ext_csd_bus_width
*ecbw
;
1412 err
= mmc_get_capabilities(mmc
);
1416 /* Restrict card's capabilities by what the host can do */
1417 mmc
->card_caps
&= (mmc
->cfg
->host_caps
| MMC_MODE_1BIT
);
1419 /* Only version 4 of MMC supports wider bus widths */
1420 if (mmc
->version
< MMC_VERSION_4
)
1423 if (!mmc
->ext_csd
) {
1424 debug("No ext_csd found!\n"); /* this should enver happen */
1428 for_each_mmc_mode_by_pref(mmc
->card_caps
, mwt
) {
1429 for_each_supported_width(mmc
->card_caps
& mwt
->widths
,
1430 mmc_is_mode_ddr(mwt
->mode
), ecbw
) {
1431 debug("trying mode %s width %d (at %d MHz)\n",
1432 mmc_mode_name(mwt
->mode
),
1433 bus_width(ecbw
->cap
),
1434 mmc_mode2freq(mmc
, mwt
->mode
) / 1000000);
1435 /* configure the bus width (card + host) */
1436 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
1438 ecbw
->ext_csd_bits
& ~EXT_CSD_DDR_FLAG
);
1441 mmc_set_bus_width(mmc
, bus_width(ecbw
->cap
));
1443 /* configure the bus speed (card) */
1444 err
= mmc_set_card_speed(mmc
, mwt
->mode
);
1449 * configure the bus width AND the ddr mode (card)
1450 * The host side will be taken care of in the next step
1452 if (ecbw
->ext_csd_bits
& EXT_CSD_DDR_FLAG
) {
1453 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
1455 ecbw
->ext_csd_bits
);
1460 /* configure the bus mode (host) */
1461 mmc_select_mode(mmc
, mwt
->mode
);
1462 mmc_set_clock(mmc
, mmc
->tran_speed
);
1464 /* do a transfer to check the configuration */
1465 err
= mmc_read_and_compare_ext_csd(mmc
);
1469 /* if an error occured, revert to a safer bus mode */
1470 mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
1471 EXT_CSD_BUS_WIDTH
, EXT_CSD_BUS_WIDTH_1
);
1472 mmc_select_mode(mmc
, MMC_LEGACY
);
1473 mmc_set_bus_width(mmc
, 1);
1477 printf("unable to select a mode\n");
1482 static int mmc_startup_v4(struct mmc
*mmc
)
1486 bool has_parts
= false;
1487 bool part_completed
;
1490 if (IS_SD(mmc
) || (mmc
->version
< MMC_VERSION_4
))
1493 ext_csd
= malloc_cache_aligned(MMC_MAX_BLOCK_LEN
);
1497 mmc
->ext_csd
= ext_csd
;
1499 /* check ext_csd version and capacity */
1500 err
= mmc_send_ext_csd(mmc
, ext_csd
);
1503 if (ext_csd
[EXT_CSD_REV
] >= 2) {
1505 * According to the JEDEC Standard, the value of
1506 * ext_csd's capacity is valid if the value is more
1509 capacity
= ext_csd
[EXT_CSD_SEC_CNT
] << 0
1510 | ext_csd
[EXT_CSD_SEC_CNT
+ 1] << 8
1511 | ext_csd
[EXT_CSD_SEC_CNT
+ 2] << 16
1512 | ext_csd
[EXT_CSD_SEC_CNT
+ 3] << 24;
1513 capacity
*= MMC_MAX_BLOCK_LEN
;
1514 if ((capacity
>> 20) > 2 * 1024)
1515 mmc
->capacity_user
= capacity
;
1518 switch (ext_csd
[EXT_CSD_REV
]) {
1520 mmc
->version
= MMC_VERSION_4_1
;
1523 mmc
->version
= MMC_VERSION_4_2
;
1526 mmc
->version
= MMC_VERSION_4_3
;
1529 mmc
->version
= MMC_VERSION_4_41
;
1532 mmc
->version
= MMC_VERSION_4_5
;
1535 mmc
->version
= MMC_VERSION_5_0
;
1538 mmc
->version
= MMC_VERSION_5_1
;
1542 /* The partition data may be non-zero but it is only
1543 * effective if PARTITION_SETTING_COMPLETED is set in
1544 * EXT_CSD, so ignore any data if this bit is not set,
1545 * except for enabling the high-capacity group size
1546 * definition (see below).
1548 part_completed
= !!(ext_csd
[EXT_CSD_PARTITION_SETTING
] &
1549 EXT_CSD_PARTITION_SETTING_COMPLETED
);
1551 /* store the partition info of emmc */
1552 mmc
->part_support
= ext_csd
[EXT_CSD_PARTITIONING_SUPPORT
];
1553 if ((ext_csd
[EXT_CSD_PARTITIONING_SUPPORT
] & PART_SUPPORT
) ||
1554 ext_csd
[EXT_CSD_BOOT_MULT
])
1555 mmc
->part_config
= ext_csd
[EXT_CSD_PART_CONF
];
1556 if (part_completed
&&
1557 (ext_csd
[EXT_CSD_PARTITIONING_SUPPORT
] & ENHNCD_SUPPORT
))
1558 mmc
->part_attr
= ext_csd
[EXT_CSD_PARTITIONS_ATTRIBUTE
];
1560 mmc
->capacity_boot
= ext_csd
[EXT_CSD_BOOT_MULT
] << 17;
1562 mmc
->capacity_rpmb
= ext_csd
[EXT_CSD_RPMB_MULT
] << 17;
1564 for (i
= 0; i
< 4; i
++) {
1565 int idx
= EXT_CSD_GP_SIZE_MULT
+ i
* 3;
1566 uint mult
= (ext_csd
[idx
+ 2] << 16) +
1567 (ext_csd
[idx
+ 1] << 8) + ext_csd
[idx
];
1570 if (!part_completed
)
1572 mmc
->capacity_gp
[i
] = mult
;
1573 mmc
->capacity_gp
[i
] *=
1574 ext_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
];
1575 mmc
->capacity_gp
[i
] *= ext_csd
[EXT_CSD_HC_WP_GRP_SIZE
];
1576 mmc
->capacity_gp
[i
] <<= 19;
1579 if (part_completed
) {
1580 mmc
->enh_user_size
=
1581 (ext_csd
[EXT_CSD_ENH_SIZE_MULT
+ 2] << 16) +
1582 (ext_csd
[EXT_CSD_ENH_SIZE_MULT
+ 1] << 8) +
1583 ext_csd
[EXT_CSD_ENH_SIZE_MULT
];
1584 mmc
->enh_user_size
*= ext_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
];
1585 mmc
->enh_user_size
*= ext_csd
[EXT_CSD_HC_WP_GRP_SIZE
];
1586 mmc
->enh_user_size
<<= 19;
1587 mmc
->enh_user_start
=
1588 (ext_csd
[EXT_CSD_ENH_START_ADDR
+ 3] << 24) +
1589 (ext_csd
[EXT_CSD_ENH_START_ADDR
+ 2] << 16) +
1590 (ext_csd
[EXT_CSD_ENH_START_ADDR
+ 1] << 8) +
1591 ext_csd
[EXT_CSD_ENH_START_ADDR
];
1592 if (mmc
->high_capacity
)
1593 mmc
->enh_user_start
<<= 9;
1597 * Host needs to enable ERASE_GRP_DEF bit if device is
1598 * partitioned. This bit will be lost every time after a reset
1599 * or power off. This will affect erase size.
1603 if ((ext_csd
[EXT_CSD_PARTITIONING_SUPPORT
] & PART_SUPPORT
) &&
1604 (ext_csd
[EXT_CSD_PARTITIONS_ATTRIBUTE
] & PART_ENH_ATTRIB
))
1607 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
1608 EXT_CSD_ERASE_GROUP_DEF
, 1);
1613 ext_csd
[EXT_CSD_ERASE_GROUP_DEF
] = 1;
1616 if (ext_csd
[EXT_CSD_ERASE_GROUP_DEF
] & 0x01) {
1617 /* Read out group size from ext_csd */
1618 mmc
->erase_grp_size
=
1619 ext_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
] * 1024;
1621 * if high capacity and partition setting completed
1622 * SEC_COUNT is valid even if it is smaller than 2 GiB
1623 * JEDEC Standard JESD84-B45, 6.2.4
1625 if (mmc
->high_capacity
&& part_completed
) {
1626 capacity
= (ext_csd
[EXT_CSD_SEC_CNT
]) |
1627 (ext_csd
[EXT_CSD_SEC_CNT
+ 1] << 8) |
1628 (ext_csd
[EXT_CSD_SEC_CNT
+ 2] << 16) |
1629 (ext_csd
[EXT_CSD_SEC_CNT
+ 3] << 24);
1630 capacity
*= MMC_MAX_BLOCK_LEN
;
1631 mmc
->capacity_user
= capacity
;
1634 /* Calculate the group size from the csd value. */
1635 int erase_gsz
, erase_gmul
;
1637 erase_gsz
= (mmc
->csd
[2] & 0x00007c00) >> 10;
1638 erase_gmul
= (mmc
->csd
[2] & 0x000003e0) >> 5;
1639 mmc
->erase_grp_size
= (erase_gsz
+ 1)
1643 mmc
->hc_wp_grp_size
= 1024
1644 * ext_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
]
1645 * ext_csd
[EXT_CSD_HC_WP_GRP_SIZE
];
1647 mmc
->wr_rel_set
= ext_csd
[EXT_CSD_WR_REL_SET
];
1652 static int mmc_startup(struct mmc
*mmc
)
1658 struct blk_desc
*bdesc
;
1660 #ifdef CONFIG_MMC_SPI_CRC_ON
1661 if (mmc_host_is_spi(mmc
)) { /* enable CRC check for spi */
1662 cmd
.cmdidx
= MMC_CMD_SPI_CRC_ON_OFF
;
1663 cmd
.resp_type
= MMC_RSP_R1
;
1665 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1672 /* Put the Card in Identify Mode */
1673 cmd
.cmdidx
= mmc_host_is_spi(mmc
) ? MMC_CMD_SEND_CID
:
1674 MMC_CMD_ALL_SEND_CID
; /* cmd not supported in spi */
1675 cmd
.resp_type
= MMC_RSP_R2
;
1678 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1683 memcpy(mmc
->cid
, cmd
.response
, 16);
1686 * For MMC cards, set the Relative Address.
1687 * For SD cards, get the Relatvie Address.
1688 * This also puts the cards into Standby State
1690 if (!mmc_host_is_spi(mmc
)) { /* cmd not supported in spi */
1691 cmd
.cmdidx
= SD_CMD_SEND_RELATIVE_ADDR
;
1692 cmd
.cmdarg
= mmc
->rca
<< 16;
1693 cmd
.resp_type
= MMC_RSP_R6
;
1695 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1701 mmc
->rca
= (cmd
.response
[0] >> 16) & 0xffff;
1704 /* Get the Card-Specific Data */
1705 cmd
.cmdidx
= MMC_CMD_SEND_CSD
;
1706 cmd
.resp_type
= MMC_RSP_R2
;
1707 cmd
.cmdarg
= mmc
->rca
<< 16;
1709 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1714 mmc
->csd
[0] = cmd
.response
[0];
1715 mmc
->csd
[1] = cmd
.response
[1];
1716 mmc
->csd
[2] = cmd
.response
[2];
1717 mmc
->csd
[3] = cmd
.response
[3];
1719 if (mmc
->version
== MMC_VERSION_UNKNOWN
) {
1720 int version
= (cmd
.response
[0] >> 26) & 0xf;
1724 mmc
->version
= MMC_VERSION_1_2
;
1727 mmc
->version
= MMC_VERSION_1_4
;
1730 mmc
->version
= MMC_VERSION_2_2
;
1733 mmc
->version
= MMC_VERSION_3
;
1736 mmc
->version
= MMC_VERSION_4
;
1739 mmc
->version
= MMC_VERSION_1_2
;
1744 /* divide frequency by 10, since the mults are 10x bigger */
1745 freq
= fbase
[(cmd
.response
[0] & 0x7)];
1746 mult
= multipliers
[((cmd
.response
[0] >> 3) & 0xf)];
1748 mmc
->legacy_speed
= freq
* mult
;
1749 mmc_select_mode(mmc
, MMC_LEGACY
);
1751 mmc
->dsr_imp
= ((cmd
.response
[1] >> 12) & 0x1);
1752 mmc
->read_bl_len
= 1 << ((cmd
.response
[1] >> 16) & 0xf);
1755 mmc
->write_bl_len
= mmc
->read_bl_len
;
1757 mmc
->write_bl_len
= 1 << ((cmd
.response
[3] >> 22) & 0xf);
1759 if (mmc
->high_capacity
) {
1760 csize
= (mmc
->csd
[1] & 0x3f) << 16
1761 | (mmc
->csd
[2] & 0xffff0000) >> 16;
1764 csize
= (mmc
->csd
[1] & 0x3ff) << 2
1765 | (mmc
->csd
[2] & 0xc0000000) >> 30;
1766 cmult
= (mmc
->csd
[2] & 0x00038000) >> 15;
1769 mmc
->capacity_user
= (csize
+ 1) << (cmult
+ 2);
1770 mmc
->capacity_user
*= mmc
->read_bl_len
;
1771 mmc
->capacity_boot
= 0;
1772 mmc
->capacity_rpmb
= 0;
1773 for (i
= 0; i
< 4; i
++)
1774 mmc
->capacity_gp
[i
] = 0;
1776 if (mmc
->read_bl_len
> MMC_MAX_BLOCK_LEN
)
1777 mmc
->read_bl_len
= MMC_MAX_BLOCK_LEN
;
1779 if (mmc
->write_bl_len
> MMC_MAX_BLOCK_LEN
)
1780 mmc
->write_bl_len
= MMC_MAX_BLOCK_LEN
;
1782 if ((mmc
->dsr_imp
) && (0xffffffff != mmc
->dsr
)) {
1783 cmd
.cmdidx
= MMC_CMD_SET_DSR
;
1784 cmd
.cmdarg
= (mmc
->dsr
& 0xffff) << 16;
1785 cmd
.resp_type
= MMC_RSP_NONE
;
1786 if (mmc_send_cmd(mmc
, &cmd
, NULL
))
1787 printf("MMC: SET_DSR failed\n");
1790 /* Select the card, and put it into Transfer Mode */
1791 if (!mmc_host_is_spi(mmc
)) { /* cmd not supported in spi */
1792 cmd
.cmdidx
= MMC_CMD_SELECT_CARD
;
1793 cmd
.resp_type
= MMC_RSP_R1
;
1794 cmd
.cmdarg
= mmc
->rca
<< 16;
1795 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1802 * For SD, its erase group is always one sector
1804 mmc
->erase_grp_size
= 1;
1805 mmc
->part_config
= MMCPART_NOAVAILABLE
;
1807 err
= mmc_startup_v4(mmc
);
1811 err
= mmc_set_capacity(mmc
, mmc_get_blk_desc(mmc
)->hwpart
);
1816 err
= sd_select_mode_and_width(mmc
);
1818 err
= mmc_select_mode_and_width(mmc
);
1824 /* Fix the block length for DDR mode */
1825 if (mmc
->ddr_mode
) {
1826 mmc
->read_bl_len
= MMC_MAX_BLOCK_LEN
;
1827 mmc
->write_bl_len
= MMC_MAX_BLOCK_LEN
;
1830 /* fill in device description */
1831 bdesc
= mmc_get_blk_desc(mmc
);
1835 bdesc
->blksz
= mmc
->read_bl_len
;
1836 bdesc
->log2blksz
= LOG2(bdesc
->blksz
);
1837 bdesc
->lba
= lldiv(mmc
->capacity
, mmc
->read_bl_len
);
1838 #if !defined(CONFIG_SPL_BUILD) || \
1839 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1840 !defined(CONFIG_USE_TINY_PRINTF))
1841 sprintf(bdesc
->vendor
, "Man %06x Snr %04x%04x",
1842 mmc
->cid
[0] >> 24, (mmc
->cid
[2] & 0xffff),
1843 (mmc
->cid
[3] >> 16) & 0xffff);
1844 sprintf(bdesc
->product
, "%c%c%c%c%c%c", mmc
->cid
[0] & 0xff,
1845 (mmc
->cid
[1] >> 24), (mmc
->cid
[1] >> 16) & 0xff,
1846 (mmc
->cid
[1] >> 8) & 0xff, mmc
->cid
[1] & 0xff,
1847 (mmc
->cid
[2] >> 24) & 0xff);
1848 sprintf(bdesc
->revision
, "%d.%d", (mmc
->cid
[2] >> 20) & 0xf,
1849 (mmc
->cid
[2] >> 16) & 0xf);
1851 bdesc
->vendor
[0] = 0;
1852 bdesc
->product
[0] = 0;
1853 bdesc
->revision
[0] = 0;
1855 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1862 static int mmc_send_if_cond(struct mmc
*mmc
)
1867 cmd
.cmdidx
= SD_CMD_SEND_IF_COND
;
1868 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1869 cmd
.cmdarg
= ((mmc
->cfg
->voltages
& 0xff8000) != 0) << 8 | 0xaa;
1870 cmd
.resp_type
= MMC_RSP_R7
;
1872 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1877 if ((cmd
.response
[0] & 0xff) != 0xaa)
1880 mmc
->version
= SD_VERSION_2
;
1885 #if !CONFIG_IS_ENABLED(DM_MMC)
1886 /* board-specific MMC power initializations. */
1887 __weak
void board_mmc_power_init(void)
1892 static int mmc_power_init(struct mmc
*mmc
)
1894 #if CONFIG_IS_ENABLED(DM_MMC)
1895 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1898 ret
= device_get_supply_regulator(mmc
->dev
, "vmmc-supply",
1901 debug("%s: No vmmc supply\n", mmc
->dev
->name
);
1903 ret
= device_get_supply_regulator(mmc
->dev
, "vqmmc-supply",
1904 &mmc
->vqmmc_supply
);
1906 debug("%s: No vqmmc supply\n", mmc
->dev
->name
);
1908 if (mmc
->vmmc_supply
) {
1909 ret
= regulator_set_enable(mmc
->vmmc_supply
, true);
1911 puts("Error enabling VMMC supply\n");
1916 #else /* !CONFIG_DM_MMC */
1918 * Driver model should use a regulator, as above, rather than calling
1919 * out to board code.
1921 board_mmc_power_init();
1926 int mmc_start_init(struct mmc
*mmc
)
1931 /* we pretend there's no card when init is NULL */
1932 no_card
= mmc_getcd(mmc
) == 0;
1933 #if !CONFIG_IS_ENABLED(DM_MMC)
1934 no_card
= no_card
|| (mmc
->cfg
->ops
->init
== NULL
);
1938 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1939 printf("MMC: no card present\n");
1947 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1948 mmc_adapter_card_type_ident();
1950 err
= mmc_power_init(mmc
);
1954 #if CONFIG_IS_ENABLED(DM_MMC)
1955 /* The device has already been probed ready for use */
1957 /* made sure it's not NULL earlier */
1958 err
= mmc
->cfg
->ops
->init(mmc
);
1963 mmc_set_bus_width(mmc
, 1);
1964 mmc_set_clock(mmc
, 1);
1966 /* Reset the Card */
1967 err
= mmc_go_idle(mmc
);
1972 /* The internal partition reset to user partition(0) at every CMD0*/
1973 mmc_get_blk_desc(mmc
)->hwpart
= 0;
1975 /* Test for SD version 2 */
1976 err
= mmc_send_if_cond(mmc
);
1978 /* Now try to get the SD card's operating condition */
1979 err
= sd_send_op_cond(mmc
);
1981 /* If the command timed out, we check for an MMC card */
1982 if (err
== -ETIMEDOUT
) {
1983 err
= mmc_send_op_cond(mmc
);
1986 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1987 printf("Card did not respond to voltage select!\n");
1994 mmc
->init_in_progress
= 1;
1999 static int mmc_complete_init(struct mmc
*mmc
)
2003 mmc
->init_in_progress
= 0;
2004 if (mmc
->op_cond_pending
)
2005 err
= mmc_complete_op_cond(mmc
);
2008 err
= mmc_startup(mmc
);
2016 int mmc_init(struct mmc
*mmc
)
2019 __maybe_unused
unsigned start
;
2020 #if CONFIG_IS_ENABLED(DM_MMC)
2021 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(mmc
->dev
);
2028 start
= get_timer(0);
2030 if (!mmc
->init_in_progress
)
2031 err
= mmc_start_init(mmc
);
2034 err
= mmc_complete_init(mmc
);
2036 printf("%s: %d, time %lu\n", __func__
, err
, get_timer(start
));
2041 int mmc_set_dsr(struct mmc
*mmc
, u16 val
)
2047 /* CPU-specific MMC initializations */
2048 __weak
int cpu_mmc_init(bd_t
*bis
)
2053 /* board-specific MMC initializations. */
2054 __weak
int board_mmc_init(bd_t
*bis
)
2059 void mmc_set_preinit(struct mmc
*mmc
, int preinit
)
2061 mmc
->preinit
= preinit
;
2064 #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
2065 static int mmc_probe(bd_t
*bis
)
2069 #elif CONFIG_IS_ENABLED(DM_MMC)
2070 static int mmc_probe(bd_t
*bis
)
2074 struct udevice
*dev
;
2076 ret
= uclass_get(UCLASS_MMC
, &uc
);
2081 * Try to add them in sequence order. Really with driver model we
2082 * should allow holes, but the current MMC list does not allow that.
2083 * So if we request 0, 1, 3 we will get 0, 1, 2.
2085 for (i
= 0; ; i
++) {
2086 ret
= uclass_get_device_by_seq(UCLASS_MMC
, i
, &dev
);
2090 uclass_foreach_dev(dev
, uc
) {
2091 ret
= device_probe(dev
);
2093 printf("%s - probe failed: %d\n", dev
->name
, ret
);
2099 static int mmc_probe(bd_t
*bis
)
2101 if (board_mmc_init(bis
) < 0)
2108 int mmc_initialize(bd_t
*bis
)
2110 static int initialized
= 0;
2112 if (initialized
) /* Avoid initializing mmc multiple times */
2116 #if !CONFIG_IS_ENABLED(BLK)
2117 #if !CONFIG_IS_ENABLED(MMC_TINY)
2121 ret
= mmc_probe(bis
);
2125 #ifndef CONFIG_SPL_BUILD
2126 print_mmc_devices(',');
2133 #ifdef CONFIG_CMD_BKOPS_ENABLE
2134 int mmc_set_bkops_enable(struct mmc
*mmc
)
2137 ALLOC_CACHE_ALIGN_BUFFER(u8
, ext_csd
, MMC_MAX_BLOCK_LEN
);
2139 err
= mmc_send_ext_csd(mmc
, ext_csd
);
2141 puts("Could not get ext_csd register values\n");
2145 if (!(ext_csd
[EXT_CSD_BKOPS_SUPPORT
] & 0x1)) {
2146 puts("Background operations not supported on device\n");
2147 return -EMEDIUMTYPE
;
2150 if (ext_csd
[EXT_CSD_BKOPS_EN
] & 0x1) {
2151 puts("Background operations already enabled\n");
2155 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
, EXT_CSD_BKOPS_EN
, 1);
2157 puts("Failed to enable manual background operations\n");
2161 puts("Enabled manual background operations\n");