2 * Freescale i.MX28 SSP MMC driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
11 * Copyright 2007, Freescale Semiconductor, Inc
14 * Based vaguely on the pxa mmc code:
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
18 * See file CREDITS for list of people who contributed to this
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/errno.h>
41 #include <asm/arch/clock.h>
42 #include <asm/arch/imx-regs.h>
43 #include <asm/arch/sys_proto.h>
44 #include <asm/arch/dma.h>
48 struct mxs_ssp_regs
*regs
;
49 uint32_t clkseq_bypass
;
50 uint32_t *clkctrl_ssp
;
52 int (*mmc_is_wp
)(int);
53 struct mxs_dma_desc
*desc
;
56 #define MXSMMC_MAX_TIMEOUT 10000
57 #define MXSMMC_SMALL_TRANSFER 512
59 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv
*priv
, struct mmc_data
*data
)
61 struct mxs_ssp_regs
*ssp_regs
= priv
->regs
;
63 int timeout
= MXSMMC_MAX_TIMEOUT
;
65 uint32_t data_count
= data
->blocksize
* data
->blocks
;
67 if (data
->flags
& MMC_DATA_READ
) {
68 data_ptr
= (uint32_t *)data
->dest
;
69 while (data_count
&& --timeout
) {
70 reg
= readl(&ssp_regs
->hw_ssp_status
);
71 if (!(reg
& SSP_STATUS_FIFO_EMPTY
)) {
72 *data_ptr
++ = readl(&ssp_regs
->hw_ssp_data
);
74 timeout
= MXSMMC_MAX_TIMEOUT
;
79 data_ptr
= (uint32_t *)data
->src
;
81 while (data_count
&& --timeout
) {
82 reg
= readl(&ssp_regs
->hw_ssp_status
);
83 if (!(reg
& SSP_STATUS_FIFO_FULL
)) {
84 writel(*data_ptr
++, &ssp_regs
->hw_ssp_data
);
86 timeout
= MXSMMC_MAX_TIMEOUT
;
92 return timeout
? 0 : COMM_ERR
;
95 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv
*priv
, struct mmc_data
*data
)
97 uint32_t data_count
= data
->blocksize
* data
->blocks
;
98 uint32_t cache_data_count
;
100 struct mxs_dma_desc
*desc
= priv
->desc
;
102 memset(desc
, 0, sizeof(struct mxs_dma_desc
));
103 desc
->address
= (dma_addr_t
)desc
;
105 if (data_count
% ARCH_DMA_MINALIGN
)
106 cache_data_count
= roundup(data_count
, ARCH_DMA_MINALIGN
);
108 cache_data_count
= data_count
;
110 if (data
->flags
& MMC_DATA_READ
) {
111 priv
->desc
->cmd
.data
= MXS_DMA_DESC_COMMAND_DMA_WRITE
;
112 priv
->desc
->cmd
.address
= (dma_addr_t
)data
->dest
;
114 priv
->desc
->cmd
.data
= MXS_DMA_DESC_COMMAND_DMA_READ
;
115 priv
->desc
->cmd
.address
= (dma_addr_t
)data
->src
;
117 /* Flush data to DRAM so DMA can pick them up */
118 flush_dcache_range((uint32_t)priv
->desc
->cmd
.address
,
119 (uint32_t)(priv
->desc
->cmd
.address
+ cache_data_count
));
122 /* Invalidate the area, so no writeback into the RAM races with DMA */
123 invalidate_dcache_range((uint32_t)priv
->desc
->cmd
.address
,
124 (uint32_t)(priv
->desc
->cmd
.address
+ cache_data_count
));
126 priv
->desc
->cmd
.data
|= MXS_DMA_DESC_IRQ
| MXS_DMA_DESC_DEC_SEM
|
127 (data_count
<< MXS_DMA_DESC_BYTES_OFFSET
);
129 dmach
= MXS_DMA_CHANNEL_AHB_APBH_SSP0
+ priv
->id
;
130 mxs_dma_desc_append(dmach
, priv
->desc
);
131 if (mxs_dma_go(dmach
))
134 /* The data arrived into DRAM, invalidate cache over them */
135 if (data
->flags
& MMC_DATA_READ
) {
136 invalidate_dcache_range((uint32_t)priv
->desc
->cmd
.address
,
137 (uint32_t)(priv
->desc
->cmd
.address
+ cache_data_count
));
144 * Sends a command out on the bus. Takes the mmc pointer,
145 * a command pointer, and an optional data pointer.
148 mxsmmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
, struct mmc_data
*data
)
150 struct mxsmmc_priv
*priv
= (struct mxsmmc_priv
*)mmc
->priv
;
151 struct mxs_ssp_regs
*ssp_regs
= priv
->regs
;
157 debug("MMC%d: CMD%d\n", mmc
->block_dev
.dev
, cmd
->cmdidx
);
160 timeout
= MXSMMC_MAX_TIMEOUT
;
163 reg
= readl(&ssp_regs
->hw_ssp_status
);
165 (SSP_STATUS_BUSY
| SSP_STATUS_DATA_BUSY
|
166 SSP_STATUS_CMD_BUSY
))) {
172 printf("MMC%d: Bus busy timeout!\n", mmc
->block_dev
.dev
);
176 /* See if card is present */
177 if (readl(&ssp_regs
->hw_ssp_status
) & SSP_STATUS_CARD_DETECT
) {
178 printf("MMC%d: No card detected!\n", mmc
->block_dev
.dev
);
182 /* Start building CTRL0 contents */
183 ctrl0
= priv
->buswidth
;
186 if (!(cmd
->resp_type
& MMC_RSP_CRC
))
187 ctrl0
|= SSP_CTRL0_IGNORE_CRC
;
188 if (cmd
->resp_type
& MMC_RSP_PRESENT
) /* Need to get response */
189 ctrl0
|= SSP_CTRL0_GET_RESP
;
190 if (cmd
->resp_type
& MMC_RSP_136
) /* It's a 136 bits response */
191 ctrl0
|= SSP_CTRL0_LONG_RESP
;
193 if (data
&& (data
->blocksize
* data
->blocks
< MXSMMC_SMALL_TRANSFER
))
194 writel(SSP_CTRL1_DMA_ENABLE
, &ssp_regs
->hw_ssp_ctrl1_clr
);
196 writel(SSP_CTRL1_DMA_ENABLE
, &ssp_regs
->hw_ssp_ctrl1_set
);
199 reg
= readl(&ssp_regs
->hw_ssp_cmd0
);
200 reg
&= ~(SSP_CMD0_CMD_MASK
| SSP_CMD0_APPEND_8CYC
);
201 reg
|= cmd
->cmdidx
<< SSP_CMD0_CMD_OFFSET
;
202 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
203 reg
|= SSP_CMD0_APPEND_8CYC
;
204 writel(reg
, &ssp_regs
->hw_ssp_cmd0
);
206 /* Command argument */
207 writel(cmd
->cmdarg
, &ssp_regs
->hw_ssp_cmd1
);
212 if (data
->flags
& MMC_DATA_READ
) {
213 ctrl0
|= SSP_CTRL0_READ
;
214 } else if (priv
->mmc_is_wp
&&
215 priv
->mmc_is_wp(mmc
->block_dev
.dev
)) {
216 printf("MMC%d: Can not write a locked card!\n",
221 ctrl0
|= SSP_CTRL0_DATA_XFER
;
222 reg
= ((data
->blocks
- 1) <<
223 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET
) |
224 ((ffs(data
->blocksize
) - 1) <<
225 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET
);
226 writel(reg
, &ssp_regs
->hw_ssp_block_size
);
228 reg
= data
->blocksize
* data
->blocks
;
229 writel(reg
, &ssp_regs
->hw_ssp_xfer_size
);
232 /* Kick off the command */
233 ctrl0
|= SSP_CTRL0_WAIT_FOR_IRQ
| SSP_CTRL0_ENABLE
| SSP_CTRL0_RUN
;
234 writel(ctrl0
, &ssp_regs
->hw_ssp_ctrl0
);
236 /* Wait for the command to complete */
237 timeout
= MXSMMC_MAX_TIMEOUT
;
240 reg
= readl(&ssp_regs
->hw_ssp_status
);
241 if (!(reg
& SSP_STATUS_CMD_BUSY
))
246 printf("MMC%d: Command %d busy\n",
247 mmc
->block_dev
.dev
, cmd
->cmdidx
);
251 /* Check command timeout */
252 if (reg
& SSP_STATUS_RESP_TIMEOUT
) {
253 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
254 mmc
->block_dev
.dev
, cmd
->cmdidx
, reg
);
258 /* Check command errors */
259 if (reg
& (SSP_STATUS_RESP_CRC_ERR
| SSP_STATUS_RESP_ERR
)) {
260 printf("MMC%d: Command %d error (status 0x%08x)!\n",
261 mmc
->block_dev
.dev
, cmd
->cmdidx
, reg
);
265 /* Copy response to response buffer */
266 if (cmd
->resp_type
& MMC_RSP_136
) {
267 cmd
->response
[3] = readl(&ssp_regs
->hw_ssp_sdresp0
);
268 cmd
->response
[2] = readl(&ssp_regs
->hw_ssp_sdresp1
);
269 cmd
->response
[1] = readl(&ssp_regs
->hw_ssp_sdresp2
);
270 cmd
->response
[0] = readl(&ssp_regs
->hw_ssp_sdresp3
);
272 cmd
->response
[0] = readl(&ssp_regs
->hw_ssp_sdresp0
);
274 /* Return if no data to process */
278 if (data
->blocksize
* data
->blocks
< MXSMMC_SMALL_TRANSFER
) {
279 ret
= mxsmmc_send_cmd_pio(priv
, data
);
281 printf("MMC%d: Data timeout with command %d "
282 "(status 0x%08x)!\n",
283 mmc
->block_dev
.dev
, cmd
->cmdidx
, reg
);
287 ret
= mxsmmc_send_cmd_dma(priv
, data
);
289 printf("MMC%d: DMA transfer failed\n",
295 /* Check data errors */
296 reg
= readl(&ssp_regs
->hw_ssp_status
);
298 (SSP_STATUS_TIMEOUT
| SSP_STATUS_DATA_CRC_ERR
|
299 SSP_STATUS_FIFO_OVRFLW
| SSP_STATUS_FIFO_UNDRFLW
)) {
300 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
301 mmc
->block_dev
.dev
, cmd
->cmdidx
, reg
);
308 static void mxsmmc_set_ios(struct mmc
*mmc
)
310 struct mxsmmc_priv
*priv
= (struct mxsmmc_priv
*)mmc
->priv
;
311 struct mxs_ssp_regs
*ssp_regs
= priv
->regs
;
313 /* Set the clock speed */
315 mx28_set_ssp_busclock(priv
->id
, mmc
->clock
/ 1000);
317 switch (mmc
->bus_width
) {
319 priv
->buswidth
= SSP_CTRL0_BUS_WIDTH_ONE_BIT
;
322 priv
->buswidth
= SSP_CTRL0_BUS_WIDTH_FOUR_BIT
;
325 priv
->buswidth
= SSP_CTRL0_BUS_WIDTH_EIGHT_BIT
;
329 /* Set the bus width */
330 clrsetbits_le32(&ssp_regs
->hw_ssp_ctrl0
,
331 SSP_CTRL0_BUS_WIDTH_MASK
, priv
->buswidth
);
333 debug("MMC%d: Set %d bits bus width\n",
334 mmc
->block_dev
.dev
, mmc
->bus_width
);
337 static int mxsmmc_init(struct mmc
*mmc
)
339 struct mxsmmc_priv
*priv
= (struct mxsmmc_priv
*)mmc
->priv
;
340 struct mxs_ssp_regs
*ssp_regs
= priv
->regs
;
343 mxs_reset_block(&ssp_regs
->hw_ssp_ctrl0_reg
);
345 /* 8 bits word length in MMC mode */
346 clrsetbits_le32(&ssp_regs
->hw_ssp_ctrl1
,
347 SSP_CTRL1_SSP_MODE_MASK
| SSP_CTRL1_WORD_LENGTH_MASK
|
348 SSP_CTRL1_DMA_ENABLE
,
349 SSP_CTRL1_SSP_MODE_SD_MMC
| SSP_CTRL1_WORD_LENGTH_EIGHT_BITS
);
351 /* Set initial bit clock 400 KHz */
352 mx28_set_ssp_busclock(priv
->id
, 400);
354 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
355 writel(SSP_CMD0_CONT_CLKING_EN
, &ssp_regs
->hw_ssp_cmd0_set
);
357 writel(SSP_CMD0_CONT_CLKING_EN
, &ssp_regs
->hw_ssp_cmd0_clr
);
362 int mxsmmc_initialize(bd_t
*bis
, int id
, int (*wp
)(int))
364 struct mxs_clkctrl_regs
*clkctrl_regs
=
365 (struct mxs_clkctrl_regs
*)MXS_CLKCTRL_BASE
;
366 struct mmc
*mmc
= NULL
;
367 struct mxsmmc_priv
*priv
= NULL
;
370 mmc
= malloc(sizeof(struct mmc
));
374 priv
= malloc(sizeof(struct mxsmmc_priv
));
380 priv
->desc
= mxs_dma_desc_alloc();
387 ret
= mxs_dma_init_channel(id
);
391 priv
->mmc_is_wp
= wp
;
395 priv
->regs
= (struct mxs_ssp_regs
*)MXS_SSP0_BASE
;
396 priv
->clkseq_bypass
= CLKCTRL_CLKSEQ_BYPASS_SSP0
;
397 priv
->clkctrl_ssp
= &clkctrl_regs
->hw_clkctrl_ssp0
;
400 priv
->regs
= (struct mxs_ssp_regs
*)MXS_SSP1_BASE
;
401 priv
->clkseq_bypass
= CLKCTRL_CLKSEQ_BYPASS_SSP1
;
402 priv
->clkctrl_ssp
= &clkctrl_regs
->hw_clkctrl_ssp1
;
405 priv
->regs
= (struct mxs_ssp_regs
*)MXS_SSP2_BASE
;
406 priv
->clkseq_bypass
= CLKCTRL_CLKSEQ_BYPASS_SSP2
;
407 priv
->clkctrl_ssp
= &clkctrl_regs
->hw_clkctrl_ssp2
;
410 priv
->regs
= (struct mxs_ssp_regs
*)MXS_SSP3_BASE
;
411 priv
->clkseq_bypass
= CLKCTRL_CLKSEQ_BYPASS_SSP3
;
412 priv
->clkctrl_ssp
= &clkctrl_regs
->hw_clkctrl_ssp3
;
416 sprintf(mmc
->name
, "MXS MMC");
417 mmc
->send_cmd
= mxsmmc_send_cmd
;
418 mmc
->set_ios
= mxsmmc_set_ios
;
419 mmc
->init
= mxsmmc_init
;
423 mmc
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
425 mmc
->host_caps
= MMC_MODE_4BIT
| MMC_MODE_8BIT
|
426 MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
429 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
430 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
431 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
432 * CLOCK_RATE could be any integer from 0 to 255.
435 mmc
->f_max
= mxc_get_clock(MXC_SSP0_CLK
+ id
) * 1000 / 2;