drivers/mmc/mxsmmc.c

   1 /*
   2  * Freescale i.MX28 SSP MMC driver
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * Based on code from LTIB:
   8  * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
   9  * Terry Lv
  10  *
  11  * Copyright 2007, Freescale Semiconductor, Inc
  12  * Andy Fleming
  13  *
  14  * Based vaguely on the pxa mmc code:
  15  * (C) Copyright 2003
  16  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  17  *
  18  * See file CREDITS for list of people who contributed to this
  19  * project.
  20  *
  21  * This program is free software; you can redistribute it and/or
  22  * modify it under the terms of the GNU General Public License as
  23  * published by the Free Software Foundation; either version 2 of
  24  * the License, or (at your option) any later version.
  25  *
  26  * This program is distributed in the hope that it will be useful,
  27  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  28  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  29  * GNU General Public License for more details.
  30  *
  31  * You should have received a copy of the GNU General Public License
  32  * along with this program; if not, write to the Free Software
  33  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  34  * MA 02111-1307 USA
  35  */
  36 #include <common.h>
  37 #include <malloc.h>
  38 #include <mmc.h>
  39 #include <asm/errno.h>
  40 #include <asm/io.h>
  41 #include <asm/arch/clock.h>
  42 #include <asm/arch/imx-regs.h>
  43 #include <asm/arch/sys_proto.h>
  44 #include <asm/arch/dma.h>
  45 #include <bouncebuf.h>
  46
  47 struct mxsmmc_priv {
  48         int                     id;
  49         struct mxs_ssp_regs     *regs;
  50         uint32_t                clkseq_bypass;
  51         uint32_t                *clkctrl_ssp;
  52         uint32_t                buswidth;
  53         int                     (*mmc_is_wp)(int);
  54         struct mxs_dma_desc     *desc;
  55 };
  56
  57 #define MXSMMC_MAX_TIMEOUT      10000
  58 #define MXSMMC_SMALL_TRANSFER   512
  59
  60 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
  61 {
  62         struct mxs_ssp_regs *ssp_regs = priv->regs;
  63         uint32_t *data_ptr;
  64         int timeout = MXSMMC_MAX_TIMEOUT;
  65         uint32_t reg;
  66         uint32_t data_count = data->blocksize * data->blocks;
  67
  68         if (data->flags & MMC_DATA_READ) {
  69                 data_ptr = (uint32_t *)data->dest;
  70                 while (data_count && --timeout) {
  71                         reg = readl(&ssp_regs->hw_ssp_status);
  72                         if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
  73                                 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
  74                                 data_count -= 4;
  75                                 timeout = MXSMMC_MAX_TIMEOUT;
  76                         } else
  77                                 udelay(1000);
  78                 }
  79         } else {
  80                 data_ptr = (uint32_t *)data->src;
  81                 timeout *= 100;
  82                 while (data_count && --timeout) {
  83                         reg = readl(&ssp_regs->hw_ssp_status);
  84                         if (!(reg & SSP_STATUS_FIFO_FULL)) {
  85                                 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
  86                                 data_count -= 4;
  87                                 timeout = MXSMMC_MAX_TIMEOUT;
  88                         } else
  89                                 udelay(1000);
  90                 }
  91         }
  92
  93         return timeout ? 0 : COMM_ERR;
  94 }
  95
  96 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
  97 {
  98         uint32_t data_count = data->blocksize * data->blocks;
  99         int dmach;
 100         struct mxs_dma_desc *desc = priv->desc;
 101         void *addr;
 102         unsigned int flags;
 103         struct bounce_buffer bbstate;
 104
 105         memset(desc, 0, sizeof(struct mxs_dma_desc));
 106         desc->address = (dma_addr_t)desc;
 107
 108         if (data->flags & MMC_DATA_READ) {
 109                 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
 110                 addr = data->dest;
 111                 flags = GEN_BB_WRITE;
 112         } else {
 113                 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
 114                 addr = (void *)data->src;
 115                 flags = GEN_BB_READ;
 116         }
 117
 118         bounce_buffer_start(&bbstate, addr, data_count, flags);
 119
 120         priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
 121
 122         priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
 123                                 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
 124
 125         dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
 126         mxs_dma_desc_append(dmach, priv->desc);
 127         if (mxs_dma_go(dmach)) {
 128                 bounce_buffer_stop(&bbstate);
 129                 return COMM_ERR;
 130         }
 131
 132         bounce_buffer_stop(&bbstate);
 133
 134         return 0;
 135 }
 136
 137 /*
 138  * Sends a command out on the bus.  Takes the mmc pointer,
 139  * a command pointer, and an optional data pointer.
 140  */
 141 static int
 142 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 143 {
 144         struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
 145         struct mxs_ssp_regs *ssp_regs = priv->regs;
 146         uint32_t reg;
 147         int timeout;
 148         uint32_t ctrl0;
 149         int ret;
 150
 151         debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
 152
 153         /* Check bus busy */
 154         timeout = MXSMMC_MAX_TIMEOUT;
 155         while (--timeout) {
 156                 udelay(1000);
 157                 reg = readl(&ssp_regs->hw_ssp_status);
 158                 if (!(reg &
 159                         (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
 160                         SSP_STATUS_CMD_BUSY))) {
 161                         break;
 162                 }
 163         }
 164
 165         if (!timeout) {
 166                 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
 167                 return TIMEOUT;
 168         }
 169
 170         /* See if card is present */
 171         if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
 172                 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
 173                 return NO_CARD_ERR;
 174         }
 175
 176         /* Start building CTRL0 contents */
 177         ctrl0 = priv->buswidth;
 178
 179         /* Set up command */
 180         if (!(cmd->resp_type & MMC_RSP_CRC))
 181                 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
 182         if (cmd->resp_type & MMC_RSP_PRESENT)   /* Need to get response */
 183                 ctrl0 |= SSP_CTRL0_GET_RESP;
 184         if (cmd->resp_type & MMC_RSP_136)       /* It's a 136 bits response */
 185                 ctrl0 |= SSP_CTRL0_LONG_RESP;
 186
 187         if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
 188                 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
 189         else
 190                 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
 191
 192         /* Command index */
 193         reg = readl(&ssp_regs->hw_ssp_cmd0);
 194         reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
 195         reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
 196         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 197                 reg |= SSP_CMD0_APPEND_8CYC;
 198         writel(reg, &ssp_regs->hw_ssp_cmd0);
 199
 200         /* Command argument */
 201         writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
 202
 203         /* Set up data */
 204         if (data) {
 205                 /* READ or WRITE */
 206                 if (data->flags & MMC_DATA_READ) {
 207                         ctrl0 |= SSP_CTRL0_READ;
 208                 } else if (priv->mmc_is_wp &&
 209                         priv->mmc_is_wp(mmc->block_dev.dev)) {
 210                         printf("MMC%d: Can not write a locked card!\n",
 211                                 mmc->block_dev.dev);
 212                         return UNUSABLE_ERR;
 213                 }
 214
 215                 ctrl0 |= SSP_CTRL0_DATA_XFER;
 216                 reg = ((data->blocks - 1) <<
 217                         SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
 218                         ((ffs(data->blocksize) - 1) <<
 219                         SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
 220                 writel(reg, &ssp_regs->hw_ssp_block_size);
 221
 222                 reg = data->blocksize * data->blocks;
 223                 writel(reg, &ssp_regs->hw_ssp_xfer_size);
 224         }
 225
 226         /* Kick off the command */
 227         ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
 228         writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
 229
 230         /* Wait for the command to complete */
 231         timeout = MXSMMC_MAX_TIMEOUT;
 232         while (--timeout) {
 233                 udelay(1000);
 234                 reg = readl(&ssp_regs->hw_ssp_status);
 235                 if (!(reg & SSP_STATUS_CMD_BUSY))
 236                         break;
 237         }
 238
 239         if (!timeout) {
 240                 printf("MMC%d: Command %d busy\n",
 241                         mmc->block_dev.dev, cmd->cmdidx);
 242                 return TIMEOUT;
 243         }
 244
 245         /* Check command timeout */
 246         if (reg & SSP_STATUS_RESP_TIMEOUT) {
 247                 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
 248                         mmc->block_dev.dev, cmd->cmdidx, reg);
 249                 return TIMEOUT;
 250         }
 251
 252         /* Check command errors */
 253         if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
 254                 printf("MMC%d: Command %d error (status 0x%08x)!\n",
 255                         mmc->block_dev.dev, cmd->cmdidx, reg);
 256                 return COMM_ERR;
 257         }
 258
 259         /* Copy response to response buffer */
 260         if (cmd->resp_type & MMC_RSP_136) {
 261                 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
 262                 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
 263                 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
 264                 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
 265         } else
 266                 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
 267
 268         /* Return if no data to process */
 269         if (!data)
 270                 return 0;
 271
 272         if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
 273                 ret = mxsmmc_send_cmd_pio(priv, data);
 274                 if (ret) {
 275                         printf("MMC%d: Data timeout with command %d "
 276                                 "(status 0x%08x)!\n",
 277                                 mmc->block_dev.dev, cmd->cmdidx, reg);
 278                         return ret;
 279                 }
 280         } else {
 281                 ret = mxsmmc_send_cmd_dma(priv, data);
 282                 if (ret) {
 283                         printf("MMC%d: DMA transfer failed\n",
 284                                 mmc->block_dev.dev);
 285                         return ret;
 286                 }
 287         }
 288
 289         /* Check data errors */
 290         reg = readl(&ssp_regs->hw_ssp_status);
 291         if (reg &
 292                 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
 293                 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
 294                 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
 295                         mmc->block_dev.dev, cmd->cmdidx, reg);
 296                 return COMM_ERR;
 297         }
 298
 299         return 0;
 300 }
 301
 302 static void mxsmmc_set_ios(struct mmc *mmc)
 303 {
 304         struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
 305         struct mxs_ssp_regs *ssp_regs = priv->regs;
 306
 307         /* Set the clock speed */
 308         if (mmc->clock)
 309                 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000);
 310
 311         switch (mmc->bus_width) {
 312         case 1:
 313                 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
 314                 break;
 315         case 4:
 316                 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
 317                 break;
 318         case 8:
 319                 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
 320                 break;
 321         }
 322
 323         /* Set the bus width */
 324         clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
 325                         SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
 326
 327         debug("MMC%d: Set %d bits bus width\n",
 328                 mmc->block_dev.dev, mmc->bus_width);
 329 }
 330
 331 static int mxsmmc_init(struct mmc *mmc)
 332 {
 333         struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
 334         struct mxs_ssp_regs *ssp_regs = priv->regs;
 335
 336         /* Reset SSP */
 337         mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
 338
 339         /* 8 bits word length in MMC mode */
 340         clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
 341                 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK |
 342                 SSP_CTRL1_DMA_ENABLE,
 343                 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
 344
 345         /* Set initial bit clock 400 KHz */
 346         mx28_set_ssp_busclock(priv->id, 400);
 347
 348         /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
 349         writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
 350         udelay(200);
 351         writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
 352
 353         return 0;
 354 }
 355
 356 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
 357 {
 358         struct mxs_clkctrl_regs *clkctrl_regs =
 359                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 360         struct mmc *mmc = NULL;
 361         struct mxsmmc_priv *priv = NULL;
 362         int ret;
 363
 364         mmc = malloc(sizeof(struct mmc));
 365         if (!mmc)
 366                 return -ENOMEM;
 367
 368         priv = malloc(sizeof(struct mxsmmc_priv));
 369         if (!priv) {
 370                 free(mmc);
 371                 return -ENOMEM;
 372         }
 373
 374         priv->desc = mxs_dma_desc_alloc();
 375         if (!priv->desc) {
 376                 free(priv);
 377                 free(mmc);
 378                 return -ENOMEM;
 379         }
 380
 381         ret = mxs_dma_init_channel(id);
 382         if (ret)
 383                 return ret;
 384
 385         priv->mmc_is_wp = wp;
 386         priv->id = id;
 387         switch (id) {
 388         case 0:
 389                 priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE;
 390                 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
 391                 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
 392                 break;
 393         case 1:
 394                 priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE;
 395                 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
 396                 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
 397                 break;
 398         case 2:
 399                 priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE;
 400                 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
 401                 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
 402                 break;
 403         case 3:
 404                 priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE;
 405                 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
 406                 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
 407                 break;
 408         }
 409
 410         sprintf(mmc->name, "MXS MMC");
 411         mmc->send_cmd = mxsmmc_send_cmd;
 412         mmc->set_ios = mxsmmc_set_ios;
 413         mmc->init = mxsmmc_init;
 414         mmc->getcd = NULL;
 415         mmc->priv = priv;
 416
 417         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 418
 419         mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
 420                          MMC_MODE_HS_52MHz | MMC_MODE_HS;
 421
 422         /*
 423          * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
 424          * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
 425          * CLOCK_DIVIDE has to be an even value from 2 to 254, and
 426          * CLOCK_RATE could be any integer from 0 to 255.
 427          */
 428         mmc->f_min = 400000;
 429         mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;
 430         mmc->b_max = 0x20;
 431
 432         mmc_register(mmc);
 433         return 0;
 434 }