3 * Texas Instruments, <www.ti.com>
4 * Syed Mohammed Khasim <khasim@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include "omap3_mmc.h"
36 static const unsigned short mmc_transspeed_val
[15][4] = {
37 {CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)},
38 {CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)},
39 {CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)},
40 {CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)},
41 {CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)},
42 {CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)},
43 {CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)},
44 {CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)},
45 {CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)},
46 {CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)},
47 {CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)},
48 {CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)},
49 {CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)},
50 {CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)},
51 {CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)}
54 static mmc_card_data cur_card_data
;
55 static block_dev_desc_t mmc_blk_dev
;
56 static hsmmc_t
*mmc_base
= (hsmmc_t
*)OMAP_HSMMC1_BASE
;
58 int mmc_set_dev(int dev_num
)
62 mmc_base
= (hsmmc_t
*)OMAP_HSMMC1_BASE
;
65 mmc_base
= (hsmmc_t
*)OMAP_HSMMC2_BASE
;
68 mmc_base
= (hsmmc_t
*)OMAP_HSMMC3_BASE
;
71 mmc_base
= (hsmmc_t
*)OMAP_HSMMC1_BASE
;
78 block_dev_desc_t
*mmc_get_dev(int dev
)
80 return (block_dev_desc_t
*) &mmc_blk_dev
;
83 static unsigned char mmc_board_init(void)
85 #if defined(CONFIG_TWL4030_POWER)
86 twl4030_power_mmc_init();
89 #if defined(CONFIG_OMAP34XX)
90 t2_t
*t2_base
= (t2_t
*)T2_BASE
;
91 struct prcm
*prcm_base
= (struct prcm
*)PRCM_BASE
;
93 writel(readl(&t2_base
->pbias_lite
) | PBIASLITEPWRDNZ1
|
94 PBIASSPEEDCTRL0
| PBIASLITEPWRDNZ0
,
95 &t2_base
->pbias_lite
);
97 writel(readl(&t2_base
->devconf0
) | MMCSDIO1ADPCLKISEL
,
100 writel(readl(&t2_base
->devconf1
) | MMCSDIO2ADPCLKISEL
,
103 writel(readl(&prcm_base
->fclken1_core
) |
104 EN_MMC1
| EN_MMC2
| EN_MMC3
,
105 &prcm_base
->fclken1_core
);
107 writel(readl(&prcm_base
->iclken1_core
) |
108 EN_MMC1
| EN_MMC2
| EN_MMC3
,
109 &prcm_base
->iclken1_core
);
112 /* TODO add appropriate OMAP4 init */
117 static void mmc_init_stream(void)
119 writel(readl(&mmc_base
->con
) | INIT_INITSTREAM
, &mmc_base
->con
);
121 writel(MMC_CMD0
, &mmc_base
->cmd
);
122 while (!(readl(&mmc_base
->stat
) & CC_MASK
));
124 writel(CC_MASK
, &mmc_base
->stat
);
126 writel(MMC_CMD0
, &mmc_base
->cmd
);
127 while (!(readl(&mmc_base
->stat
) & CC_MASK
));
129 writel(readl(&mmc_base
->con
) & ~INIT_INITSTREAM
, &mmc_base
->con
);
132 static unsigned char mmc_clock_config(unsigned int iclk
, unsigned short clk_div
)
136 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
137 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
141 val
= MMC_INIT_SEQ_CLK
/ 2;
144 val
= MMC_400kHz_CLK
;
152 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
153 (val
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
155 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
);
157 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
161 static unsigned char mmc_init_setup(void)
163 unsigned int reg_val
;
167 writel(readl(&mmc_base
->sysconfig
) | MMC_SOFTRESET
,
168 &mmc_base
->sysconfig
);
169 while ((readl(&mmc_base
->sysstatus
) & RESETDONE
) == 0);
171 writel(readl(&mmc_base
->sysctl
) | SOFTRESETALL
, &mmc_base
->sysctl
);
172 while ((readl(&mmc_base
->sysctl
) & SOFTRESETALL
) != 0x0);
174 writel(DTW_1_BITMODE
| SDBP_PWROFF
| SDVS_3V0
, &mmc_base
->hctl
);
175 writel(readl(&mmc_base
->capa
) | VS30_3V0SUP
| VS18_1V8SUP
,
178 reg_val
= readl(&mmc_base
->con
) & RESERVED_MASK
;
180 writel(CTPL_MMC_SD
| reg_val
| WPP_ACTIVEHIGH
| CDP_ACTIVEHIGH
|
181 MIT_CTO
| DW8_1_4BITMODE
| MODE_FUNC
| STR_BLOCK
|
182 HR_NOHOSTRESP
| INIT_NOINIT
| NOOPENDRAIN
, &mmc_base
->con
);
184 mmc_clock_config(CLK_INITSEQ
, 0);
185 writel(readl(&mmc_base
->hctl
) | SDBP_PWRON
, &mmc_base
->hctl
);
187 writel(IE_BADA
| IE_CERR
| IE_DEB
| IE_DCRC
| IE_DTO
| IE_CIE
|
188 IE_CEB
| IE_CCRC
| IE_CTO
| IE_BRR
| IE_BWR
| IE_TC
| IE_CC
,
195 static unsigned char mmc_send_cmd(unsigned int cmd
, unsigned int arg
,
196 unsigned int *response
)
198 unsigned int mmc_stat
;
200 while ((readl(&mmc_base
->pstate
) & DATI_MASK
) == DATI_CMDDIS
);
202 writel(BLEN_512BYTESLEN
| NBLK_STPCNT
, &mmc_base
->blk
);
203 writel(0xFFFFFFFF, &mmc_base
->stat
);
204 writel(arg
, &mmc_base
->arg
);
205 writel(cmd
| CMD_TYPE_NORMAL
| CICE_NOCHECK
| CCCE_NOCHECK
|
206 MSBS_SGLEBLK
| ACEN_DISABLE
| BCE_DISABLE
| DE_DISABLE
,
211 mmc_stat
= readl(&mmc_base
->stat
);
212 } while (mmc_stat
== 0);
214 if ((mmc_stat
& ERRI_MASK
) != 0)
215 return (unsigned char) mmc_stat
;
217 if (mmc_stat
& CC_MASK
) {
218 writel(CC_MASK
, &mmc_base
->stat
);
219 response
[0] = readl(&mmc_base
->rsp10
);
220 if ((cmd
& RSP_TYPE_MASK
) == RSP_TYPE_LGHT136
) {
221 response
[1] = readl(&mmc_base
->rsp32
);
222 response
[2] = readl(&mmc_base
->rsp54
);
223 response
[3] = readl(&mmc_base
->rsp76
);
231 static unsigned char mmc_read_data(unsigned int *output_buf
)
233 unsigned int mmc_stat
;
234 unsigned int read_count
= 0;
241 mmc_stat
= readl(&mmc_base
->stat
);
242 } while (mmc_stat
== 0);
244 if ((mmc_stat
& ERRI_MASK
) != 0)
245 return (unsigned char) mmc_stat
;
247 if (mmc_stat
& BRR_MASK
) {
250 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
252 for (k
= 0; k
< MMCSD_SECTOR_SIZE
/ 4; k
++) {
253 *output_buf
= readl(&mmc_base
->data
);
259 if (mmc_stat
& BWR_MASK
)
260 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
263 if (mmc_stat
& TC_MASK
) {
264 writel(readl(&mmc_base
->stat
) | TC_MASK
,
272 static unsigned char mmc_detect_card(mmc_card_data
*mmc_card_cur
)
275 unsigned int argument
= 0;
276 unsigned int ocr_value
, ocr_recvd
, ret_cmd41
, hcs_val
;
277 unsigned short retry_cnt
= 2000;
280 /* Set to Initialization Clock */
281 err
= mmc_clock_config(CLK_400KHZ
, 0);
285 mmc_card_cur
->RCA
= MMC_RELATIVE_CARD_ADDRESS
;
286 argument
= 0x00000000;
288 ocr_value
= (0x1FF << 15);
289 err
= mmc_send_cmd(MMC_CMD0
, argument
, mmc_resp
.resp
);
293 argument
= SD_CMD8_CHECK_PATTERN
| SD_CMD8_2_7_3_6_V_RANGE
;
294 err
= mmc_send_cmd(MMC_SDCMD8
, argument
, mmc_resp
.resp
);
295 hcs_val
= (err
== 1) ?
296 MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR
:
297 MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE
;
299 argument
= 0x0000 << 16;
300 err
= mmc_send_cmd(MMC_CMD55
, argument
, mmc_resp
.resp
);
302 mmc_card_cur
->card_type
= SD_CARD
;
303 ocr_value
|= hcs_val
;
304 ret_cmd41
= MMC_ACMD41
;
306 mmc_card_cur
->card_type
= MMC_CARD
;
307 ocr_value
|= MMC_OCR_REG_ACCESS_MODE_SECTOR
;
308 ret_cmd41
= MMC_CMD1
;
309 writel(readl(&mmc_base
->con
) & ~OD
, &mmc_base
->con
);
310 writel(readl(&mmc_base
->con
) | OPENDRAIN
, &mmc_base
->con
);
313 argument
= ocr_value
;
314 err
= mmc_send_cmd(ret_cmd41
, argument
, mmc_resp
.resp
);
318 ocr_recvd
= mmc_resp
.r3
.ocr
;
320 while (!(ocr_recvd
& (0x1 << 31)) && (retry_cnt
> 0)) {
322 if (mmc_card_cur
->card_type
== SD_CARD
) {
323 argument
= 0x0000 << 16;
324 err
= mmc_send_cmd(MMC_CMD55
, argument
, mmc_resp
.resp
);
327 argument
= ocr_value
;
328 err
= mmc_send_cmd(ret_cmd41
, argument
, mmc_resp
.resp
);
331 ocr_recvd
= mmc_resp
.r3
.ocr
;
334 if (!(ocr_recvd
& (0x1 << 31)))
337 if (mmc_card_cur
->card_type
== MMC_CARD
) {
338 if ((ocr_recvd
& MMC_OCR_REG_ACCESS_MODE_MASK
) ==
339 MMC_OCR_REG_ACCESS_MODE_SECTOR
) {
340 mmc_card_cur
->mode
= SECTOR_MODE
;
342 mmc_card_cur
->mode
= BYTE_MODE
;
345 ocr_recvd
&= ~MMC_OCR_REG_ACCESS_MODE_MASK
;
347 if ((ocr_recvd
& MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK
)
348 == MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR
) {
349 mmc_card_cur
->mode
= SECTOR_MODE
;
351 mmc_card_cur
->mode
= BYTE_MODE
;
353 ocr_recvd
&= ~MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK
;
356 ocr_recvd
&= ~(0x1 << 31);
357 if (!(ocr_recvd
& ocr_value
))
360 err
= mmc_send_cmd(MMC_CMD2
, argument
, mmc_resp
.resp
);
364 if (mmc_card_cur
->card_type
== MMC_CARD
) {
365 argument
= mmc_card_cur
->RCA
<< 16;
366 err
= mmc_send_cmd(MMC_CMD3
, argument
, mmc_resp
.resp
);
370 argument
= 0x00000000;
371 err
= mmc_send_cmd(MMC_SDCMD3
, argument
, mmc_resp
.resp
);
375 mmc_card_cur
->RCA
= mmc_resp
.r6
.newpublishedrca
;
378 writel(readl(&mmc_base
->con
) & ~OD
, &mmc_base
->con
);
379 writel(readl(&mmc_base
->con
) | NOOPENDRAIN
, &mmc_base
->con
);
383 static unsigned char mmc_read_cardsize(mmc_card_data
*mmc_dev_data
,
384 mmc_csd_reg_t
*cur_csd
)
386 mmc_extended_csd_reg_t ext_csd
;
387 unsigned int size
, count
, blk_len
, blk_no
, card_size
, argument
;
389 unsigned int resp
[4];
391 if (mmc_dev_data
->mode
== SECTOR_MODE
) {
392 if (mmc_dev_data
->card_type
== SD_CARD
) {
394 (((mmc_sd2_csd_reg_t
*) cur_csd
)->
395 c_size_lsb
& MMC_SD2_CSD_C_SIZE_LSB_MASK
) |
396 ((((mmc_sd2_csd_reg_t
*) cur_csd
)->
397 c_size_msb
& MMC_SD2_CSD_C_SIZE_MSB_MASK
)
398 << MMC_SD2_CSD_C_SIZE_MSB_OFFSET
);
399 mmc_dev_data
->size
= card_size
* 1024;
400 if (mmc_dev_data
->size
== 0)
403 argument
= 0x00000000;
404 err
= mmc_send_cmd(MMC_CMD8
, argument
, resp
);
407 err
= mmc_read_data((unsigned int *) &ext_csd
);
410 mmc_dev_data
->size
= ext_csd
.sectorcount
;
412 if (mmc_dev_data
->size
== 0)
413 mmc_dev_data
->size
= 8388608;
416 if (cur_csd
->c_size_mult
>= 8)
419 if (cur_csd
->read_bl_len
>= 12)
423 count
= 1 << (cur_csd
->c_size_mult
+ 2);
424 card_size
= (cur_csd
->c_size_lsb
& MMC_CSD_C_SIZE_LSB_MASK
) |
425 ((cur_csd
->c_size_msb
& MMC_CSD_C_SIZE_MSB_MASK
)
426 << MMC_CSD_C_SIZE_MSB_OFFSET
);
427 blk_no
= (card_size
+ 1) * count
;
428 blk_len
= 1 << cur_csd
->read_bl_len
;
429 size
= blk_no
* blk_len
;
430 mmc_dev_data
->size
= size
/ MMCSD_SECTOR_SIZE
;
431 if (mmc_dev_data
->size
== 0)
437 static unsigned long mmc_bread(int dev_num
, unsigned long blknr
,
438 lbaint_t blkcnt
, void *dst
)
441 unsigned int argument
;
442 unsigned int resp
[4];
443 unsigned int *output_buf
= dst
;
444 unsigned int sec_inc_val
;
450 if (cur_card_data
.mode
== SECTOR_MODE
) {
454 argument
= blknr
* MMCSD_SECTOR_SIZE
;
455 sec_inc_val
= MMCSD_SECTOR_SIZE
;
458 for (i
= 0; i
< blkcnt
; i
++) {
459 err
= mmc_send_cmd(MMC_CMD17
, argument
, resp
);
461 printf("mmc: CMD17 failed, status = %08x\n", err
);
465 err
= mmc_read_data(output_buf
);
467 printf("mmc: read failed, status = %08x\n", err
);
471 output_buf
+= (MMCSD_SECTOR_SIZE
/ 4);
472 argument
+= sec_inc_val
;
478 static unsigned char configure_mmc(mmc_card_data
*mmc_card_cur
)
480 unsigned char ret_val
;
481 unsigned int argument
;
482 unsigned int trans_clk
, trans_fact
, trans_unit
, retries
= 2;
483 unsigned char trans_speed
;
486 ret_val
= mmc_init_setup();
492 ret_val
= mmc_detect_card(mmc_card_cur
);
494 } while ((retries
> 0) && (ret_val
!= 1));
496 argument
= mmc_card_cur
->RCA
<< 16;
497 ret_val
= mmc_send_cmd(MMC_CMD9
, argument
, mmc_resp
.resp
);
501 if (mmc_card_cur
->card_type
== MMC_CARD
)
502 mmc_card_cur
->version
= mmc_resp
.Card_CSD
.spec_vers
;
504 trans_speed
= mmc_resp
.Card_CSD
.tran_speed
;
506 ret_val
= mmc_send_cmd(MMC_CMD4
, MMC_DSR_DEFAULT
<< 16, mmc_resp
.resp
);
510 trans_unit
= trans_speed
& MMC_CSD_TRAN_SPEED_UNIT_MASK
;
511 trans_fact
= trans_speed
& MMC_CSD_TRAN_SPEED_FACTOR_MASK
;
513 if (trans_unit
> MMC_CSD_TRAN_SPEED_UNIT_100MHZ
)
516 if ((trans_fact
< MMC_CSD_TRAN_SPEED_FACTOR_1_0
) ||
517 (trans_fact
> MMC_CSD_TRAN_SPEED_FACTOR_8_0
))
523 trans_clk
= mmc_transspeed_val
[trans_fact
- 1][trans_unit
] * 2;
524 ret_val
= mmc_clock_config(CLK_MISC
, trans_clk
);
529 argument
= mmc_card_cur
->RCA
<< 16;
530 ret_val
= mmc_send_cmd(MMC_CMD7_SELECT
, argument
, mmc_resp
.resp
);
534 /* Configure the block length to 512 bytes */
535 argument
= MMCSD_SECTOR_SIZE
;
536 ret_val
= mmc_send_cmd(MMC_CMD16
, argument
, mmc_resp
.resp
);
540 /* get the card size in sectors */
541 ret_val
= mmc_read_cardsize(mmc_card_cur
, &mmc_resp
.Card_CSD
);
548 int mmc_legacy_init(int dev
)
550 if (mmc_set_dev(dev
) != 0)
553 if (configure_mmc(&cur_card_data
) != 1)
556 mmc_blk_dev
.if_type
= IF_TYPE_MMC
;
557 mmc_blk_dev
.part_type
= PART_TYPE_DOS
;
560 mmc_blk_dev
.type
= 0;
562 /* FIXME fill in the correct size (is set to 32MByte) */
563 mmc_blk_dev
.blksz
= MMCSD_SECTOR_SIZE
;
564 mmc_blk_dev
.lba
= 0x10000;
565 mmc_blk_dev
.removable
= 0;
566 mmc_blk_dev
.block_read
= mmc_bread
;
568 fat_register_device(&mmc_blk_dev
, 1);