3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/arch/mmc_host_def.h>
36 #if !defined(CONFIG_SOC_KEYSTONE)
38 #include <asm/arch/sys_proto.h>
42 DECLARE_GLOBAL_DATA_PTR
;
44 /* simplify defines to OMAP_HSMMC_USE_GPIO */
45 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
46 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
47 #define OMAP_HSMMC_USE_GPIO
49 #undef OMAP_HSMMC_USE_GPIO
52 /* common definitions for all OMAPs */
53 #define SYSCTL_SRC (1 << 25)
54 #define SYSCTL_SRD (1 << 26)
56 struct omap_hsmmc_data
{
57 struct hsmmc
*base_addr
;
58 struct mmc_config cfg
;
59 #ifdef OMAP_HSMMC_USE_GPIO
61 struct gpio_desc cd_gpio
; /* Change Detect GPIO */
62 struct gpio_desc wp_gpio
; /* Write Protect GPIO */
71 /* If we fail after 1 second wait, something is really bad */
72 #define MAX_RETRY_MS 1000
74 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
);
75 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
78 #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
79 static int omap_mmc_setup_gpio_in(int gpio
, const char *label
)
83 #ifndef CONFIG_DM_GPIO
84 if (!gpio_is_valid(gpio
))
87 ret
= gpio_request(gpio
, label
);
91 ret
= gpio_direction_input(gpio
);
99 #if defined(CONFIG_OMAP44XX)
100 static void omap4_vmmc_pbias_config(struct mmc
*mmc
)
104 value
= readl((*ctrl
)->control_pbiaslite
);
105 value
&= ~(MMC1_PBIASLITE_PWRDNZ
| MMC1_PWRDNZ
);
106 writel(value
, (*ctrl
)->control_pbiaslite
);
107 value
= readl((*ctrl
)->control_pbiaslite
);
108 value
|= MMC1_PBIASLITE_VMODE
| MMC1_PBIASLITE_PWRDNZ
| MMC1_PWRDNZ
;
109 writel(value
, (*ctrl
)->control_pbiaslite
);
113 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
114 static void omap5_pbias_config(struct mmc
*mmc
)
118 value
= readl((*ctrl
)->control_pbias
);
119 value
&= ~SDCARD_PWRDNZ
;
120 writel(value
, (*ctrl
)->control_pbias
);
121 udelay(10); /* wait 10 us */
122 value
&= ~SDCARD_BIAS_PWRDNZ
;
123 writel(value
, (*ctrl
)->control_pbias
);
125 palmas_mmc1_poweron_ldo();
127 value
= readl((*ctrl
)->control_pbias
);
128 value
|= SDCARD_BIAS_PWRDNZ
;
129 writel(value
, (*ctrl
)->control_pbias
);
130 udelay(150); /* wait 150 us */
131 value
|= SDCARD_PWRDNZ
;
132 writel(value
, (*ctrl
)->control_pbias
);
133 udelay(150); /* wait 150 us */
137 static unsigned char mmc_board_init(struct mmc
*mmc
)
139 #if defined(CONFIG_OMAP34XX)
140 t2_t
*t2_base
= (t2_t
*)T2_BASE
;
141 struct prcm
*prcm_base
= (struct prcm
*)PRCM_BASE
;
144 pbias_lite
= readl(&t2_base
->pbias_lite
);
145 pbias_lite
&= ~(PBIASLITEPWRDNZ1
| PBIASLITEPWRDNZ0
);
146 #ifdef CONFIG_TARGET_OMAP3_CAIRO
147 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
148 pbias_lite
&= ~PBIASLITEVMODE0
;
150 writel(pbias_lite
, &t2_base
->pbias_lite
);
152 writel(pbias_lite
| PBIASLITEPWRDNZ1
|
153 PBIASSPEEDCTRL0
| PBIASLITEPWRDNZ0
,
154 &t2_base
->pbias_lite
);
156 writel(readl(&t2_base
->devconf0
) | MMCSDIO1ADPCLKISEL
,
159 writel(readl(&t2_base
->devconf1
) | MMCSDIO2ADPCLKISEL
,
162 /* Change from default of 52MHz to 26MHz if necessary */
163 if (!(mmc
->cfg
->host_caps
& MMC_MODE_HS_52MHz
))
164 writel(readl(&t2_base
->ctl_prog_io1
) & ~CTLPROGIO1SPEEDCTRL
,
165 &t2_base
->ctl_prog_io1
);
167 writel(readl(&prcm_base
->fclken1_core
) |
168 EN_MMC1
| EN_MMC2
| EN_MMC3
,
169 &prcm_base
->fclken1_core
);
171 writel(readl(&prcm_base
->iclken1_core
) |
172 EN_MMC1
| EN_MMC2
| EN_MMC3
,
173 &prcm_base
->iclken1_core
);
176 #if defined(CONFIG_OMAP44XX)
177 /* PBIAS config needed for MMC1 only */
178 if (mmc
->block_dev
.devnum
== 0)
179 omap4_vmmc_pbias_config(mmc
);
181 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
182 if (mmc
->block_dev
.devnum
== 0)
183 omap5_pbias_config(mmc
);
189 void mmc_init_stream(struct hsmmc
*mmc_base
)
193 writel(readl(&mmc_base
->con
) | INIT_INITSTREAM
, &mmc_base
->con
);
195 writel(MMC_CMD0
, &mmc_base
->cmd
);
196 start
= get_timer(0);
197 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
198 if (get_timer(0) - start
> MAX_RETRY_MS
) {
199 printf("%s: timedout waiting for cc!\n", __func__
);
203 writel(CC_MASK
, &mmc_base
->stat
)
205 writel(MMC_CMD0
, &mmc_base
->cmd
)
207 start
= get_timer(0);
208 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
209 if (get_timer(0) - start
> MAX_RETRY_MS
) {
210 printf("%s: timedout waiting for cc2!\n", __func__
);
214 writel(readl(&mmc_base
->con
) & ~INIT_INITSTREAM
, &mmc_base
->con
);
218 static int omap_hsmmc_init_setup(struct mmc
*mmc
)
220 struct hsmmc
*mmc_base
;
221 unsigned int reg_val
;
225 mmc_base
= ((struct omap_hsmmc_data
*)mmc
->priv
)->base_addr
;
228 writel(readl(&mmc_base
->sysconfig
) | MMC_SOFTRESET
,
229 &mmc_base
->sysconfig
);
230 start
= get_timer(0);
231 while ((readl(&mmc_base
->sysstatus
) & RESETDONE
) == 0) {
232 if (get_timer(0) - start
> MAX_RETRY_MS
) {
233 printf("%s: timedout waiting for cc2!\n", __func__
);
237 writel(readl(&mmc_base
->sysctl
) | SOFTRESETALL
, &mmc_base
->sysctl
);
238 start
= get_timer(0);
239 while ((readl(&mmc_base
->sysctl
) & SOFTRESETALL
) != 0x0) {
240 if (get_timer(0) - start
> MAX_RETRY_MS
) {
241 printf("%s: timedout waiting for softresetall!\n",
246 writel(DTW_1_BITMODE
| SDBP_PWROFF
| SDVS_3V0
, &mmc_base
->hctl
);
247 writel(readl(&mmc_base
->capa
) | VS30_3V0SUP
| VS18_1V8SUP
,
250 reg_val
= readl(&mmc_base
->con
) & RESERVED_MASK
;
252 writel(CTPL_MMC_SD
| reg_val
| WPP_ACTIVEHIGH
| CDP_ACTIVEHIGH
|
253 MIT_CTO
| DW8_1_4BITMODE
| MODE_FUNC
| STR_BLOCK
|
254 HR_NOHOSTRESP
| INIT_NOINIT
| NOOPENDRAIN
, &mmc_base
->con
);
257 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
258 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
259 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
260 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
261 start
= get_timer(0);
262 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
263 if (get_timer(0) - start
> MAX_RETRY_MS
) {
264 printf("%s: timedout waiting for ics!\n", __func__
);
268 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
270 writel(readl(&mmc_base
->hctl
) | SDBP_PWRON
, &mmc_base
->hctl
);
272 writel(IE_BADA
| IE_CERR
| IE_DEB
| IE_DCRC
| IE_DTO
| IE_CIE
|
273 IE_CEB
| IE_CCRC
| IE_CTO
| IE_BRR
| IE_BWR
| IE_TC
| IE_CC
,
276 mmc_init_stream(mmc_base
);
282 * MMC controller internal finite state machine reset
284 * Used to reset command or data internal state machines, using respectively
285 * SRC or SRD bit of SYSCTL register
287 static void mmc_reset_controller_fsm(struct hsmmc
*mmc_base
, u32 bit
)
291 mmc_reg_out(&mmc_base
->sysctl
, bit
, bit
);
294 * CMD(DAT) lines reset procedures are slightly different
295 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
296 * According to OMAP3 TRM:
297 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
299 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
300 * procedure steps must be as follows:
301 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
302 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
303 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
304 * 3. Wait until the SRC (SRD) bit returns to 0x0
305 * (reset procedure is completed).
307 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
308 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
309 if (!(readl(&mmc_base
->sysctl
) & bit
)) {
310 start
= get_timer(0);
311 while (!(readl(&mmc_base
->sysctl
) & bit
)) {
312 if (get_timer(0) - start
> MAX_RETRY_MS
)
317 start
= get_timer(0);
318 while ((readl(&mmc_base
->sysctl
) & bit
) != 0) {
319 if (get_timer(0) - start
> MAX_RETRY_MS
) {
320 printf("%s: timedout waiting for sysctl %x to clear\n",
327 static int omap_hsmmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
328 struct mmc_data
*data
)
330 struct hsmmc
*mmc_base
;
331 unsigned int flags
, mmc_stat
;
334 mmc_base
= ((struct omap_hsmmc_data
*)mmc
->priv
)->base_addr
;
335 start
= get_timer(0);
336 while ((readl(&mmc_base
->pstate
) & (DATI_MASK
| CMDI_MASK
)) != 0) {
337 if (get_timer(0) - start
> MAX_RETRY_MS
) {
338 printf("%s: timedout waiting on cmd inhibit to clear\n",
343 writel(0xFFFFFFFF, &mmc_base
->stat
);
344 start
= get_timer(0);
345 while (readl(&mmc_base
->stat
)) {
346 if (get_timer(0) - start
> MAX_RETRY_MS
) {
347 printf("%s: timedout waiting for STAT (%x) to clear\n",
348 __func__
, readl(&mmc_base
->stat
));
354 * CMDIDX[13:8] : Command index
355 * DATAPRNT[5] : Data Present Select
356 * ENCMDIDX[4] : Command Index Check Enable
357 * ENCMDCRC[3] : Command CRC Check Enable
362 * 11 = Length 48 Check busy after response
364 /* Delay added before checking the status of frq change
365 * retry not supported by mmc.c(core file)
367 if (cmd
->cmdidx
== SD_CMD_APP_SEND_SCR
)
368 udelay(50000); /* wait 50 ms */
370 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
372 else if (cmd
->resp_type
& MMC_RSP_136
)
373 flags
= RSP_TYPE_LGHT136
| CICE_NOCHECK
;
374 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
375 flags
= RSP_TYPE_LGHT48B
;
377 flags
= RSP_TYPE_LGHT48
;
379 /* enable default flags */
380 flags
= flags
| (CMD_TYPE_NORMAL
| CICE_NOCHECK
| CCCE_NOCHECK
|
381 MSBS_SGLEBLK
| ACEN_DISABLE
| BCE_DISABLE
| DE_DISABLE
);
383 if (cmd
->resp_type
& MMC_RSP_CRC
)
385 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
389 if ((cmd
->cmdidx
== MMC_CMD_READ_MULTIPLE_BLOCK
) ||
390 (cmd
->cmdidx
== MMC_CMD_WRITE_MULTIPLE_BLOCK
)) {
391 flags
|= (MSBS_MULTIBLK
| BCE_ENABLE
);
392 data
->blocksize
= 512;
393 writel(data
->blocksize
| (data
->blocks
<< 16),
396 writel(data
->blocksize
| NBLK_STPCNT
, &mmc_base
->blk
);
398 if (data
->flags
& MMC_DATA_READ
)
399 flags
|= (DP_DATA
| DDIR_READ
);
401 flags
|= (DP_DATA
| DDIR_WRITE
);
404 writel(cmd
->cmdarg
, &mmc_base
->arg
);
405 udelay(20); /* To fix "No status update" error on eMMC */
406 writel((cmd
->cmdidx
<< 24) | flags
, &mmc_base
->cmd
);
408 start
= get_timer(0);
410 mmc_stat
= readl(&mmc_base
->stat
);
411 if (get_timer(0) - start
> MAX_RETRY_MS
) {
412 printf("%s : timeout: No status update\n", __func__
);
417 if ((mmc_stat
& IE_CTO
) != 0) {
418 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRC
);
420 } else if ((mmc_stat
& ERRI_MASK
) != 0)
423 if (mmc_stat
& CC_MASK
) {
424 writel(CC_MASK
, &mmc_base
->stat
);
425 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
426 if (cmd
->resp_type
& MMC_RSP_136
) {
427 /* response type 2 */
428 cmd
->response
[3] = readl(&mmc_base
->rsp10
);
429 cmd
->response
[2] = readl(&mmc_base
->rsp32
);
430 cmd
->response
[1] = readl(&mmc_base
->rsp54
);
431 cmd
->response
[0] = readl(&mmc_base
->rsp76
);
433 /* response types 1, 1b, 3, 4, 5, 6 */
434 cmd
->response
[0] = readl(&mmc_base
->rsp10
);
438 if (data
&& (data
->flags
& MMC_DATA_READ
)) {
439 mmc_read_data(mmc_base
, data
->dest
,
440 data
->blocksize
* data
->blocks
);
441 } else if (data
&& (data
->flags
& MMC_DATA_WRITE
)) {
442 mmc_write_data(mmc_base
, data
->src
,
443 data
->blocksize
* data
->blocks
);
448 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
)
450 unsigned int *output_buf
= (unsigned int *)buf
;
451 unsigned int mmc_stat
;
457 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
461 ulong start
= get_timer(0);
463 mmc_stat
= readl(&mmc_base
->stat
);
464 if (get_timer(0) - start
> MAX_RETRY_MS
) {
465 printf("%s: timedout waiting for status!\n",
469 } while (mmc_stat
== 0);
471 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
472 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
474 if ((mmc_stat
& ERRI_MASK
) != 0)
477 if (mmc_stat
& BRR_MASK
) {
480 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
482 for (k
= 0; k
< count
; k
++) {
483 *output_buf
= readl(&mmc_base
->data
);
489 if (mmc_stat
& BWR_MASK
)
490 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
493 if (mmc_stat
& TC_MASK
) {
494 writel(readl(&mmc_base
->stat
) | TC_MASK
,
502 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
505 unsigned int *input_buf
= (unsigned int *)buf
;
506 unsigned int mmc_stat
;
512 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
516 ulong start
= get_timer(0);
518 mmc_stat
= readl(&mmc_base
->stat
);
519 if (get_timer(0) - start
> MAX_RETRY_MS
) {
520 printf("%s: timedout waiting for status!\n",
524 } while (mmc_stat
== 0);
526 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
527 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
529 if ((mmc_stat
& ERRI_MASK
) != 0)
532 if (mmc_stat
& BWR_MASK
) {
535 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
537 for (k
= 0; k
< count
; k
++) {
538 writel(*input_buf
, &mmc_base
->data
);
544 if (mmc_stat
& BRR_MASK
)
545 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
548 if (mmc_stat
& TC_MASK
) {
549 writel(readl(&mmc_base
->stat
) | TC_MASK
,
557 static void omap_hsmmc_set_ios(struct mmc
*mmc
)
559 struct hsmmc
*mmc_base
;
560 unsigned int dsor
= 0;
563 mmc_base
= ((struct omap_hsmmc_data
*)mmc
->priv
)->base_addr
;
564 /* configue bus width */
565 switch (mmc
->bus_width
) {
567 writel(readl(&mmc_base
->con
) | DTW_8_BITMODE
,
572 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
574 writel(readl(&mmc_base
->hctl
) | DTW_4_BITMODE
,
580 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
582 writel(readl(&mmc_base
->hctl
) & ~DTW_4_BITMODE
,
587 /* configure clock with 96Mhz system clock.
589 if (mmc
->clock
!= 0) {
590 dsor
= (MMC_CLOCK_REFERENCE
* 1000000 / mmc
->clock
);
591 if ((MMC_CLOCK_REFERENCE
* 1000000) / dsor
> mmc
->clock
)
595 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
596 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
598 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
599 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
601 start
= get_timer(0);
602 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
603 if (get_timer(0) - start
> MAX_RETRY_MS
) {
604 printf("%s: timedout waiting for ics!\n", __func__
);
608 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
611 #ifdef OMAP_HSMMC_USE_GPIO
613 static int omap_hsmmc_getcd(struct mmc
*mmc
)
615 struct omap_hsmmc_data
*priv
= mmc
->priv
;
618 value
= dm_gpio_get_value(&priv
->cd_gpio
);
619 /* if no CD return as 1 */
623 if (priv
->cd_inverted
)
628 static int omap_hsmmc_getwp(struct mmc
*mmc
)
630 struct omap_hsmmc_data
*priv
= mmc
->priv
;
633 value
= dm_gpio_get_value(&priv
->wp_gpio
);
634 /* if no WP return as 0 */
640 static int omap_hsmmc_getcd(struct mmc
*mmc
)
642 struct omap_hsmmc_data
*priv_data
= mmc
->priv
;
645 /* if no CD return as 1 */
646 cd_gpio
= priv_data
->cd_gpio
;
650 /* NOTE: assumes card detect signal is active-low */
651 return !gpio_get_value(cd_gpio
);
654 static int omap_hsmmc_getwp(struct mmc
*mmc
)
656 struct omap_hsmmc_data
*priv_data
= mmc
->priv
;
659 /* if no WP return as 0 */
660 wp_gpio
= priv_data
->wp_gpio
;
664 /* NOTE: assumes write protect signal is active-high */
665 return gpio_get_value(wp_gpio
);
670 static const struct mmc_ops omap_hsmmc_ops
= {
671 .send_cmd
= omap_hsmmc_send_cmd
,
672 .set_ios
= omap_hsmmc_set_ios
,
673 .init
= omap_hsmmc_init_setup
,
674 #ifdef OMAP_HSMMC_USE_GPIO
675 .getcd
= omap_hsmmc_getcd
,
676 .getwp
= omap_hsmmc_getwp
,
680 #ifndef CONFIG_DM_MMC
681 int omap_mmc_init(int dev_index
, uint host_caps_mask
, uint f_max
, int cd_gpio
,
685 struct omap_hsmmc_data
*priv_data
;
686 struct mmc_config
*cfg
;
689 priv_data
= malloc(sizeof(*priv_data
));
690 if (priv_data
== NULL
)
693 host_caps_val
= MMC_MODE_4BIT
| MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
697 priv_data
->base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
699 #ifdef OMAP_HSMMC2_BASE
701 priv_data
->base_addr
= (struct hsmmc
*)OMAP_HSMMC2_BASE
;
702 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
703 defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
704 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
705 defined(CONFIG_HSMMC2_8BIT)
706 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
707 host_caps_val
|= MMC_MODE_8BIT
;
711 #ifdef OMAP_HSMMC3_BASE
713 priv_data
->base_addr
= (struct hsmmc
*)OMAP_HSMMC3_BASE
;
714 #if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
715 /* Enable 8-bit interface for eMMC on DRA7XX */
716 host_caps_val
|= MMC_MODE_8BIT
;
721 priv_data
->base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
724 #ifdef OMAP_HSMMC_USE_GPIO
725 /* on error gpio values are set to -1, which is what we want */
726 priv_data
->cd_gpio
= omap_mmc_setup_gpio_in(cd_gpio
, "mmc_cd");
727 priv_data
->wp_gpio
= omap_mmc_setup_gpio_in(wp_gpio
, "mmc_wp");
730 cfg
= &priv_data
->cfg
;
732 cfg
->name
= "OMAP SD/MMC";
733 cfg
->ops
= &omap_hsmmc_ops
;
735 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
736 cfg
->host_caps
= host_caps_val
& ~host_caps_mask
;
743 if (cfg
->host_caps
& MMC_MODE_HS
) {
744 if (cfg
->host_caps
& MMC_MODE_HS_52MHz
)
745 cfg
->f_max
= 52000000;
747 cfg
->f_max
= 26000000;
749 cfg
->f_max
= 20000000;
752 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
754 #if defined(CONFIG_OMAP34XX)
756 * Silicon revs 2.1 and older do not support multiblock transfers.
758 if ((get_cpu_family() == CPU_OMAP34XX
) && (get_cpu_rev() <= CPU_3XX_ES21
))
761 mmc
= mmc_create(cfg
, priv_data
);
768 static int omap_hsmmc_ofdata_to_platdata(struct udevice
*dev
)
770 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
771 const void *fdt
= gd
->fdt_blob
;
772 int node
= dev
->of_offset
;
773 struct mmc_config
*cfg
;
776 priv
->base_addr
= map_physmem(dev_get_addr(dev
), sizeof(struct hsmmc
*),
780 cfg
->host_caps
= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
781 val
= fdtdec_get_int(fdt
, node
, "bus-width", -1);
783 printf("error: bus-width property missing\n");
789 cfg
->host_caps
|= MMC_MODE_8BIT
;
791 cfg
->host_caps
|= MMC_MODE_4BIT
;
794 printf("error: invalid bus-width property\n");
799 cfg
->f_max
= fdtdec_get_int(fdt
, node
, "max-frequency", 52000000);
800 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
801 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
803 priv
->cd_inverted
= fdtdec_get_bool(fdt
, node
, "cd-inverted");
808 static int omap_hsmmc_probe(struct udevice
*dev
)
810 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
811 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
812 struct mmc_config
*cfg
;
816 cfg
->name
= "OMAP SD/MMC";
817 cfg
->ops
= &omap_hsmmc_ops
;
819 mmc
= mmc_create(cfg
, priv
);
828 static const struct udevice_id omap_hsmmc_ids
[] = {
829 { .compatible
= "ti,omap3-hsmmc" },
830 { .compatible
= "ti,omap4-hsmmc" },
831 { .compatible
= "ti,am33xx-hsmmc" },
835 U_BOOT_DRIVER(omap_hsmmc
) = {
836 .name
= "omap_hsmmc",
838 .of_match
= omap_hsmmc_ids
,
839 .ofdata_to_platdata
= omap_hsmmc_ofdata_to_platdata
,
840 .probe
= omap_hsmmc_probe
,
841 .priv_auto_alloc_size
= sizeof(struct omap_hsmmc_data
),