3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
36 #include <asm/arch/mmc_host_def.h>
37 #ifdef CONFIG_OMAP54XX
38 #include <asm/arch/mux_dra7xx.h>
39 #include <asm/arch/dra7xx_iodelay.h>
41 #if !defined(CONFIG_SOC_KEYSTONE)
43 #include <asm/arch/sys_proto.h>
45 #ifdef CONFIG_MMC_OMAP36XX_PINS
46 #include <asm/arch/mux.h>
50 DECLARE_GLOBAL_DATA_PTR
;
52 /* simplify defines to OMAP_HSMMC_USE_GPIO */
53 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
54 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
55 #define OMAP_HSMMC_USE_GPIO
57 #undef OMAP_HSMMC_USE_GPIO
60 /* common definitions for all OMAPs */
61 #define SYSCTL_SRC (1 << 25)
62 #define SYSCTL_SRD (1 << 26)
64 #ifdef CONFIG_IODELAY_RECALIBRATION
65 struct omap_hsmmc_pinctrl_state
{
66 struct pad_conf_entry
*padconf
;
68 struct iodelay_cfg_entry
*iodelay
;
73 struct omap_hsmmc_data
{
74 struct hsmmc
*base_addr
;
75 #if !CONFIG_IS_ENABLED(DM_MMC)
76 struct mmc_config cfg
;
80 #ifdef OMAP_HSMMC_USE_GPIO
81 #if CONFIG_IS_ENABLED(DM_MMC)
82 struct gpio_desc cd_gpio
; /* Change Detect GPIO */
83 struct gpio_desc wp_gpio
; /* Write Protect GPIO */
90 #if CONFIG_IS_ENABLED(DM_MMC)
95 #ifndef CONFIG_OMAP34XX
96 struct omap_hsmmc_adma_desc
*adma_desc_table
;
100 #ifdef CONFIG_IODELAY_RECALIBRATION
101 struct omap_hsmmc_pinctrl_state
*default_pinctrl_state
;
102 struct omap_hsmmc_pinctrl_state
*hs_pinctrl_state
;
103 struct omap_hsmmc_pinctrl_state
*hs200_1_8v_pinctrl_state
;
104 struct omap_hsmmc_pinctrl_state
*ddr_1_8v_pinctrl_state
;
105 struct omap_hsmmc_pinctrl_state
*sdr12_pinctrl_state
;
106 struct omap_hsmmc_pinctrl_state
*sdr25_pinctrl_state
;
107 struct omap_hsmmc_pinctrl_state
*ddr50_pinctrl_state
;
108 struct omap_hsmmc_pinctrl_state
*sdr50_pinctrl_state
;
109 struct omap_hsmmc_pinctrl_state
*sdr104_pinctrl_state
;
113 struct omap_mmc_of_data
{
117 #ifndef CONFIG_OMAP34XX
118 struct omap_hsmmc_adma_desc
{
125 #define ADMA_MAX_LEN 63488
127 /* Decriptor table defines */
128 #define ADMA_DESC_ATTR_VALID BIT(0)
129 #define ADMA_DESC_ATTR_END BIT(1)
130 #define ADMA_DESC_ATTR_INT BIT(2)
131 #define ADMA_DESC_ATTR_ACT1 BIT(4)
132 #define ADMA_DESC_ATTR_ACT2 BIT(5)
134 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
135 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
138 /* If we fail after 1 second wait, something is really bad */
139 #define MAX_RETRY_MS 1000
140 #define MMC_TIMEOUT_MS 20
142 /* DMA transfers can take a long time if a lot a data is transferred.
143 * The timeout must take in account the amount of data. Let's assume
144 * that the time will never exceed 333 ms per MB (in other word we assume
145 * that the bandwidth is always above 3MB/s).
147 #define DMA_TIMEOUT_PER_MB 333
148 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
149 #define OMAP_HSMMC_NO_1_8_V BIT(1)
150 #define OMAP_HSMMC_USE_ADMA BIT(2)
151 #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
153 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
);
154 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
156 static void omap_hsmmc_start_clock(struct hsmmc
*mmc_base
);
157 static void omap_hsmmc_stop_clock(struct hsmmc
*mmc_base
);
158 static void mmc_reset_controller_fsm(struct hsmmc
*mmc_base
, u32 bit
);
160 static inline struct omap_hsmmc_data
*omap_hsmmc_get_data(struct mmc
*mmc
)
162 #if CONFIG_IS_ENABLED(DM_MMC)
163 return dev_get_priv(mmc
->dev
);
165 return (struct omap_hsmmc_data
*)mmc
->priv
;
168 static inline struct mmc_config
*omap_hsmmc_get_cfg(struct mmc
*mmc
)
170 #if CONFIG_IS_ENABLED(DM_MMC)
171 struct omap_hsmmc_plat
*plat
= dev_get_platdata(mmc
->dev
);
174 return &((struct omap_hsmmc_data
*)mmc
->priv
)->cfg
;
178 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
179 static int omap_mmc_setup_gpio_in(int gpio
, const char *label
)
183 #ifndef CONFIG_DM_GPIO
184 if (!gpio_is_valid(gpio
))
187 ret
= gpio_request(gpio
, label
);
191 ret
= gpio_direction_input(gpio
);
199 static unsigned char mmc_board_init(struct mmc
*mmc
)
201 #if defined(CONFIG_OMAP34XX)
202 struct mmc_config
*cfg
= omap_hsmmc_get_cfg(mmc
);
203 t2_t
*t2_base
= (t2_t
*)T2_BASE
;
204 struct prcm
*prcm_base
= (struct prcm
*)PRCM_BASE
;
206 #ifdef CONFIG_MMC_OMAP36XX_PINS
207 u32 wkup_ctrl
= readl(OMAP34XX_CTRL_WKUP_CTRL
);
210 pbias_lite
= readl(&t2_base
->pbias_lite
);
211 pbias_lite
&= ~(PBIASLITEPWRDNZ1
| PBIASLITEPWRDNZ0
);
212 #ifdef CONFIG_TARGET_OMAP3_CAIRO
213 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
214 pbias_lite
&= ~PBIASLITEVMODE0
;
216 #ifdef CONFIG_MMC_OMAP36XX_PINS
217 if (get_cpu_family() == CPU_OMAP36XX
) {
218 /* Disable extended drain IO before changing PBIAS */
219 wkup_ctrl
&= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ
;
220 writel(wkup_ctrl
, OMAP34XX_CTRL_WKUP_CTRL
);
223 writel(pbias_lite
, &t2_base
->pbias_lite
);
225 writel(pbias_lite
| PBIASLITEPWRDNZ1
|
226 PBIASSPEEDCTRL0
| PBIASLITEPWRDNZ0
,
227 &t2_base
->pbias_lite
);
229 #ifdef CONFIG_MMC_OMAP36XX_PINS
230 if (get_cpu_family() == CPU_OMAP36XX
)
231 /* Enable extended drain IO after changing PBIAS */
233 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ
,
234 OMAP34XX_CTRL_WKUP_CTRL
);
236 writel(readl(&t2_base
->devconf0
) | MMCSDIO1ADPCLKISEL
,
239 writel(readl(&t2_base
->devconf1
) | MMCSDIO2ADPCLKISEL
,
242 /* Change from default of 52MHz to 26MHz if necessary */
243 if (!(cfg
->host_caps
& MMC_MODE_HS_52MHz
))
244 writel(readl(&t2_base
->ctl_prog_io1
) & ~CTLPROGIO1SPEEDCTRL
,
245 &t2_base
->ctl_prog_io1
);
247 writel(readl(&prcm_base
->fclken1_core
) |
248 EN_MMC1
| EN_MMC2
| EN_MMC3
,
249 &prcm_base
->fclken1_core
);
251 writel(readl(&prcm_base
->iclken1_core
) |
252 EN_MMC1
| EN_MMC2
| EN_MMC3
,
253 &prcm_base
->iclken1_core
);
256 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
257 /* PBIAS config needed for MMC1 only */
258 if (mmc_get_blk_desc(mmc
)->devnum
== 0)
259 vmmc_pbias_config(LDO_VOLT_3V0
);
265 void mmc_init_stream(struct hsmmc
*mmc_base
)
269 writel(readl(&mmc_base
->con
) | INIT_INITSTREAM
, &mmc_base
->con
);
271 writel(MMC_CMD0
, &mmc_base
->cmd
);
272 start
= get_timer(0);
273 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
274 if (get_timer(0) - start
> MAX_RETRY_MS
) {
275 printf("%s: timedout waiting for cc!\n", __func__
);
279 writel(CC_MASK
, &mmc_base
->stat
)
281 writel(MMC_CMD0
, &mmc_base
->cmd
)
283 start
= get_timer(0);
284 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
285 if (get_timer(0) - start
> MAX_RETRY_MS
) {
286 printf("%s: timedout waiting for cc2!\n", __func__
);
290 writel(readl(&mmc_base
->con
) & ~INIT_INITSTREAM
, &mmc_base
->con
);
293 #if CONFIG_IS_ENABLED(DM_MMC)
294 #ifdef CONFIG_IODELAY_RECALIBRATION
295 static void omap_hsmmc_io_recalibrate(struct mmc
*mmc
)
297 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
298 struct omap_hsmmc_pinctrl_state
*pinctrl_state
;
300 switch (priv
->mode
) {
302 pinctrl_state
= priv
->hs200_1_8v_pinctrl_state
;
305 pinctrl_state
= priv
->sdr104_pinctrl_state
;
308 pinctrl_state
= priv
->sdr50_pinctrl_state
;
311 pinctrl_state
= priv
->ddr50_pinctrl_state
;
314 pinctrl_state
= priv
->sdr25_pinctrl_state
;
317 pinctrl_state
= priv
->sdr12_pinctrl_state
;
322 pinctrl_state
= priv
->hs_pinctrl_state
;
325 pinctrl_state
= priv
->ddr_1_8v_pinctrl_state
;
327 pinctrl_state
= priv
->default_pinctrl_state
;
331 if (priv
->controller_flags
& OMAP_HSMMC_REQUIRE_IODELAY
) {
332 if (pinctrl_state
->iodelay
)
333 late_recalibrate_iodelay(pinctrl_state
->padconf
,
334 pinctrl_state
->npads
,
335 pinctrl_state
->iodelay
,
336 pinctrl_state
->niodelays
);
338 do_set_mux32((*ctrl
)->control_padconf_core_base
,
339 pinctrl_state
->padconf
,
340 pinctrl_state
->npads
);
344 static void omap_hsmmc_set_timing(struct mmc
*mmc
)
347 struct hsmmc
*mmc_base
;
348 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
350 mmc_base
= priv
->base_addr
;
352 omap_hsmmc_stop_clock(mmc_base
);
353 val
= readl(&mmc_base
->ac12
);
354 val
&= ~AC12_UHSMC_MASK
;
355 priv
->mode
= mmc
->selected_mode
;
357 if (mmc_is_mode_ddr(priv
->mode
))
358 writel(readl(&mmc_base
->con
) | DDR
, &mmc_base
->con
);
360 writel(readl(&mmc_base
->con
) & ~DDR
, &mmc_base
->con
);
362 switch (priv
->mode
) {
365 val
|= AC12_UHSMC_SDR104
;
368 val
|= AC12_UHSMC_SDR50
;
372 val
|= AC12_UHSMC_DDR50
;
377 val
|= AC12_UHSMC_SDR25
;
383 val
|= AC12_UHSMC_SDR12
;
386 val
|= AC12_UHSMC_RES
;
389 writel(val
, &mmc_base
->ac12
);
391 #ifdef CONFIG_IODELAY_RECALIBRATION
392 omap_hsmmc_io_recalibrate(mmc
);
394 omap_hsmmc_start_clock(mmc_base
);
397 static void omap_hsmmc_conf_bus_power(struct mmc
*mmc
)
399 struct hsmmc
*mmc_base
;
400 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
403 mmc_base
= priv
->base_addr
;
405 val
= readl(&mmc_base
->hctl
) & ~SDVS_MASK
;
419 writel(val
, &mmc_base
->hctl
);
422 static void omap_hsmmc_set_capabilities(struct mmc
*mmc
)
424 struct hsmmc
*mmc_base
;
425 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
428 mmc_base
= priv
->base_addr
;
429 val
= readl(&mmc_base
->capa
);
431 if (priv
->controller_flags
& OMAP_HSMMC_SUPPORTS_DUAL_VOLT
) {
432 val
|= (VS30_3V0SUP
| VS18_1V8SUP
);
434 } else if (priv
->controller_flags
& OMAP_HSMMC_NO_1_8_V
) {
444 writel(val
, &mmc_base
->capa
);
447 #ifdef MMC_SUPPORTS_TUNING
448 static void omap_hsmmc_disable_tuning(struct mmc
*mmc
)
450 struct hsmmc
*mmc_base
;
451 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
454 mmc_base
= priv
->base_addr
;
455 val
= readl(&mmc_base
->ac12
);
456 val
&= ~(AC12_SCLK_SEL
);
457 writel(val
, &mmc_base
->ac12
);
459 val
= readl(&mmc_base
->dll
);
460 val
&= ~(DLL_FORCE_VALUE
| DLL_SWT
);
461 writel(val
, &mmc_base
->dll
);
464 static void omap_hsmmc_set_dll(struct mmc
*mmc
, int count
)
467 struct hsmmc
*mmc_base
;
468 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
471 mmc_base
= priv
->base_addr
;
472 val
= readl(&mmc_base
->dll
);
473 val
|= DLL_FORCE_VALUE
;
474 val
&= ~(DLL_FORCE_SR_C_MASK
<< DLL_FORCE_SR_C_SHIFT
);
475 val
|= (count
<< DLL_FORCE_SR_C_SHIFT
);
476 writel(val
, &mmc_base
->dll
);
479 writel(val
, &mmc_base
->dll
);
480 for (i
= 0; i
< 1000; i
++) {
481 if (readl(&mmc_base
->dll
) & DLL_CALIB
)
485 writel(val
, &mmc_base
->dll
);
488 static int omap_hsmmc_execute_tuning(struct udevice
*dev
, uint opcode
)
490 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
491 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
492 struct mmc
*mmc
= upriv
->mmc
;
493 struct hsmmc
*mmc_base
;
495 u8 cur_match
, prev_match
= 0;
498 u32 start_window
= 0, max_window
= 0;
499 u32 length
= 0, max_len
= 0;
501 mmc_base
= priv
->base_addr
;
502 val
= readl(&mmc_base
->capa2
);
504 /* clock tuning is not needed for upto 52MHz */
505 if (!((mmc
->selected_mode
== MMC_HS_200
) ||
506 (mmc
->selected_mode
== UHS_SDR104
) ||
507 ((mmc
->selected_mode
== UHS_SDR50
) && (val
& CAPA2_TSDR50
))))
510 val
= readl(&mmc_base
->dll
);
512 writel(val
, &mmc_base
->dll
);
513 while (phase_delay
<= MAX_PHASE_DELAY
) {
514 omap_hsmmc_set_dll(mmc
, phase_delay
);
516 cur_match
= !mmc_send_tuning(mmc
, opcode
, NULL
);
522 start_window
= phase_delay
;
527 if (length
> max_len
) {
528 max_window
= start_window
;
532 prev_match
= cur_match
;
541 val
= readl(&mmc_base
->ac12
);
542 if (!(val
& AC12_SCLK_SEL
)) {
547 phase_delay
= max_window
+ 4 * ((3 * max_len
) >> 2);
548 omap_hsmmc_set_dll(mmc
, phase_delay
);
550 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
551 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRC
);
557 omap_hsmmc_disable_tuning(mmc
);
558 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
559 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRC
);
566 static void mmc_enable_irq(struct mmc
*mmc
, struct mmc_cmd
*cmd
)
568 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
569 struct hsmmc
*mmc_base
= priv
->base_addr
;
570 u32 irq_mask
= INT_EN_MASK
;
573 * TODO: Errata i802 indicates only DCRC interrupts can occur during
574 * tuning procedure and DCRC should be disabled. But see occurences
575 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
576 * interrupts occur along with BRR, so the data is actually in the
577 * buffer. It has to be debugged why these interrutps occur
579 if (cmd
&& mmc_is_tuning_cmd(cmd
->cmdidx
))
580 irq_mask
&= ~(IE_DEB
| IE_DCRC
| IE_CIE
| IE_CEB
| IE_CCRC
);
582 writel(irq_mask
, &mmc_base
->ie
);
585 static int omap_hsmmc_init_setup(struct mmc
*mmc
)
587 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
588 struct hsmmc
*mmc_base
;
589 unsigned int reg_val
;
593 mmc_base
= priv
->base_addr
;
596 writel(readl(&mmc_base
->sysconfig
) | MMC_SOFTRESET
,
597 &mmc_base
->sysconfig
);
598 start
= get_timer(0);
599 while ((readl(&mmc_base
->sysstatus
) & RESETDONE
) == 0) {
600 if (get_timer(0) - start
> MAX_RETRY_MS
) {
601 printf("%s: timedout waiting for cc2!\n", __func__
);
605 writel(readl(&mmc_base
->sysctl
) | SOFTRESETALL
, &mmc_base
->sysctl
);
606 start
= get_timer(0);
607 while ((readl(&mmc_base
->sysctl
) & SOFTRESETALL
) != 0x0) {
608 if (get_timer(0) - start
> MAX_RETRY_MS
) {
609 printf("%s: timedout waiting for softresetall!\n",
614 #ifndef CONFIG_OMAP34XX
615 reg_val
= readl(&mmc_base
->hl_hwinfo
);
616 if (reg_val
& MADMA_EN
)
617 priv
->controller_flags
|= OMAP_HSMMC_USE_ADMA
;
620 #if CONFIG_IS_ENABLED(DM_MMC)
621 omap_hsmmc_set_capabilities(mmc
);
622 omap_hsmmc_conf_bus_power(mmc
);
624 writel(DTW_1_BITMODE
| SDBP_PWROFF
| SDVS_3V0
, &mmc_base
->hctl
);
625 writel(readl(&mmc_base
->capa
) | VS30_3V0SUP
| VS18_1V8SUP
,
629 reg_val
= readl(&mmc_base
->con
) & RESERVED_MASK
;
631 writel(CTPL_MMC_SD
| reg_val
| WPP_ACTIVEHIGH
| CDP_ACTIVEHIGH
|
632 MIT_CTO
| DW8_1_4BITMODE
| MODE_FUNC
| STR_BLOCK
|
633 HR_NOHOSTRESP
| INIT_NOINIT
| NOOPENDRAIN
, &mmc_base
->con
);
636 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
637 (ICE_STOP
| DTO_15THDTO
));
638 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
639 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
640 start
= get_timer(0);
641 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
642 if (get_timer(0) - start
> MAX_RETRY_MS
) {
643 printf("%s: timedout waiting for ics!\n", __func__
);
647 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
649 writel(readl(&mmc_base
->hctl
) | SDBP_PWRON
, &mmc_base
->hctl
);
651 mmc_enable_irq(mmc
, NULL
);
652 mmc_init_stream(mmc_base
);
658 * MMC controller internal finite state machine reset
660 * Used to reset command or data internal state machines, using respectively
661 * SRC or SRD bit of SYSCTL register
663 static void mmc_reset_controller_fsm(struct hsmmc
*mmc_base
, u32 bit
)
667 mmc_reg_out(&mmc_base
->sysctl
, bit
, bit
);
670 * CMD(DAT) lines reset procedures are slightly different
671 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
672 * According to OMAP3 TRM:
673 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
675 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
676 * procedure steps must be as follows:
677 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
678 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
679 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
680 * 3. Wait until the SRC (SRD) bit returns to 0x0
681 * (reset procedure is completed).
683 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
684 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
685 if (!(readl(&mmc_base
->sysctl
) & bit
)) {
686 start
= get_timer(0);
687 while (!(readl(&mmc_base
->sysctl
) & bit
)) {
688 if (get_timer(0) - start
> MMC_TIMEOUT_MS
)
693 start
= get_timer(0);
694 while ((readl(&mmc_base
->sysctl
) & bit
) != 0) {
695 if (get_timer(0) - start
> MAX_RETRY_MS
) {
696 printf("%s: timedout waiting for sysctl %x to clear\n",
703 #ifndef CONFIG_OMAP34XX
704 static void omap_hsmmc_adma_desc(struct mmc
*mmc
, char *buf
, u16 len
, bool end
)
706 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
707 struct omap_hsmmc_adma_desc
*desc
;
710 desc
= &priv
->adma_desc_table
[priv
->desc_slot
];
712 attr
= ADMA_DESC_ATTR_VALID
| ADMA_DESC_TRANSFER_DATA
;
716 attr
|= ADMA_DESC_ATTR_END
;
719 desc
->addr
= (u32
)buf
;
724 static void omap_hsmmc_prepare_adma_table(struct mmc
*mmc
,
725 struct mmc_data
*data
)
727 uint total_len
= data
->blocksize
* data
->blocks
;
728 uint desc_count
= DIV_ROUND_UP(total_len
, ADMA_MAX_LEN
);
729 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
734 priv
->adma_desc_table
= (struct omap_hsmmc_adma_desc
*)
735 memalign(ARCH_DMA_MINALIGN
, desc_count
*
736 sizeof(struct omap_hsmmc_adma_desc
));
738 if (data
->flags
& MMC_DATA_READ
)
741 buf
= (char *)data
->src
;
744 omap_hsmmc_adma_desc(mmc
, buf
, ADMA_MAX_LEN
, false);
746 total_len
-= ADMA_MAX_LEN
;
749 omap_hsmmc_adma_desc(mmc
, buf
, total_len
, true);
751 flush_dcache_range((long)priv
->adma_desc_table
,
752 (long)priv
->adma_desc_table
+
754 sizeof(struct omap_hsmmc_adma_desc
),
758 static void omap_hsmmc_prepare_data(struct mmc
*mmc
, struct mmc_data
*data
)
760 struct hsmmc
*mmc_base
;
761 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
765 mmc_base
= priv
->base_addr
;
766 omap_hsmmc_prepare_adma_table(mmc
, data
);
768 if (data
->flags
& MMC_DATA_READ
)
771 buf
= (char *)data
->src
;
773 val
= readl(&mmc_base
->hctl
);
775 writel(val
, &mmc_base
->hctl
);
777 val
= readl(&mmc_base
->con
);
779 writel(val
, &mmc_base
->con
);
781 writel((u32
)priv
->adma_desc_table
, &mmc_base
->admasal
);
783 flush_dcache_range((u32
)buf
,
785 ROUND(data
->blocksize
* data
->blocks
,
789 static void omap_hsmmc_dma_cleanup(struct mmc
*mmc
)
791 struct hsmmc
*mmc_base
;
792 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
795 mmc_base
= priv
->base_addr
;
797 val
= readl(&mmc_base
->con
);
799 writel(val
, &mmc_base
->con
);
801 val
= readl(&mmc_base
->hctl
);
803 writel(val
, &mmc_base
->hctl
);
805 kfree(priv
->adma_desc_table
);
808 #define omap_hsmmc_adma_desc
809 #define omap_hsmmc_prepare_adma_table
810 #define omap_hsmmc_prepare_data
811 #define omap_hsmmc_dma_cleanup
814 #if !CONFIG_IS_ENABLED(DM_MMC)
815 static int omap_hsmmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
816 struct mmc_data
*data
)
818 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
820 static int omap_hsmmc_send_cmd(struct udevice
*dev
, struct mmc_cmd
*cmd
,
821 struct mmc_data
*data
)
823 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
824 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
825 struct mmc
*mmc
= upriv
->mmc
;
827 struct hsmmc
*mmc_base
;
828 unsigned int flags
, mmc_stat
;
831 mmc_base
= priv
->base_addr
;
833 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
836 start
= get_timer(0);
837 while ((readl(&mmc_base
->pstate
) & (DATI_MASK
| CMDI_MASK
)) != 0) {
838 if (get_timer(0) - start
> MAX_RETRY_MS
) {
839 printf("%s: timedout waiting on cmd inhibit to clear\n",
844 writel(0xFFFFFFFF, &mmc_base
->stat
);
845 start
= get_timer(0);
846 while (readl(&mmc_base
->stat
)) {
847 if (get_timer(0) - start
> MAX_RETRY_MS
) {
848 printf("%s: timedout waiting for STAT (%x) to clear\n",
849 __func__
, readl(&mmc_base
->stat
));
855 * CMDIDX[13:8] : Command index
856 * DATAPRNT[5] : Data Present Select
857 * ENCMDIDX[4] : Command Index Check Enable
858 * ENCMDCRC[3] : Command CRC Check Enable
863 * 11 = Length 48 Check busy after response
865 /* Delay added before checking the status of frq change
866 * retry not supported by mmc.c(core file)
868 if (cmd
->cmdidx
== SD_CMD_APP_SEND_SCR
)
869 udelay(50000); /* wait 50 ms */
871 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
873 else if (cmd
->resp_type
& MMC_RSP_136
)
874 flags
= RSP_TYPE_LGHT136
| CICE_NOCHECK
;
875 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
876 flags
= RSP_TYPE_LGHT48B
;
878 flags
= RSP_TYPE_LGHT48
;
880 /* enable default flags */
881 flags
= flags
| (CMD_TYPE_NORMAL
| CICE_NOCHECK
| CCCE_NOCHECK
|
883 flags
&= ~(ACEN_ENABLE
| BCE_ENABLE
| DE_ENABLE
);
885 if (cmd
->resp_type
& MMC_RSP_CRC
)
887 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
891 if ((cmd
->cmdidx
== MMC_CMD_READ_MULTIPLE_BLOCK
) ||
892 (cmd
->cmdidx
== MMC_CMD_WRITE_MULTIPLE_BLOCK
)) {
893 flags
|= (MSBS_MULTIBLK
| BCE_ENABLE
| ACEN_ENABLE
);
894 data
->blocksize
= 512;
895 writel(data
->blocksize
| (data
->blocks
<< 16),
898 writel(data
->blocksize
| NBLK_STPCNT
, &mmc_base
->blk
);
900 if (data
->flags
& MMC_DATA_READ
)
901 flags
|= (DP_DATA
| DDIR_READ
);
903 flags
|= (DP_DATA
| DDIR_WRITE
);
905 #ifndef CONFIG_OMAP34XX
906 if ((priv
->controller_flags
& OMAP_HSMMC_USE_ADMA
) &&
907 !mmc_is_tuning_cmd(cmd
->cmdidx
)) {
908 omap_hsmmc_prepare_data(mmc
, data
);
914 mmc_enable_irq(mmc
, cmd
);
916 writel(cmd
->cmdarg
, &mmc_base
->arg
);
917 udelay(20); /* To fix "No status update" error on eMMC */
918 writel((cmd
->cmdidx
<< 24) | flags
, &mmc_base
->cmd
);
920 start
= get_timer(0);
922 mmc_stat
= readl(&mmc_base
->stat
);
923 if (get_timer(start
) > MAX_RETRY_MS
) {
924 printf("%s : timeout: No status update\n", __func__
);
929 if ((mmc_stat
& IE_CTO
) != 0) {
930 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRC
);
932 } else if ((mmc_stat
& ERRI_MASK
) != 0)
935 if (mmc_stat
& CC_MASK
) {
936 writel(CC_MASK
, &mmc_base
->stat
);
937 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
938 if (cmd
->resp_type
& MMC_RSP_136
) {
939 /* response type 2 */
940 cmd
->response
[3] = readl(&mmc_base
->rsp10
);
941 cmd
->response
[2] = readl(&mmc_base
->rsp32
);
942 cmd
->response
[1] = readl(&mmc_base
->rsp54
);
943 cmd
->response
[0] = readl(&mmc_base
->rsp76
);
945 /* response types 1, 1b, 3, 4, 5, 6 */
946 cmd
->response
[0] = readl(&mmc_base
->rsp10
);
950 #ifndef CONFIG_OMAP34XX
951 if ((priv
->controller_flags
& OMAP_HSMMC_USE_ADMA
) && data
&&
952 !mmc_is_tuning_cmd(cmd
->cmdidx
)) {
955 if (mmc_stat
& IE_ADMAE
) {
956 omap_hsmmc_dma_cleanup(mmc
);
960 sz_mb
= DIV_ROUND_UP(data
->blocksize
* data
->blocks
, 1 << 20);
961 timeout
= sz_mb
* DMA_TIMEOUT_PER_MB
;
962 if (timeout
< MAX_RETRY_MS
)
963 timeout
= MAX_RETRY_MS
;
965 start
= get_timer(0);
967 mmc_stat
= readl(&mmc_base
->stat
);
968 if (mmc_stat
& TC_MASK
) {
969 writel(readl(&mmc_base
->stat
) | TC_MASK
,
973 if (get_timer(start
) > timeout
) {
974 printf("%s : DMA timeout: No status update\n",
980 omap_hsmmc_dma_cleanup(mmc
);
985 if (data
&& (data
->flags
& MMC_DATA_READ
)) {
986 mmc_read_data(mmc_base
, data
->dest
,
987 data
->blocksize
* data
->blocks
);
988 } else if (data
&& (data
->flags
& MMC_DATA_WRITE
)) {
989 mmc_write_data(mmc_base
, data
->src
,
990 data
->blocksize
* data
->blocks
);
995 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
)
997 unsigned int *output_buf
= (unsigned int *)buf
;
998 unsigned int mmc_stat
;
1004 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
1008 ulong start
= get_timer(0);
1010 mmc_stat
= readl(&mmc_base
->stat
);
1011 if (get_timer(0) - start
> MAX_RETRY_MS
) {
1012 printf("%s: timedout waiting for status!\n",
1016 } while (mmc_stat
== 0);
1018 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
1019 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
1021 if ((mmc_stat
& ERRI_MASK
) != 0)
1024 if (mmc_stat
& BRR_MASK
) {
1027 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
1029 for (k
= 0; k
< count
; k
++) {
1030 *output_buf
= readl(&mmc_base
->data
);
1036 if (mmc_stat
& BWR_MASK
)
1037 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
1040 if (mmc_stat
& TC_MASK
) {
1041 writel(readl(&mmc_base
->stat
) | TC_MASK
,
1049 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
1052 unsigned int *input_buf
= (unsigned int *)buf
;
1053 unsigned int mmc_stat
;
1057 * Start Polled Write
1059 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
1063 ulong start
= get_timer(0);
1065 mmc_stat
= readl(&mmc_base
->stat
);
1066 if (get_timer(0) - start
> MAX_RETRY_MS
) {
1067 printf("%s: timedout waiting for status!\n",
1071 } while (mmc_stat
== 0);
1073 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
1074 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
1076 if ((mmc_stat
& ERRI_MASK
) != 0)
1079 if (mmc_stat
& BWR_MASK
) {
1082 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
1084 for (k
= 0; k
< count
; k
++) {
1085 writel(*input_buf
, &mmc_base
->data
);
1091 if (mmc_stat
& BRR_MASK
)
1092 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
1095 if (mmc_stat
& TC_MASK
) {
1096 writel(readl(&mmc_base
->stat
) | TC_MASK
,
1104 static void omap_hsmmc_stop_clock(struct hsmmc
*mmc_base
)
1106 writel(readl(&mmc_base
->sysctl
) & ~CEN_ENABLE
, &mmc_base
->sysctl
);
1109 static void omap_hsmmc_start_clock(struct hsmmc
*mmc_base
)
1111 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
1114 static void omap_hsmmc_set_clock(struct mmc
*mmc
)
1116 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
1117 struct hsmmc
*mmc_base
;
1118 unsigned int dsor
= 0;
1121 mmc_base
= priv
->base_addr
;
1122 omap_hsmmc_stop_clock(mmc_base
);
1124 /* TODO: Is setting DTO required here? */
1125 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
),
1126 (ICE_STOP
| DTO_15THDTO
));
1128 if (mmc
->clock
!= 0) {
1129 dsor
= DIV_ROUND_UP(MMC_CLOCK_REFERENCE
* 1000000, mmc
->clock
);
1130 if (dsor
> CLKD_MAX
)
1136 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
1137 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
1139 start
= get_timer(0);
1140 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
1141 if (get_timer(0) - start
> MAX_RETRY_MS
) {
1142 printf("%s: timedout waiting for ics!\n", __func__
);
1147 priv
->clock
= mmc
->clock
;
1148 omap_hsmmc_start_clock(mmc_base
);
1151 static void omap_hsmmc_set_bus_width(struct mmc
*mmc
)
1153 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
1154 struct hsmmc
*mmc_base
;
1156 mmc_base
= priv
->base_addr
;
1157 /* configue bus width */
1158 switch (mmc
->bus_width
) {
1160 writel(readl(&mmc_base
->con
) | DTW_8_BITMODE
,
1165 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
1167 writel(readl(&mmc_base
->hctl
) | DTW_4_BITMODE
,
1173 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
1175 writel(readl(&mmc_base
->hctl
) & ~DTW_4_BITMODE
,
1180 priv
->bus_width
= mmc
->bus_width
;
1183 #if !CONFIG_IS_ENABLED(DM_MMC)
1184 static int omap_hsmmc_set_ios(struct mmc
*mmc
)
1186 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
1188 static int omap_hsmmc_set_ios(struct udevice
*dev
)
1190 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
1191 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
1192 struct mmc
*mmc
= upriv
->mmc
;
1195 if (priv
->bus_width
!= mmc
->bus_width
)
1196 omap_hsmmc_set_bus_width(mmc
);
1198 if (priv
->clock
!= mmc
->clock
)
1199 omap_hsmmc_set_clock(mmc
);
1201 #if CONFIG_IS_ENABLED(DM_MMC)
1202 if (priv
->mode
!= mmc
->selected_mode
)
1203 omap_hsmmc_set_timing(mmc
);
1208 #ifdef OMAP_HSMMC_USE_GPIO
1209 #if CONFIG_IS_ENABLED(DM_MMC)
1210 static int omap_hsmmc_getcd(struct udevice
*dev
)
1212 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
1215 value
= dm_gpio_get_value(&priv
->cd_gpio
);
1216 /* if no CD return as 1 */
1220 if (priv
->cd_inverted
)
1225 static int omap_hsmmc_getwp(struct udevice
*dev
)
1227 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
1230 value
= dm_gpio_get_value(&priv
->wp_gpio
);
1231 /* if no WP return as 0 */
1237 static int omap_hsmmc_getcd(struct mmc
*mmc
)
1239 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
1242 /* if no CD return as 1 */
1243 cd_gpio
= priv
->cd_gpio
;
1247 /* NOTE: assumes card detect signal is active-low */
1248 return !gpio_get_value(cd_gpio
);
1251 static int omap_hsmmc_getwp(struct mmc
*mmc
)
1253 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
1256 /* if no WP return as 0 */
1257 wp_gpio
= priv
->wp_gpio
;
1261 /* NOTE: assumes write protect signal is active-high */
1262 return gpio_get_value(wp_gpio
);
1267 #if CONFIG_IS_ENABLED(DM_MMC)
1268 static const struct dm_mmc_ops omap_hsmmc_ops
= {
1269 .send_cmd
= omap_hsmmc_send_cmd
,
1270 .set_ios
= omap_hsmmc_set_ios
,
1271 #ifdef OMAP_HSMMC_USE_GPIO
1272 .get_cd
= omap_hsmmc_getcd
,
1273 .get_wp
= omap_hsmmc_getwp
,
1275 #ifdef MMC_SUPPORTS_TUNING
1276 .execute_tuning
= omap_hsmmc_execute_tuning
,
1280 static const struct mmc_ops omap_hsmmc_ops
= {
1281 .send_cmd
= omap_hsmmc_send_cmd
,
1282 .set_ios
= omap_hsmmc_set_ios
,
1283 .init
= omap_hsmmc_init_setup
,
1284 #ifdef OMAP_HSMMC_USE_GPIO
1285 .getcd
= omap_hsmmc_getcd
,
1286 .getwp
= omap_hsmmc_getwp
,
1291 #if !CONFIG_IS_ENABLED(DM_MMC)
1292 int omap_mmc_init(int dev_index
, uint host_caps_mask
, uint f_max
, int cd_gpio
,
1296 struct omap_hsmmc_data
*priv
;
1297 struct mmc_config
*cfg
;
1300 priv
= malloc(sizeof(*priv
));
1304 host_caps_val
= MMC_MODE_4BIT
| MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
1306 switch (dev_index
) {
1308 priv
->base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
1310 #ifdef OMAP_HSMMC2_BASE
1312 priv
->base_addr
= (struct hsmmc
*)OMAP_HSMMC2_BASE
;
1313 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1314 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1315 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1316 defined(CONFIG_HSMMC2_8BIT)
1317 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1318 host_caps_val
|= MMC_MODE_8BIT
;
1322 #ifdef OMAP_HSMMC3_BASE
1324 priv
->base_addr
= (struct hsmmc
*)OMAP_HSMMC3_BASE
;
1325 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1326 /* Enable 8-bit interface for eMMC on DRA7XX */
1327 host_caps_val
|= MMC_MODE_8BIT
;
1332 priv
->base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
1335 #ifdef OMAP_HSMMC_USE_GPIO
1336 /* on error gpio values are set to -1, which is what we want */
1337 priv
->cd_gpio
= omap_mmc_setup_gpio_in(cd_gpio
, "mmc_cd");
1338 priv
->wp_gpio
= omap_mmc_setup_gpio_in(wp_gpio
, "mmc_wp");
1343 cfg
->name
= "OMAP SD/MMC";
1344 cfg
->ops
= &omap_hsmmc_ops
;
1346 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
1347 cfg
->host_caps
= host_caps_val
& ~host_caps_mask
;
1349 cfg
->f_min
= 400000;
1354 if (cfg
->host_caps
& MMC_MODE_HS
) {
1355 if (cfg
->host_caps
& MMC_MODE_HS_52MHz
)
1356 cfg
->f_max
= 52000000;
1358 cfg
->f_max
= 26000000;
1360 cfg
->f_max
= 20000000;
1363 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
1365 #if defined(CONFIG_OMAP34XX)
1367 * Silicon revs 2.1 and older do not support multiblock transfers.
1369 if ((get_cpu_family() == CPU_OMAP34XX
) && (get_cpu_rev() <= CPU_3XX_ES21
))
1373 mmc
= mmc_create(cfg
, priv
);
1381 #ifdef CONFIG_IODELAY_RECALIBRATION
1382 static struct pad_conf_entry
*
1383 omap_hsmmc_get_pad_conf_entry(const fdt32_t
*pinctrl
, int count
)
1386 struct pad_conf_entry
*padconf
;
1388 padconf
= (struct pad_conf_entry
*)malloc(sizeof(*padconf
) * count
);
1390 debug("failed to allocate memory\n");
1394 while (index
< count
) {
1395 padconf
[index
].offset
= fdt32_to_cpu(pinctrl
[2 * index
]);
1396 padconf
[index
].val
= fdt32_to_cpu(pinctrl
[2 * index
+ 1]);
1403 static struct iodelay_cfg_entry
*
1404 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t
*pinctrl
, int count
)
1407 struct iodelay_cfg_entry
*iodelay
;
1409 iodelay
= (struct iodelay_cfg_entry
*)malloc(sizeof(*iodelay
) * count
);
1411 debug("failed to allocate memory\n");
1415 while (index
< count
) {
1416 iodelay
[index
].offset
= fdt32_to_cpu(pinctrl
[3 * index
]);
1417 iodelay
[index
].a_delay
= fdt32_to_cpu(pinctrl
[3 * index
+ 1]);
1418 iodelay
[index
].g_delay
= fdt32_to_cpu(pinctrl
[3 * index
+ 2]);
1425 static const fdt32_t
*omap_hsmmc_get_pinctrl_entry(u32 phandle
,
1426 const char *name
, int *len
)
1428 const void *fdt
= gd
->fdt_blob
;
1430 const fdt32_t
*pinctrl
;
1432 offset
= fdt_node_offset_by_phandle(fdt
, phandle
);
1434 debug("failed to get pinctrl node %s.\n",
1435 fdt_strerror(offset
));
1439 pinctrl
= fdt_getprop(fdt
, offset
, name
, len
);
1441 debug("failed to get property %s\n", name
);
1448 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc
*mmc
,
1451 const void *fdt
= gd
->fdt_blob
;
1452 const __be32
*phandle
;
1453 int node
= dev_of_offset(mmc
->dev
);
1455 phandle
= fdt_getprop(fdt
, node
, prop_name
, NULL
);
1457 debug("failed to get property %s\n", prop_name
);
1461 return fdt32_to_cpu(*phandle
);
1464 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc
*mmc
,
1467 const void *fdt
= gd
->fdt_blob
;
1468 const __be32
*phandle
;
1471 int node
= dev_of_offset(mmc
->dev
);
1473 phandle
= fdt_getprop(fdt
, node
, prop_name
, &len
);
1475 debug("failed to get property %s\n", prop_name
);
1479 /* No manual mode iodelay values if count < 2 */
1480 count
= len
/ sizeof(*phandle
);
1484 return fdt32_to_cpu(*(phandle
+ 1));
1487 static struct pad_conf_entry
*
1488 omap_hsmmc_get_pad_conf(struct mmc
*mmc
, char *prop_name
, int *npads
)
1492 struct pad_conf_entry
*padconf
;
1494 const fdt32_t
*pinctrl
;
1496 phandle
= omap_hsmmc_get_pad_conf_phandle(mmc
, prop_name
);
1498 return ERR_PTR(-EINVAL
);
1500 pinctrl
= omap_hsmmc_get_pinctrl_entry(phandle
, "pinctrl-single,pins",
1503 return ERR_PTR(-EINVAL
);
1505 count
= (len
/ sizeof(*pinctrl
)) / 2;
1506 padconf
= omap_hsmmc_get_pad_conf_entry(pinctrl
, count
);
1508 return ERR_PTR(-EINVAL
);
1515 static struct iodelay_cfg_entry
*
1516 omap_hsmmc_get_iodelay(struct mmc
*mmc
, char *prop_name
, int *niodelay
)
1520 struct iodelay_cfg_entry
*iodelay
;
1522 const fdt32_t
*pinctrl
;
1524 phandle
= omap_hsmmc_get_iodelay_phandle(mmc
, prop_name
);
1525 /* Not all modes have manual mode iodelay values. So its not fatal */
1529 pinctrl
= omap_hsmmc_get_pinctrl_entry(phandle
, "pinctrl-pin-array",
1532 return ERR_PTR(-EINVAL
);
1534 count
= (len
/ sizeof(*pinctrl
)) / 3;
1535 iodelay
= omap_hsmmc_get_iodelay_cfg_entry(pinctrl
, count
);
1537 return ERR_PTR(-EINVAL
);
1544 static struct omap_hsmmc_pinctrl_state
*
1545 omap_hsmmc_get_pinctrl_by_mode(struct mmc
*mmc
, char *mode
)
1550 const void *fdt
= gd
->fdt_blob
;
1551 int node
= dev_of_offset(mmc
->dev
);
1553 struct omap_hsmmc_pinctrl_state
*pinctrl_state
;
1555 pinctrl_state
= (struct omap_hsmmc_pinctrl_state
*)
1556 malloc(sizeof(*pinctrl_state
));
1557 if (!pinctrl_state
) {
1558 debug("failed to allocate memory\n");
1562 index
= fdt_stringlist_search(fdt
, node
, "pinctrl-names", mode
);
1564 debug("fail to find %s mode %s\n", mode
, fdt_strerror(index
));
1565 goto err_pinctrl_state
;
1568 sprintf(prop_name
, "pinctrl-%d", index
);
1570 pinctrl_state
->padconf
= omap_hsmmc_get_pad_conf(mmc
, prop_name
,
1572 if (IS_ERR(pinctrl_state
->padconf
))
1573 goto err_pinctrl_state
;
1574 pinctrl_state
->npads
= npads
;
1576 pinctrl_state
->iodelay
= omap_hsmmc_get_iodelay(mmc
, prop_name
,
1578 if (IS_ERR(pinctrl_state
->iodelay
))
1580 pinctrl_state
->niodelays
= niodelays
;
1582 return pinctrl_state
;
1585 kfree(pinctrl_state
->padconf
);
1588 kfree(pinctrl_state
);
1592 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode) \
1594 struct omap_hsmmc_pinctrl_state *s = NULL; \
1596 if (!(cfg->host_caps & capmask)) \
1599 if (priv->hw_rev) { \
1600 sprintf(str, "%s-%s", #mode, priv->hw_rev); \
1601 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
1605 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1608 debug("%s: no pinctrl for %s\n", \
1609 mmc->dev->name, #mode); \
1610 cfg->host_caps &= ~(capmask); \
1612 priv->mode##_pinctrl_state = s; \
1616 static int omap_hsmmc_get_pinctrl_state(struct mmc
*mmc
)
1618 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
1619 struct mmc_config
*cfg
= omap_hsmmc_get_cfg(mmc
);
1620 struct omap_hsmmc_pinctrl_state
*default_pinctrl
;
1622 if (!(priv
->controller_flags
& OMAP_HSMMC_REQUIRE_IODELAY
))
1625 default_pinctrl
= omap_hsmmc_get_pinctrl_by_mode(mmc
, "default");
1626 if (!default_pinctrl
) {
1627 printf("no pinctrl state for default mode\n");
1631 priv
->default_pinctrl_state
= default_pinctrl
;
1633 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104
), sdr104
);
1634 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50
), sdr50
);
1635 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50
), ddr50
);
1636 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25
), sdr25
);
1637 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12
), sdr12
);
1639 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200
), hs200_1_8v
);
1640 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52
), ddr_1_8v
);
1641 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS
, hs
);
1647 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1648 #ifdef CONFIG_OMAP54XX
1649 __weak
const struct mmc_platform_fixups
*platform_fixups_mmc(uint32_t addr
)
1655 static int omap_hsmmc_ofdata_to_platdata(struct udevice
*dev
)
1657 struct omap_hsmmc_plat
*plat
= dev_get_platdata(dev
);
1658 struct omap_mmc_of_data
*of_data
= (void *)dev_get_driver_data(dev
);
1660 struct mmc_config
*cfg
= &plat
->cfg
;
1661 #ifdef CONFIG_OMAP54XX
1662 const struct mmc_platform_fixups
*fixups
;
1664 const void *fdt
= gd
->fdt_blob
;
1665 int node
= dev_of_offset(dev
);
1668 plat
->base_addr
= map_physmem(devfdt_get_addr(dev
),
1669 sizeof(struct hsmmc
*),
1672 ret
= mmc_of_parse(dev
, cfg
);
1676 cfg
->host_caps
|= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
1677 cfg
->f_min
= 400000;
1678 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
1679 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
1680 if (fdtdec_get_bool(fdt
, node
, "ti,dual-volt"))
1681 plat
->controller_flags
|= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
;
1682 if (fdtdec_get_bool(fdt
, node
, "no-1-8-v"))
1683 plat
->controller_flags
|= OMAP_HSMMC_NO_1_8_V
;
1685 plat
->controller_flags
|= of_data
->controller_flags
;
1687 #ifdef CONFIG_OMAP54XX
1688 fixups
= platform_fixups_mmc(devfdt_get_addr(dev
));
1690 plat
->hw_rev
= fixups
->hw_rev
;
1691 cfg
->host_caps
&= ~fixups
->unsupported_caps
;
1692 cfg
->f_max
= fixups
->max_freq
;
1696 #ifdef OMAP_HSMMC_USE_GPIO
1697 plat
->cd_inverted
= fdtdec_get_bool(fdt
, node
, "cd-inverted");
1706 static int omap_hsmmc_bind(struct udevice
*dev
)
1708 struct omap_hsmmc_plat
*plat
= dev_get_platdata(dev
);
1710 return mmc_bind(dev
, &plat
->mmc
, &plat
->cfg
);
1713 static int omap_hsmmc_probe(struct udevice
*dev
)
1715 struct omap_hsmmc_plat
*plat
= dev_get_platdata(dev
);
1716 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
1717 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
1718 struct mmc_config
*cfg
= &plat
->cfg
;
1720 #ifdef CONFIG_IODELAY_RECALIBRATION
1724 cfg
->name
= "OMAP SD/MMC";
1725 priv
->base_addr
= plat
->base_addr
;
1726 priv
->controller_flags
= plat
->controller_flags
;
1727 priv
->hw_rev
= plat
->hw_rev
;
1728 #ifdef OMAP_HSMMC_USE_GPIO
1729 priv
->cd_inverted
= plat
->cd_inverted
;
1735 mmc
= mmc_create(cfg
, priv
);
1740 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1741 gpio_request_by_name(dev
, "cd-gpios", 0, &priv
->cd_gpio
, GPIOD_IS_IN
);
1742 gpio_request_by_name(dev
, "wp-gpios", 0, &priv
->wp_gpio
, GPIOD_IS_IN
);
1748 #ifdef CONFIG_IODELAY_RECALIBRATION
1749 ret
= omap_hsmmc_get_pinctrl_state(mmc
);
1751 * disable high speed modes for the platforms that require IO delay
1752 * and for which we don't have this information
1755 (priv
->controller_flags
& OMAP_HSMMC_REQUIRE_IODELAY
)) {
1756 priv
->controller_flags
&= ~OMAP_HSMMC_REQUIRE_IODELAY
;
1757 cfg
->host_caps
&= ~(MMC_CAP(MMC_HS_200
) | MMC_CAP(MMC_DDR_52
) |
1762 return omap_hsmmc_init_setup(mmc
);
1765 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1767 static const struct omap_mmc_of_data dra7_mmc_of_data
= {
1768 .controller_flags
= OMAP_HSMMC_REQUIRE_IODELAY
,
1771 static const struct udevice_id omap_hsmmc_ids
[] = {
1772 { .compatible
= "ti,omap3-hsmmc" },
1773 { .compatible
= "ti,omap4-hsmmc" },
1774 { .compatible
= "ti,am33xx-hsmmc" },
1775 { .compatible
= "ti,dra7-hsmmc", .data
= (ulong
)&dra7_mmc_of_data
},
1780 U_BOOT_DRIVER(omap_hsmmc
) = {
1781 .name
= "omap_hsmmc",
1783 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1784 .of_match
= omap_hsmmc_ids
,
1785 .ofdata_to_platdata
= omap_hsmmc_ofdata_to_platdata
,
1786 .platdata_auto_alloc_size
= sizeof(struct omap_hsmmc_plat
),
1789 .bind
= omap_hsmmc_bind
,
1791 .ops
= &omap_hsmmc_ops
,
1792 .probe
= omap_hsmmc_probe
,
1793 .priv_auto_alloc_size
= sizeof(struct omap_hsmmc_data
),
1794 .flags
= DM_FLAG_PRE_RELOC
,