3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/arch/mmc_host_def.h>
36 #if !defined(CONFIG_SOC_KEYSTONE)
38 #include <asm/arch/sys_proto.h>
42 DECLARE_GLOBAL_DATA_PTR
;
44 /* simplify defines to OMAP_HSMMC_USE_GPIO */
45 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
46 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
47 #define OMAP_HSMMC_USE_GPIO
49 #undef OMAP_HSMMC_USE_GPIO
52 /* common definitions for all OMAPs */
53 #define SYSCTL_SRC (1 << 25)
54 #define SYSCTL_SRD (1 << 26)
56 struct omap_hsmmc_data
{
57 struct hsmmc
*base_addr
;
58 struct mmc_config cfg
;
59 #ifdef OMAP_HSMMC_USE_GPIO
61 struct gpio_desc cd_gpio
; /* Change Detect GPIO */
62 struct gpio_desc wp_gpio
; /* Write Protect GPIO */
71 /* If we fail after 1 second wait, something is really bad */
72 #define MAX_RETRY_MS 1000
74 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
);
75 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
78 #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
79 static int omap_mmc_setup_gpio_in(int gpio
, const char *label
)
83 #ifndef CONFIG_DM_GPIO
84 if (!gpio_is_valid(gpio
))
87 ret
= gpio_request(gpio
, label
);
91 ret
= gpio_direction_input(gpio
);
99 static unsigned char mmc_board_init(struct mmc
*mmc
)
101 #if defined(CONFIG_OMAP34XX)
102 t2_t
*t2_base
= (t2_t
*)T2_BASE
;
103 struct prcm
*prcm_base
= (struct prcm
*)PRCM_BASE
;
106 pbias_lite
= readl(&t2_base
->pbias_lite
);
107 pbias_lite
&= ~(PBIASLITEPWRDNZ1
| PBIASLITEPWRDNZ0
);
108 #ifdef CONFIG_TARGET_OMAP3_CAIRO
109 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
110 pbias_lite
&= ~PBIASLITEVMODE0
;
112 writel(pbias_lite
, &t2_base
->pbias_lite
);
114 writel(pbias_lite
| PBIASLITEPWRDNZ1
|
115 PBIASSPEEDCTRL0
| PBIASLITEPWRDNZ0
,
116 &t2_base
->pbias_lite
);
118 writel(readl(&t2_base
->devconf0
) | MMCSDIO1ADPCLKISEL
,
121 writel(readl(&t2_base
->devconf1
) | MMCSDIO2ADPCLKISEL
,
124 /* Change from default of 52MHz to 26MHz if necessary */
125 if (!(mmc
->cfg
->host_caps
& MMC_MODE_HS_52MHz
))
126 writel(readl(&t2_base
->ctl_prog_io1
) & ~CTLPROGIO1SPEEDCTRL
,
127 &t2_base
->ctl_prog_io1
);
129 writel(readl(&prcm_base
->fclken1_core
) |
130 EN_MMC1
| EN_MMC2
| EN_MMC3
,
131 &prcm_base
->fclken1_core
);
133 writel(readl(&prcm_base
->iclken1_core
) |
134 EN_MMC1
| EN_MMC2
| EN_MMC3
,
135 &prcm_base
->iclken1_core
);
138 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
139 /* PBIAS config needed for MMC1 only */
140 if (mmc
->block_dev
.devnum
== 0)
141 vmmc_pbias_config(LDO_VOLT_3V0
);
147 void mmc_init_stream(struct hsmmc
*mmc_base
)
151 writel(readl(&mmc_base
->con
) | INIT_INITSTREAM
, &mmc_base
->con
);
153 writel(MMC_CMD0
, &mmc_base
->cmd
);
154 start
= get_timer(0);
155 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
156 if (get_timer(0) - start
> MAX_RETRY_MS
) {
157 printf("%s: timedout waiting for cc!\n", __func__
);
161 writel(CC_MASK
, &mmc_base
->stat
)
163 writel(MMC_CMD0
, &mmc_base
->cmd
)
165 start
= get_timer(0);
166 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
167 if (get_timer(0) - start
> MAX_RETRY_MS
) {
168 printf("%s: timedout waiting for cc2!\n", __func__
);
172 writel(readl(&mmc_base
->con
) & ~INIT_INITSTREAM
, &mmc_base
->con
);
175 static int omap_hsmmc_init_setup(struct mmc
*mmc
)
177 struct hsmmc
*mmc_base
;
178 unsigned int reg_val
;
182 mmc_base
= ((struct omap_hsmmc_data
*)mmc
->priv
)->base_addr
;
185 writel(readl(&mmc_base
->sysconfig
) | MMC_SOFTRESET
,
186 &mmc_base
->sysconfig
);
187 start
= get_timer(0);
188 while ((readl(&mmc_base
->sysstatus
) & RESETDONE
) == 0) {
189 if (get_timer(0) - start
> MAX_RETRY_MS
) {
190 printf("%s: timedout waiting for cc2!\n", __func__
);
194 writel(readl(&mmc_base
->sysctl
) | SOFTRESETALL
, &mmc_base
->sysctl
);
195 start
= get_timer(0);
196 while ((readl(&mmc_base
->sysctl
) & SOFTRESETALL
) != 0x0) {
197 if (get_timer(0) - start
> MAX_RETRY_MS
) {
198 printf("%s: timedout waiting for softresetall!\n",
203 writel(DTW_1_BITMODE
| SDBP_PWROFF
| SDVS_3V0
, &mmc_base
->hctl
);
204 writel(readl(&mmc_base
->capa
) | VS30_3V0SUP
| VS18_1V8SUP
,
207 reg_val
= readl(&mmc_base
->con
) & RESERVED_MASK
;
209 writel(CTPL_MMC_SD
| reg_val
| WPP_ACTIVEHIGH
| CDP_ACTIVEHIGH
|
210 MIT_CTO
| DW8_1_4BITMODE
| MODE_FUNC
| STR_BLOCK
|
211 HR_NOHOSTRESP
| INIT_NOINIT
| NOOPENDRAIN
, &mmc_base
->con
);
214 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
215 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
216 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
217 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
218 start
= get_timer(0);
219 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
220 if (get_timer(0) - start
> MAX_RETRY_MS
) {
221 printf("%s: timedout waiting for ics!\n", __func__
);
225 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
227 writel(readl(&mmc_base
->hctl
) | SDBP_PWRON
, &mmc_base
->hctl
);
229 writel(IE_BADA
| IE_CERR
| IE_DEB
| IE_DCRC
| IE_DTO
| IE_CIE
|
230 IE_CEB
| IE_CCRC
| IE_CTO
| IE_BRR
| IE_BWR
| IE_TC
| IE_CC
,
233 mmc_init_stream(mmc_base
);
239 * MMC controller internal finite state machine reset
241 * Used to reset command or data internal state machines, using respectively
242 * SRC or SRD bit of SYSCTL register
244 static void mmc_reset_controller_fsm(struct hsmmc
*mmc_base
, u32 bit
)
248 mmc_reg_out(&mmc_base
->sysctl
, bit
, bit
);
251 * CMD(DAT) lines reset procedures are slightly different
252 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
253 * According to OMAP3 TRM:
254 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
256 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
257 * procedure steps must be as follows:
258 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
259 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
260 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
261 * 3. Wait until the SRC (SRD) bit returns to 0x0
262 * (reset procedure is completed).
264 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
265 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
266 if (!(readl(&mmc_base
->sysctl
) & bit
)) {
267 start
= get_timer(0);
268 while (!(readl(&mmc_base
->sysctl
) & bit
)) {
269 if (get_timer(0) - start
> MAX_RETRY_MS
)
274 start
= get_timer(0);
275 while ((readl(&mmc_base
->sysctl
) & bit
) != 0) {
276 if (get_timer(0) - start
> MAX_RETRY_MS
) {
277 printf("%s: timedout waiting for sysctl %x to clear\n",
284 static int omap_hsmmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
285 struct mmc_data
*data
)
287 struct hsmmc
*mmc_base
;
288 unsigned int flags
, mmc_stat
;
291 mmc_base
= ((struct omap_hsmmc_data
*)mmc
->priv
)->base_addr
;
292 start
= get_timer(0);
293 while ((readl(&mmc_base
->pstate
) & (DATI_MASK
| CMDI_MASK
)) != 0) {
294 if (get_timer(0) - start
> MAX_RETRY_MS
) {
295 printf("%s: timedout waiting on cmd inhibit to clear\n",
300 writel(0xFFFFFFFF, &mmc_base
->stat
);
301 start
= get_timer(0);
302 while (readl(&mmc_base
->stat
)) {
303 if (get_timer(0) - start
> MAX_RETRY_MS
) {
304 printf("%s: timedout waiting for STAT (%x) to clear\n",
305 __func__
, readl(&mmc_base
->stat
));
311 * CMDIDX[13:8] : Command index
312 * DATAPRNT[5] : Data Present Select
313 * ENCMDIDX[4] : Command Index Check Enable
314 * ENCMDCRC[3] : Command CRC Check Enable
319 * 11 = Length 48 Check busy after response
321 /* Delay added before checking the status of frq change
322 * retry not supported by mmc.c(core file)
324 if (cmd
->cmdidx
== SD_CMD_APP_SEND_SCR
)
325 udelay(50000); /* wait 50 ms */
327 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
329 else if (cmd
->resp_type
& MMC_RSP_136
)
330 flags
= RSP_TYPE_LGHT136
| CICE_NOCHECK
;
331 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
332 flags
= RSP_TYPE_LGHT48B
;
334 flags
= RSP_TYPE_LGHT48
;
336 /* enable default flags */
337 flags
= flags
| (CMD_TYPE_NORMAL
| CICE_NOCHECK
| CCCE_NOCHECK
|
338 MSBS_SGLEBLK
| ACEN_DISABLE
| BCE_DISABLE
| DE_DISABLE
);
340 if (cmd
->resp_type
& MMC_RSP_CRC
)
342 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
346 if ((cmd
->cmdidx
== MMC_CMD_READ_MULTIPLE_BLOCK
) ||
347 (cmd
->cmdidx
== MMC_CMD_WRITE_MULTIPLE_BLOCK
)) {
348 flags
|= (MSBS_MULTIBLK
| BCE_ENABLE
);
349 data
->blocksize
= 512;
350 writel(data
->blocksize
| (data
->blocks
<< 16),
353 writel(data
->blocksize
| NBLK_STPCNT
, &mmc_base
->blk
);
355 if (data
->flags
& MMC_DATA_READ
)
356 flags
|= (DP_DATA
| DDIR_READ
);
358 flags
|= (DP_DATA
| DDIR_WRITE
);
361 writel(cmd
->cmdarg
, &mmc_base
->arg
);
362 udelay(20); /* To fix "No status update" error on eMMC */
363 writel((cmd
->cmdidx
<< 24) | flags
, &mmc_base
->cmd
);
365 start
= get_timer(0);
367 mmc_stat
= readl(&mmc_base
->stat
);
368 if (get_timer(0) - start
> MAX_RETRY_MS
) {
369 printf("%s : timeout: No status update\n", __func__
);
374 if ((mmc_stat
& IE_CTO
) != 0) {
375 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRC
);
377 } else if ((mmc_stat
& ERRI_MASK
) != 0)
380 if (mmc_stat
& CC_MASK
) {
381 writel(CC_MASK
, &mmc_base
->stat
);
382 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
383 if (cmd
->resp_type
& MMC_RSP_136
) {
384 /* response type 2 */
385 cmd
->response
[3] = readl(&mmc_base
->rsp10
);
386 cmd
->response
[2] = readl(&mmc_base
->rsp32
);
387 cmd
->response
[1] = readl(&mmc_base
->rsp54
);
388 cmd
->response
[0] = readl(&mmc_base
->rsp76
);
390 /* response types 1, 1b, 3, 4, 5, 6 */
391 cmd
->response
[0] = readl(&mmc_base
->rsp10
);
395 if (data
&& (data
->flags
& MMC_DATA_READ
)) {
396 mmc_read_data(mmc_base
, data
->dest
,
397 data
->blocksize
* data
->blocks
);
398 } else if (data
&& (data
->flags
& MMC_DATA_WRITE
)) {
399 mmc_write_data(mmc_base
, data
->src
,
400 data
->blocksize
* data
->blocks
);
405 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
)
407 unsigned int *output_buf
= (unsigned int *)buf
;
408 unsigned int mmc_stat
;
414 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
418 ulong start
= get_timer(0);
420 mmc_stat
= readl(&mmc_base
->stat
);
421 if (get_timer(0) - start
> MAX_RETRY_MS
) {
422 printf("%s: timedout waiting for status!\n",
426 } while (mmc_stat
== 0);
428 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
429 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
431 if ((mmc_stat
& ERRI_MASK
) != 0)
434 if (mmc_stat
& BRR_MASK
) {
437 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
439 for (k
= 0; k
< count
; k
++) {
440 *output_buf
= readl(&mmc_base
->data
);
446 if (mmc_stat
& BWR_MASK
)
447 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
450 if (mmc_stat
& TC_MASK
) {
451 writel(readl(&mmc_base
->stat
) | TC_MASK
,
459 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
462 unsigned int *input_buf
= (unsigned int *)buf
;
463 unsigned int mmc_stat
;
469 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
473 ulong start
= get_timer(0);
475 mmc_stat
= readl(&mmc_base
->stat
);
476 if (get_timer(0) - start
> MAX_RETRY_MS
) {
477 printf("%s: timedout waiting for status!\n",
481 } while (mmc_stat
== 0);
483 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
484 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
486 if ((mmc_stat
& ERRI_MASK
) != 0)
489 if (mmc_stat
& BWR_MASK
) {
492 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
494 for (k
= 0; k
< count
; k
++) {
495 writel(*input_buf
, &mmc_base
->data
);
501 if (mmc_stat
& BRR_MASK
)
502 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
505 if (mmc_stat
& TC_MASK
) {
506 writel(readl(&mmc_base
->stat
) | TC_MASK
,
514 static void omap_hsmmc_set_ios(struct mmc
*mmc
)
516 struct hsmmc
*mmc_base
;
517 unsigned int dsor
= 0;
520 mmc_base
= ((struct omap_hsmmc_data
*)mmc
->priv
)->base_addr
;
521 /* configue bus width */
522 switch (mmc
->bus_width
) {
524 writel(readl(&mmc_base
->con
) | DTW_8_BITMODE
,
529 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
531 writel(readl(&mmc_base
->hctl
) | DTW_4_BITMODE
,
537 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
539 writel(readl(&mmc_base
->hctl
) & ~DTW_4_BITMODE
,
544 /* configure clock with 96Mhz system clock.
546 if (mmc
->clock
!= 0) {
547 dsor
= (MMC_CLOCK_REFERENCE
* 1000000 / mmc
->clock
);
548 if ((MMC_CLOCK_REFERENCE
* 1000000) / dsor
> mmc
->clock
)
552 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
553 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
555 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
556 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
558 start
= get_timer(0);
559 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
560 if (get_timer(0) - start
> MAX_RETRY_MS
) {
561 printf("%s: timedout waiting for ics!\n", __func__
);
565 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
568 #ifdef OMAP_HSMMC_USE_GPIO
570 static int omap_hsmmc_getcd(struct mmc
*mmc
)
572 struct omap_hsmmc_data
*priv
= mmc
->priv
;
575 value
= dm_gpio_get_value(&priv
->cd_gpio
);
576 /* if no CD return as 1 */
580 if (priv
->cd_inverted
)
585 static int omap_hsmmc_getwp(struct mmc
*mmc
)
587 struct omap_hsmmc_data
*priv
= mmc
->priv
;
590 value
= dm_gpio_get_value(&priv
->wp_gpio
);
591 /* if no WP return as 0 */
597 static int omap_hsmmc_getcd(struct mmc
*mmc
)
599 struct omap_hsmmc_data
*priv_data
= mmc
->priv
;
602 /* if no CD return as 1 */
603 cd_gpio
= priv_data
->cd_gpio
;
607 /* NOTE: assumes card detect signal is active-low */
608 return !gpio_get_value(cd_gpio
);
611 static int omap_hsmmc_getwp(struct mmc
*mmc
)
613 struct omap_hsmmc_data
*priv_data
= mmc
->priv
;
616 /* if no WP return as 0 */
617 wp_gpio
= priv_data
->wp_gpio
;
621 /* NOTE: assumes write protect signal is active-high */
622 return gpio_get_value(wp_gpio
);
627 static const struct mmc_ops omap_hsmmc_ops
= {
628 .send_cmd
= omap_hsmmc_send_cmd
,
629 .set_ios
= omap_hsmmc_set_ios
,
630 .init
= omap_hsmmc_init_setup
,
631 #ifdef OMAP_HSMMC_USE_GPIO
632 .getcd
= omap_hsmmc_getcd
,
633 .getwp
= omap_hsmmc_getwp
,
637 #ifndef CONFIG_DM_MMC
638 int omap_mmc_init(int dev_index
, uint host_caps_mask
, uint f_max
, int cd_gpio
,
642 struct omap_hsmmc_data
*priv_data
;
643 struct mmc_config
*cfg
;
646 priv_data
= malloc(sizeof(*priv_data
));
647 if (priv_data
== NULL
)
650 host_caps_val
= MMC_MODE_4BIT
| MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
654 priv_data
->base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
656 #ifdef OMAP_HSMMC2_BASE
658 priv_data
->base_addr
= (struct hsmmc
*)OMAP_HSMMC2_BASE
;
659 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
660 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
661 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
662 defined(CONFIG_HSMMC2_8BIT)
663 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
664 host_caps_val
|= MMC_MODE_8BIT
;
668 #ifdef OMAP_HSMMC3_BASE
670 priv_data
->base_addr
= (struct hsmmc
*)OMAP_HSMMC3_BASE
;
671 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
672 /* Enable 8-bit interface for eMMC on DRA7XX */
673 host_caps_val
|= MMC_MODE_8BIT
;
678 priv_data
->base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
681 #ifdef OMAP_HSMMC_USE_GPIO
682 /* on error gpio values are set to -1, which is what we want */
683 priv_data
->cd_gpio
= omap_mmc_setup_gpio_in(cd_gpio
, "mmc_cd");
684 priv_data
->wp_gpio
= omap_mmc_setup_gpio_in(wp_gpio
, "mmc_wp");
687 cfg
= &priv_data
->cfg
;
689 cfg
->name
= "OMAP SD/MMC";
690 cfg
->ops
= &omap_hsmmc_ops
;
692 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
693 cfg
->host_caps
= host_caps_val
& ~host_caps_mask
;
700 if (cfg
->host_caps
& MMC_MODE_HS
) {
701 if (cfg
->host_caps
& MMC_MODE_HS_52MHz
)
702 cfg
->f_max
= 52000000;
704 cfg
->f_max
= 26000000;
706 cfg
->f_max
= 20000000;
709 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
711 #if defined(CONFIG_OMAP34XX)
713 * Silicon revs 2.1 and older do not support multiblock transfers.
715 if ((get_cpu_family() == CPU_OMAP34XX
) && (get_cpu_rev() <= CPU_3XX_ES21
))
718 mmc
= mmc_create(cfg
, priv_data
);
725 static int omap_hsmmc_ofdata_to_platdata(struct udevice
*dev
)
727 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
728 const void *fdt
= gd
->fdt_blob
;
729 int node
= dev
->of_offset
;
730 struct mmc_config
*cfg
;
733 priv
->base_addr
= map_physmem(dev_get_addr(dev
), sizeof(struct hsmmc
*),
737 cfg
->host_caps
= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
738 val
= fdtdec_get_int(fdt
, node
, "bus-width", -1);
740 printf("error: bus-width property missing\n");
746 cfg
->host_caps
|= MMC_MODE_8BIT
;
748 cfg
->host_caps
|= MMC_MODE_4BIT
;
751 printf("error: invalid bus-width property\n");
756 cfg
->f_max
= fdtdec_get_int(fdt
, node
, "max-frequency", 52000000);
757 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
758 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
760 #ifdef OMAP_HSMMC_USE_GPIO
761 priv
->cd_inverted
= fdtdec_get_bool(fdt
, node
, "cd-inverted");
767 static int omap_hsmmc_probe(struct udevice
*dev
)
769 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
770 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
771 struct mmc_config
*cfg
;
775 cfg
->name
= "OMAP SD/MMC";
776 cfg
->ops
= &omap_hsmmc_ops
;
778 mmc
= mmc_create(cfg
, priv
);
782 #ifdef OMAP_HSMMC_USE_GPIO
783 gpio_request_by_name(dev
, "cd-gpios", 0, &priv
->cd_gpio
, GPIOD_IS_IN
);
784 gpio_request_by_name(dev
, "wp-gpios", 0, &priv
->wp_gpio
, GPIOD_IS_IN
);
793 static const struct udevice_id omap_hsmmc_ids
[] = {
794 { .compatible
= "ti,omap3-hsmmc" },
795 { .compatible
= "ti,omap4-hsmmc" },
796 { .compatible
= "ti,am33xx-hsmmc" },
800 U_BOOT_DRIVER(omap_hsmmc
) = {
801 .name
= "omap_hsmmc",
803 .of_match
= omap_hsmmc_ids
,
804 .ofdata_to_platdata
= omap_hsmmc_ofdata_to_platdata
,
805 .probe
= omap_hsmmc_probe
,
806 .priv_auto_alloc_size
= sizeof(struct omap_hsmmc_data
),