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mmc: omap_hsmmc: Workaround for errata id i802
[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c
1 /*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25 #include <config.h>
26 #include <common.h>
27 #include <malloc.h>
28 #include <memalign.h>
29 #include <mmc.h>
30 #include <part.h>
31 #include <i2c.h>
32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
33 #include <palmas.h>
34 #endif
35 #include <asm/io.h>
36 #include <asm/arch/mmc_host_def.h>
37 #if !defined(CONFIG_SOC_KEYSTONE)
38 #include <asm/gpio.h>
39 #include <asm/arch/sys_proto.h>
40 #endif
41 #ifdef CONFIG_MMC_OMAP36XX_PINS
42 #include <asm/arch/mux.h>
43 #endif
44 #include <dm.h>
45
46 DECLARE_GLOBAL_DATA_PTR;
47
48 /* simplify defines to OMAP_HSMMC_USE_GPIO */
49 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
50 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
51 #define OMAP_HSMMC_USE_GPIO
52 #else
53 #undef OMAP_HSMMC_USE_GPIO
54 #endif
55
56 /* common definitions for all OMAPs */
57 #define SYSCTL_SRC (1 << 25)
58 #define SYSCTL_SRD (1 << 26)
59
60 struct omap_hsmmc_data {
61 struct hsmmc *base_addr;
62 #if !CONFIG_IS_ENABLED(DM_MMC)
63 struct mmc_config cfg;
64 #endif
65 uint bus_width;
66 uint clock;
67 #ifdef OMAP_HSMMC_USE_GPIO
68 #if CONFIG_IS_ENABLED(DM_MMC)
69 struct gpio_desc cd_gpio; /* Change Detect GPIO */
70 struct gpio_desc wp_gpio; /* Write Protect GPIO */
71 bool cd_inverted;
72 #else
73 int cd_gpio;
74 int wp_gpio;
75 #endif
76 #endif
77 #if CONFIG_IS_ENABLED(DM_MMC)
78 uint iov;
79 enum bus_mode mode;
80 #endif
81 u8 controller_flags;
82 #ifndef CONFIG_OMAP34XX
83 struct omap_hsmmc_adma_desc *adma_desc_table;
84 uint desc_slot;
85 #endif
86 };
87
88 #ifndef CONFIG_OMAP34XX
89 struct omap_hsmmc_adma_desc {
90 u8 attr;
91 u8 reserved;
92 u16 len;
93 u32 addr;
94 };
95
96 #define ADMA_MAX_LEN 63488
97
98 /* Decriptor table defines */
99 #define ADMA_DESC_ATTR_VALID BIT(0)
100 #define ADMA_DESC_ATTR_END BIT(1)
101 #define ADMA_DESC_ATTR_INT BIT(2)
102 #define ADMA_DESC_ATTR_ACT1 BIT(4)
103 #define ADMA_DESC_ATTR_ACT2 BIT(5)
104
105 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
106 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
107 #endif
108
109 /* If we fail after 1 second wait, something is really bad */
110 #define MAX_RETRY_MS 1000
111
112 /* DMA transfers can take a long time if a lot a data is transferred.
113 * The timeout must take in account the amount of data. Let's assume
114 * that the time will never exceed 333 ms per MB (in other word we assume
115 * that the bandwidth is always above 3MB/s).
116 */
117 #define DMA_TIMEOUT_PER_MB 333
118 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
119 #define OMAP_HSMMC_NO_1_8_V BIT(1)
120 #define OMAP_HSMMC_USE_ADMA BIT(2)
121
122 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
123 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
124 unsigned int siz);
125 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
126 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
127 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
128
129 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
130 {
131 #if CONFIG_IS_ENABLED(DM_MMC)
132 return dev_get_priv(mmc->dev);
133 #else
134 return (struct omap_hsmmc_data *)mmc->priv;
135 #endif
136 }
137 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
138 {
139 #if CONFIG_IS_ENABLED(DM_MMC)
140 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
141 return &plat->cfg;
142 #else
143 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
144 #endif
145 }
146
147 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
148 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
149 {
150 int ret;
151
152 #ifndef CONFIG_DM_GPIO
153 if (!gpio_is_valid(gpio))
154 return -1;
155 #endif
156 ret = gpio_request(gpio, label);
157 if (ret)
158 return ret;
159
160 ret = gpio_direction_input(gpio);
161 if (ret)
162 return ret;
163
164 return gpio;
165 }
166 #endif
167
168 static unsigned char mmc_board_init(struct mmc *mmc)
169 {
170 #if defined(CONFIG_OMAP34XX)
171 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
172 t2_t *t2_base = (t2_t *)T2_BASE;
173 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
174 u32 pbias_lite;
175 #ifdef CONFIG_MMC_OMAP36XX_PINS
176 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
177 #endif
178
179 pbias_lite = readl(&t2_base->pbias_lite);
180 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
181 #ifdef CONFIG_TARGET_OMAP3_CAIRO
182 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
183 pbias_lite &= ~PBIASLITEVMODE0;
184 #endif
185 #ifdef CONFIG_MMC_OMAP36XX_PINS
186 if (get_cpu_family() == CPU_OMAP36XX) {
187 /* Disable extended drain IO before changing PBIAS */
188 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
189 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
190 }
191 #endif
192 writel(pbias_lite, &t2_base->pbias_lite);
193
194 writel(pbias_lite | PBIASLITEPWRDNZ1 |
195 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
196 &t2_base->pbias_lite);
197
198 #ifdef CONFIG_MMC_OMAP36XX_PINS
199 if (get_cpu_family() == CPU_OMAP36XX)
200 /* Enable extended drain IO after changing PBIAS */
201 writel(wkup_ctrl |
202 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
203 OMAP34XX_CTRL_WKUP_CTRL);
204 #endif
205 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
206 &t2_base->devconf0);
207
208 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
209 &t2_base->devconf1);
210
211 /* Change from default of 52MHz to 26MHz if necessary */
212 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
213 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
214 &t2_base->ctl_prog_io1);
215
216 writel(readl(&prcm_base->fclken1_core) |
217 EN_MMC1 | EN_MMC2 | EN_MMC3,
218 &prcm_base->fclken1_core);
219
220 writel(readl(&prcm_base->iclken1_core) |
221 EN_MMC1 | EN_MMC2 | EN_MMC3,
222 &prcm_base->iclken1_core);
223 #endif
224
225 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
226 /* PBIAS config needed for MMC1 only */
227 if (mmc_get_blk_desc(mmc)->devnum == 0)
228 vmmc_pbias_config(LDO_VOLT_3V0);
229 #endif
230
231 return 0;
232 }
233
234 void mmc_init_stream(struct hsmmc *mmc_base)
235 {
236 ulong start;
237
238 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
239
240 writel(MMC_CMD0, &mmc_base->cmd);
241 start = get_timer(0);
242 while (!(readl(&mmc_base->stat) & CC_MASK)) {
243 if (get_timer(0) - start > MAX_RETRY_MS) {
244 printf("%s: timedout waiting for cc!\n", __func__);
245 return;
246 }
247 }
248 writel(CC_MASK, &mmc_base->stat)
249 ;
250 writel(MMC_CMD0, &mmc_base->cmd)
251 ;
252 start = get_timer(0);
253 while (!(readl(&mmc_base->stat) & CC_MASK)) {
254 if (get_timer(0) - start > MAX_RETRY_MS) {
255 printf("%s: timedout waiting for cc2!\n", __func__);
256 return;
257 }
258 }
259 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
260 }
261
262 #if CONFIG_IS_ENABLED(DM_MMC)
263 static void omap_hsmmc_set_timing(struct mmc *mmc)
264 {
265 u32 val;
266 struct hsmmc *mmc_base;
267 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
268
269 mmc_base = priv->base_addr;
270
271 val = readl(&mmc_base->ac12);
272 val &= ~AC12_UHSMC_MASK;
273 priv->mode = mmc->selected_mode;
274
275 if (mmc_is_mode_ddr(priv->mode))
276 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
277 else
278 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
279
280 switch (priv->mode) {
281 case MMC_HS_200:
282 case UHS_SDR104:
283 val |= AC12_UHSMC_SDR104;
284 break;
285 case UHS_SDR50:
286 val |= AC12_UHSMC_SDR50;
287 break;
288 case MMC_DDR_52:
289 case UHS_DDR50:
290 val |= AC12_UHSMC_DDR50;
291 break;
292 case SD_HS:
293 case MMC_HS_52:
294 case UHS_SDR25:
295 val |= AC12_UHSMC_SDR25;
296 break;
297 case MMC_LEGACY:
298 case MMC_HS:
299 case SD_LEGACY:
300 case UHS_SDR12:
301 val |= AC12_UHSMC_SDR12;
302 break;
303 default:
304 val |= AC12_UHSMC_RES;
305 break;
306 }
307 writel(val, &mmc_base->ac12);
308 }
309
310 static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
311 {
312 struct hsmmc *mmc_base;
313 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
314 u32 val;
315
316 mmc_base = priv->base_addr;
317
318 val = readl(&mmc_base->hctl) & ~SDVS_MASK;
319
320 switch (priv->iov) {
321 case IOV_3V3:
322 val |= SDVS_3V3;
323 break;
324 case IOV_3V0:
325 val |= SDVS_3V0;
326 break;
327 case IOV_1V8:
328 val |= SDVS_1V8;
329 break;
330 }
331
332 writel(val, &mmc_base->hctl);
333 }
334
335 static void omap_hsmmc_set_capabilities(struct mmc *mmc)
336 {
337 struct hsmmc *mmc_base;
338 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
339 u32 val;
340
341 mmc_base = priv->base_addr;
342 val = readl(&mmc_base->capa);
343
344 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
345 val |= (VS30_3V0SUP | VS18_1V8SUP);
346 priv->iov = IOV_3V0;
347 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
348 val |= VS30_3V0SUP;
349 val &= ~VS18_1V8SUP;
350 priv->iov = IOV_3V0;
351 } else {
352 val |= VS18_1V8SUP;
353 val &= ~VS30_3V0SUP;
354 priv->iov = IOV_1V8;
355 }
356
357 writel(val, &mmc_base->capa);
358 }
359
360 #ifdef MMC_SUPPORTS_TUNING
361 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
362 {
363 struct hsmmc *mmc_base;
364 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
365 u32 val;
366
367 mmc_base = priv->base_addr;
368 val = readl(&mmc_base->ac12);
369 val &= ~(AC12_SCLK_SEL);
370 writel(val, &mmc_base->ac12);
371
372 val = readl(&mmc_base->dll);
373 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
374 writel(val, &mmc_base->dll);
375 }
376
377 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
378 {
379 int i;
380 struct hsmmc *mmc_base;
381 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
382 u32 val;
383
384 mmc_base = priv->base_addr;
385 val = readl(&mmc_base->dll);
386 val |= DLL_FORCE_VALUE;
387 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
388 val |= (count << DLL_FORCE_SR_C_SHIFT);
389 writel(val, &mmc_base->dll);
390
391 val |= DLL_CALIB;
392 writel(val, &mmc_base->dll);
393 for (i = 0; i < 1000; i++) {
394 if (readl(&mmc_base->dll) & DLL_CALIB)
395 break;
396 }
397 val &= ~DLL_CALIB;
398 writel(val, &mmc_base->dll);
399 }
400
401 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
402 {
403 struct omap_hsmmc_data *priv = dev_get_priv(dev);
404 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
405 struct mmc *mmc = upriv->mmc;
406 struct hsmmc *mmc_base;
407 u32 val;
408 u8 cur_match, prev_match = 0;
409 int ret;
410 u32 phase_delay = 0;
411 u32 start_window = 0, max_window = 0;
412 u32 length = 0, max_len = 0;
413
414 mmc_base = priv->base_addr;
415 val = readl(&mmc_base->capa2);
416
417 /* clock tuning is not needed for upto 52MHz */
418 if (!((mmc->selected_mode == MMC_HS_200) ||
419 (mmc->selected_mode == UHS_SDR104) ||
420 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
421 return 0;
422
423 val = readl(&mmc_base->dll);
424 val |= DLL_SWT;
425 writel(val, &mmc_base->dll);
426 while (phase_delay <= MAX_PHASE_DELAY) {
427 omap_hsmmc_set_dll(mmc, phase_delay);
428
429 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
430
431 if (cur_match) {
432 if (prev_match) {
433 length++;
434 } else {
435 start_window = phase_delay;
436 length = 1;
437 }
438 }
439
440 if (length > max_len) {
441 max_window = start_window;
442 max_len = length;
443 }
444
445 prev_match = cur_match;
446 phase_delay += 4;
447 }
448
449 if (!max_len) {
450 ret = -EIO;
451 goto tuning_error;
452 }
453
454 val = readl(&mmc_base->ac12);
455 if (!(val & AC12_SCLK_SEL)) {
456 ret = -EIO;
457 goto tuning_error;
458 }
459
460 phase_delay = max_window + 4 * ((3 * max_len) >> 2);
461 omap_hsmmc_set_dll(mmc, phase_delay);
462
463 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
464 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
465
466 return 0;
467
468 tuning_error:
469
470 omap_hsmmc_disable_tuning(mmc);
471 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
472 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
473
474 return ret;
475 }
476 #endif
477 #endif
478
479 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
480 {
481 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
482 struct hsmmc *mmc_base = priv->base_addr;
483 u32 irq_mask = INT_EN_MASK;
484
485 /*
486 * TODO: Errata i802 indicates only DCRC interrupts can occur during
487 * tuning procedure and DCRC should be disabled. But see occurences
488 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
489 * interrupts occur along with BRR, so the data is actually in the
490 * buffer. It has to be debugged why these interrutps occur
491 */
492 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
493 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
494
495 writel(irq_mask, &mmc_base->ie);
496 }
497
498 static int omap_hsmmc_init_setup(struct mmc *mmc)
499 {
500 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
501 struct hsmmc *mmc_base;
502 unsigned int reg_val;
503 unsigned int dsor;
504 ulong start;
505
506 mmc_base = priv->base_addr;
507 mmc_board_init(mmc);
508
509 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
510 &mmc_base->sysconfig);
511 start = get_timer(0);
512 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
513 if (get_timer(0) - start > MAX_RETRY_MS) {
514 printf("%s: timedout waiting for cc2!\n", __func__);
515 return -ETIMEDOUT;
516 }
517 }
518 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
519 start = get_timer(0);
520 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
521 if (get_timer(0) - start > MAX_RETRY_MS) {
522 printf("%s: timedout waiting for softresetall!\n",
523 __func__);
524 return -ETIMEDOUT;
525 }
526 }
527 #ifndef CONFIG_OMAP34XX
528 reg_val = readl(&mmc_base->hl_hwinfo);
529 if (reg_val & MADMA_EN)
530 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
531 #endif
532
533 #if CONFIG_IS_ENABLED(DM_MMC)
534 omap_hsmmc_set_capabilities(mmc);
535 omap_hsmmc_conf_bus_power(mmc);
536 #else
537 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
538 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
539 &mmc_base->capa);
540 #endif
541
542 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
543
544 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
545 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
546 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
547
548 dsor = 240;
549 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
550 (ICE_STOP | DTO_15THDTO));
551 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
552 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
553 start = get_timer(0);
554 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
555 if (get_timer(0) - start > MAX_RETRY_MS) {
556 printf("%s: timedout waiting for ics!\n", __func__);
557 return -ETIMEDOUT;
558 }
559 }
560 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
561
562 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
563
564 mmc_enable_irq(mmc, NULL);
565 mmc_init_stream(mmc_base);
566
567 return 0;
568 }
569
570 /*
571 * MMC controller internal finite state machine reset
572 *
573 * Used to reset command or data internal state machines, using respectively
574 * SRC or SRD bit of SYSCTL register
575 */
576 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
577 {
578 ulong start;
579
580 mmc_reg_out(&mmc_base->sysctl, bit, bit);
581
582 /*
583 * CMD(DAT) lines reset procedures are slightly different
584 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
585 * According to OMAP3 TRM:
586 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
587 * returns to 0x0.
588 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
589 * procedure steps must be as follows:
590 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
591 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
592 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
593 * 3. Wait until the SRC (SRD) bit returns to 0x0
594 * (reset procedure is completed).
595 */
596 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
597 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
598 if (!(readl(&mmc_base->sysctl) & bit)) {
599 start = get_timer(0);
600 while (!(readl(&mmc_base->sysctl) & bit)) {
601 if (get_timer(0) - start > MAX_RETRY_MS)
602 return;
603 }
604 }
605 #endif
606 start = get_timer(0);
607 while ((readl(&mmc_base->sysctl) & bit) != 0) {
608 if (get_timer(0) - start > MAX_RETRY_MS) {
609 printf("%s: timedout waiting for sysctl %x to clear\n",
610 __func__, bit);
611 return;
612 }
613 }
614 }
615
616 #ifndef CONFIG_OMAP34XX
617 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
618 {
619 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
620 struct omap_hsmmc_adma_desc *desc;
621 u8 attr;
622
623 desc = &priv->adma_desc_table[priv->desc_slot];
624
625 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
626 if (!end)
627 priv->desc_slot++;
628 else
629 attr |= ADMA_DESC_ATTR_END;
630
631 desc->len = len;
632 desc->addr = (u32)buf;
633 desc->reserved = 0;
634 desc->attr = attr;
635 }
636
637 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
638 struct mmc_data *data)
639 {
640 uint total_len = data->blocksize * data->blocks;
641 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
642 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
643 int i = desc_count;
644 char *buf;
645
646 priv->desc_slot = 0;
647 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
648 memalign(ARCH_DMA_MINALIGN, desc_count *
649 sizeof(struct omap_hsmmc_adma_desc));
650
651 if (data->flags & MMC_DATA_READ)
652 buf = data->dest;
653 else
654 buf = (char *)data->src;
655
656 while (--i) {
657 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
658 buf += ADMA_MAX_LEN;
659 total_len -= ADMA_MAX_LEN;
660 }
661
662 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
663
664 flush_dcache_range((long)priv->adma_desc_table,
665 (long)priv->adma_desc_table +
666 ROUND(desc_count *
667 sizeof(struct omap_hsmmc_adma_desc),
668 ARCH_DMA_MINALIGN));
669 }
670
671 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
672 {
673 struct hsmmc *mmc_base;
674 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
675 u32 val;
676 char *buf;
677
678 mmc_base = priv->base_addr;
679 omap_hsmmc_prepare_adma_table(mmc, data);
680
681 if (data->flags & MMC_DATA_READ)
682 buf = data->dest;
683 else
684 buf = (char *)data->src;
685
686 val = readl(&mmc_base->hctl);
687 val |= DMA_SELECT;
688 writel(val, &mmc_base->hctl);
689
690 val = readl(&mmc_base->con);
691 val |= DMA_MASTER;
692 writel(val, &mmc_base->con);
693
694 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
695
696 flush_dcache_range((u32)buf,
697 (u32)buf +
698 ROUND(data->blocksize * data->blocks,
699 ARCH_DMA_MINALIGN));
700 }
701
702 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
703 {
704 struct hsmmc *mmc_base;
705 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
706 u32 val;
707
708 mmc_base = priv->base_addr;
709
710 val = readl(&mmc_base->con);
711 val &= ~DMA_MASTER;
712 writel(val, &mmc_base->con);
713
714 val = readl(&mmc_base->hctl);
715 val &= ~DMA_SELECT;
716 writel(val, &mmc_base->hctl);
717
718 kfree(priv->adma_desc_table);
719 }
720 #else
721 #define omap_hsmmc_adma_desc
722 #define omap_hsmmc_prepare_adma_table
723 #define omap_hsmmc_prepare_data
724 #define omap_hsmmc_dma_cleanup
725 #endif
726
727 #if !CONFIG_IS_ENABLED(DM_MMC)
728 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
729 struct mmc_data *data)
730 {
731 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
732 #else
733 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
734 struct mmc_data *data)
735 {
736 struct omap_hsmmc_data *priv = dev_get_priv(dev);
737 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
738 struct mmc *mmc = upriv->mmc;
739 #endif
740 struct hsmmc *mmc_base;
741 unsigned int flags, mmc_stat;
742 ulong start;
743
744 mmc_base = priv->base_addr;
745
746 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
747 return 0;
748
749 start = get_timer(0);
750 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
751 if (get_timer(0) - start > MAX_RETRY_MS) {
752 printf("%s: timedout waiting on cmd inhibit to clear\n",
753 __func__);
754 return -ETIMEDOUT;
755 }
756 }
757 writel(0xFFFFFFFF, &mmc_base->stat);
758 start = get_timer(0);
759 while (readl(&mmc_base->stat)) {
760 if (get_timer(0) - start > MAX_RETRY_MS) {
761 printf("%s: timedout waiting for STAT (%x) to clear\n",
762 __func__, readl(&mmc_base->stat));
763 return -ETIMEDOUT;
764 }
765 }
766 /*
767 * CMDREG
768 * CMDIDX[13:8] : Command index
769 * DATAPRNT[5] : Data Present Select
770 * ENCMDIDX[4] : Command Index Check Enable
771 * ENCMDCRC[3] : Command CRC Check Enable
772 * RSPTYP[1:0]
773 * 00 = No Response
774 * 01 = Length 136
775 * 10 = Length 48
776 * 11 = Length 48 Check busy after response
777 */
778 /* Delay added before checking the status of frq change
779 * retry not supported by mmc.c(core file)
780 */
781 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
782 udelay(50000); /* wait 50 ms */
783
784 if (!(cmd->resp_type & MMC_RSP_PRESENT))
785 flags = 0;
786 else if (cmd->resp_type & MMC_RSP_136)
787 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
788 else if (cmd->resp_type & MMC_RSP_BUSY)
789 flags = RSP_TYPE_LGHT48B;
790 else
791 flags = RSP_TYPE_LGHT48;
792
793 /* enable default flags */
794 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
795 MSBS_SGLEBLK);
796 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
797
798 if (cmd->resp_type & MMC_RSP_CRC)
799 flags |= CCCE_CHECK;
800 if (cmd->resp_type & MMC_RSP_OPCODE)
801 flags |= CICE_CHECK;
802
803 if (data) {
804 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
805 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
806 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
807 data->blocksize = 512;
808 writel(data->blocksize | (data->blocks << 16),
809 &mmc_base->blk);
810 } else
811 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
812
813 if (data->flags & MMC_DATA_READ)
814 flags |= (DP_DATA | DDIR_READ);
815 else
816 flags |= (DP_DATA | DDIR_WRITE);
817
818 #ifndef CONFIG_OMAP34XX
819 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
820 !mmc_is_tuning_cmd(cmd->cmdidx)) {
821 omap_hsmmc_prepare_data(mmc, data);
822 flags |= DE_ENABLE;
823 }
824 #endif
825 }
826
827 mmc_enable_irq(mmc, cmd);
828
829 writel(cmd->cmdarg, &mmc_base->arg);
830 udelay(20); /* To fix "No status update" error on eMMC */
831 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
832
833 start = get_timer(0);
834 do {
835 mmc_stat = readl(&mmc_base->stat);
836 if (get_timer(start) > MAX_RETRY_MS) {
837 printf("%s : timeout: No status update\n", __func__);
838 return -ETIMEDOUT;
839 }
840 } while (!mmc_stat);
841
842 if ((mmc_stat & IE_CTO) != 0) {
843 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
844 return -ETIMEDOUT;
845 } else if ((mmc_stat & ERRI_MASK) != 0)
846 return -1;
847
848 if (mmc_stat & CC_MASK) {
849 writel(CC_MASK, &mmc_base->stat);
850 if (cmd->resp_type & MMC_RSP_PRESENT) {
851 if (cmd->resp_type & MMC_RSP_136) {
852 /* response type 2 */
853 cmd->response[3] = readl(&mmc_base->rsp10);
854 cmd->response[2] = readl(&mmc_base->rsp32);
855 cmd->response[1] = readl(&mmc_base->rsp54);
856 cmd->response[0] = readl(&mmc_base->rsp76);
857 } else
858 /* response types 1, 1b, 3, 4, 5, 6 */
859 cmd->response[0] = readl(&mmc_base->rsp10);
860 }
861 }
862
863 #ifndef CONFIG_OMAP34XX
864 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
865 !mmc_is_tuning_cmd(cmd->cmdidx)) {
866 u32 sz_mb, timeout;
867
868 if (mmc_stat & IE_ADMAE) {
869 omap_hsmmc_dma_cleanup(mmc);
870 return -EIO;
871 }
872
873 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
874 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
875 if (timeout < MAX_RETRY_MS)
876 timeout = MAX_RETRY_MS;
877
878 start = get_timer(0);
879 do {
880 mmc_stat = readl(&mmc_base->stat);
881 if (mmc_stat & TC_MASK) {
882 writel(readl(&mmc_base->stat) | TC_MASK,
883 &mmc_base->stat);
884 break;
885 }
886 if (get_timer(start) > timeout) {
887 printf("%s : DMA timeout: No status update\n",
888 __func__);
889 return -ETIMEDOUT;
890 }
891 } while (1);
892
893 omap_hsmmc_dma_cleanup(mmc);
894 return 0;
895 }
896 #endif
897
898 if (data && (data->flags & MMC_DATA_READ)) {
899 mmc_read_data(mmc_base, data->dest,
900 data->blocksize * data->blocks);
901 } else if (data && (data->flags & MMC_DATA_WRITE)) {
902 mmc_write_data(mmc_base, data->src,
903 data->blocksize * data->blocks);
904 }
905 return 0;
906 }
907
908 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
909 {
910 unsigned int *output_buf = (unsigned int *)buf;
911 unsigned int mmc_stat;
912 unsigned int count;
913
914 /*
915 * Start Polled Read
916 */
917 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
918 count /= 4;
919
920 while (size) {
921 ulong start = get_timer(0);
922 do {
923 mmc_stat = readl(&mmc_base->stat);
924 if (get_timer(0) - start > MAX_RETRY_MS) {
925 printf("%s: timedout waiting for status!\n",
926 __func__);
927 return -ETIMEDOUT;
928 }
929 } while (mmc_stat == 0);
930
931 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
932 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
933
934 if ((mmc_stat & ERRI_MASK) != 0)
935 return 1;
936
937 if (mmc_stat & BRR_MASK) {
938 unsigned int k;
939
940 writel(readl(&mmc_base->stat) | BRR_MASK,
941 &mmc_base->stat);
942 for (k = 0; k < count; k++) {
943 *output_buf = readl(&mmc_base->data);
944 output_buf++;
945 }
946 size -= (count*4);
947 }
948
949 if (mmc_stat & BWR_MASK)
950 writel(readl(&mmc_base->stat) | BWR_MASK,
951 &mmc_base->stat);
952
953 if (mmc_stat & TC_MASK) {
954 writel(readl(&mmc_base->stat) | TC_MASK,
955 &mmc_base->stat);
956 break;
957 }
958 }
959 return 0;
960 }
961
962 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
963 unsigned int size)
964 {
965 unsigned int *input_buf = (unsigned int *)buf;
966 unsigned int mmc_stat;
967 unsigned int count;
968
969 /*
970 * Start Polled Write
971 */
972 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
973 count /= 4;
974
975 while (size) {
976 ulong start = get_timer(0);
977 do {
978 mmc_stat = readl(&mmc_base->stat);
979 if (get_timer(0) - start > MAX_RETRY_MS) {
980 printf("%s: timedout waiting for status!\n",
981 __func__);
982 return -ETIMEDOUT;
983 }
984 } while (mmc_stat == 0);
985
986 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
987 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
988
989 if ((mmc_stat & ERRI_MASK) != 0)
990 return 1;
991
992 if (mmc_stat & BWR_MASK) {
993 unsigned int k;
994
995 writel(readl(&mmc_base->stat) | BWR_MASK,
996 &mmc_base->stat);
997 for (k = 0; k < count; k++) {
998 writel(*input_buf, &mmc_base->data);
999 input_buf++;
1000 }
1001 size -= (count*4);
1002 }
1003
1004 if (mmc_stat & BRR_MASK)
1005 writel(readl(&mmc_base->stat) | BRR_MASK,
1006 &mmc_base->stat);
1007
1008 if (mmc_stat & TC_MASK) {
1009 writel(readl(&mmc_base->stat) | TC_MASK,
1010 &mmc_base->stat);
1011 break;
1012 }
1013 }
1014 return 0;
1015 }
1016
1017 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1018 {
1019 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1020 }
1021
1022 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1023 {
1024 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1025 }
1026
1027 static void omap_hsmmc_set_clock(struct mmc *mmc)
1028 {
1029 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1030 struct hsmmc *mmc_base;
1031 unsigned int dsor = 0;
1032 ulong start;
1033
1034 mmc_base = priv->base_addr;
1035 omap_hsmmc_stop_clock(mmc_base);
1036
1037 /* TODO: Is setting DTO required here? */
1038 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1039 (ICE_STOP | DTO_15THDTO));
1040
1041 if (mmc->clock != 0) {
1042 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1043 if (dsor > CLKD_MAX)
1044 dsor = CLKD_MAX;
1045 } else {
1046 dsor = CLKD_MAX;
1047 }
1048
1049 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1050 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1051
1052 start = get_timer(0);
1053 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1054 if (get_timer(0) - start > MAX_RETRY_MS) {
1055 printf("%s: timedout waiting for ics!\n", __func__);
1056 return;
1057 }
1058 }
1059
1060 priv->clock = mmc->clock;
1061 omap_hsmmc_start_clock(mmc_base);
1062 }
1063
1064 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1065 {
1066 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1067 struct hsmmc *mmc_base;
1068
1069 mmc_base = priv->base_addr;
1070 /* configue bus width */
1071 switch (mmc->bus_width) {
1072 case 8:
1073 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1074 &mmc_base->con);
1075 break;
1076
1077 case 4:
1078 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1079 &mmc_base->con);
1080 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1081 &mmc_base->hctl);
1082 break;
1083
1084 case 1:
1085 default:
1086 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1087 &mmc_base->con);
1088 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1089 &mmc_base->hctl);
1090 break;
1091 }
1092
1093 priv->bus_width = mmc->bus_width;
1094 }
1095
1096 #if !CONFIG_IS_ENABLED(DM_MMC)
1097 static int omap_hsmmc_set_ios(struct mmc *mmc)
1098 {
1099 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1100 #else
1101 static int omap_hsmmc_set_ios(struct udevice *dev)
1102 {
1103 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1104 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1105 struct mmc *mmc = upriv->mmc;
1106 #endif
1107
1108 if (priv->bus_width != mmc->bus_width)
1109 omap_hsmmc_set_bus_width(mmc);
1110
1111 if (priv->clock != mmc->clock)
1112 omap_hsmmc_set_clock(mmc);
1113
1114 #if CONFIG_IS_ENABLED(DM_MMC)
1115 if (priv->mode != mmc->selected_mode)
1116 omap_hsmmc_set_timing(mmc);
1117 #endif
1118 return 0;
1119 }
1120
1121 #ifdef OMAP_HSMMC_USE_GPIO
1122 #if CONFIG_IS_ENABLED(DM_MMC)
1123 static int omap_hsmmc_getcd(struct udevice *dev)
1124 {
1125 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1126 int value;
1127
1128 value = dm_gpio_get_value(&priv->cd_gpio);
1129 /* if no CD return as 1 */
1130 if (value < 0)
1131 return 1;
1132
1133 if (priv->cd_inverted)
1134 return !value;
1135 return value;
1136 }
1137
1138 static int omap_hsmmc_getwp(struct udevice *dev)
1139 {
1140 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1141 int value;
1142
1143 value = dm_gpio_get_value(&priv->wp_gpio);
1144 /* if no WP return as 0 */
1145 if (value < 0)
1146 return 0;
1147 return value;
1148 }
1149 #else
1150 static int omap_hsmmc_getcd(struct mmc *mmc)
1151 {
1152 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1153 int cd_gpio;
1154
1155 /* if no CD return as 1 */
1156 cd_gpio = priv->cd_gpio;
1157 if (cd_gpio < 0)
1158 return 1;
1159
1160 /* NOTE: assumes card detect signal is active-low */
1161 return !gpio_get_value(cd_gpio);
1162 }
1163
1164 static int omap_hsmmc_getwp(struct mmc *mmc)
1165 {
1166 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1167 int wp_gpio;
1168
1169 /* if no WP return as 0 */
1170 wp_gpio = priv->wp_gpio;
1171 if (wp_gpio < 0)
1172 return 0;
1173
1174 /* NOTE: assumes write protect signal is active-high */
1175 return gpio_get_value(wp_gpio);
1176 }
1177 #endif
1178 #endif
1179
1180 #if CONFIG_IS_ENABLED(DM_MMC)
1181 static const struct dm_mmc_ops omap_hsmmc_ops = {
1182 .send_cmd = omap_hsmmc_send_cmd,
1183 .set_ios = omap_hsmmc_set_ios,
1184 #ifdef OMAP_HSMMC_USE_GPIO
1185 .get_cd = omap_hsmmc_getcd,
1186 .get_wp = omap_hsmmc_getwp,
1187 #endif
1188 #ifdef MMC_SUPPORTS_TUNING
1189 .execute_tuning = omap_hsmmc_execute_tuning,
1190 #endif
1191 };
1192 #else
1193 static const struct mmc_ops omap_hsmmc_ops = {
1194 .send_cmd = omap_hsmmc_send_cmd,
1195 .set_ios = omap_hsmmc_set_ios,
1196 .init = omap_hsmmc_init_setup,
1197 #ifdef OMAP_HSMMC_USE_GPIO
1198 .getcd = omap_hsmmc_getcd,
1199 .getwp = omap_hsmmc_getwp,
1200 #endif
1201 };
1202 #endif
1203
1204 #if !CONFIG_IS_ENABLED(DM_MMC)
1205 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1206 int wp_gpio)
1207 {
1208 struct mmc *mmc;
1209 struct omap_hsmmc_data *priv;
1210 struct mmc_config *cfg;
1211 uint host_caps_val;
1212
1213 priv = malloc(sizeof(*priv));
1214 if (priv == NULL)
1215 return -1;
1216
1217 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1218
1219 switch (dev_index) {
1220 case 0:
1221 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1222 break;
1223 #ifdef OMAP_HSMMC2_BASE
1224 case 1:
1225 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1226 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1227 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1228 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1229 defined(CONFIG_HSMMC2_8BIT)
1230 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1231 host_caps_val |= MMC_MODE_8BIT;
1232 #endif
1233 break;
1234 #endif
1235 #ifdef OMAP_HSMMC3_BASE
1236 case 2:
1237 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1238 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1239 /* Enable 8-bit interface for eMMC on DRA7XX */
1240 host_caps_val |= MMC_MODE_8BIT;
1241 #endif
1242 break;
1243 #endif
1244 default:
1245 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1246 return 1;
1247 }
1248 #ifdef OMAP_HSMMC_USE_GPIO
1249 /* on error gpio values are set to -1, which is what we want */
1250 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1251 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1252 #endif
1253
1254 cfg = &priv->cfg;
1255
1256 cfg->name = "OMAP SD/MMC";
1257 cfg->ops = &omap_hsmmc_ops;
1258
1259 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1260 cfg->host_caps = host_caps_val & ~host_caps_mask;
1261
1262 cfg->f_min = 400000;
1263
1264 if (f_max != 0)
1265 cfg->f_max = f_max;
1266 else {
1267 if (cfg->host_caps & MMC_MODE_HS) {
1268 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1269 cfg->f_max = 52000000;
1270 else
1271 cfg->f_max = 26000000;
1272 } else
1273 cfg->f_max = 20000000;
1274 }
1275
1276 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1277
1278 #if defined(CONFIG_OMAP34XX)
1279 /*
1280 * Silicon revs 2.1 and older do not support multiblock transfers.
1281 */
1282 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1283 cfg->b_max = 1;
1284 #endif
1285 mmc = mmc_create(cfg, priv);
1286 if (mmc == NULL)
1287 return -1;
1288
1289 return 0;
1290 }
1291 #else
1292 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1293 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1294 {
1295 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1296 struct mmc_config *cfg = &plat->cfg;
1297 const void *fdt = gd->fdt_blob;
1298 int node = dev_of_offset(dev);
1299 int val;
1300
1301 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1302 sizeof(struct hsmmc *),
1303 MAP_NOCACHE);
1304
1305 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
1306 val = fdtdec_get_int(fdt, node, "bus-width", -1);
1307 if (val < 0) {
1308 printf("error: bus-width property missing\n");
1309 return -ENOENT;
1310 }
1311
1312 switch (val) {
1313 case 0x8:
1314 cfg->host_caps |= MMC_MODE_8BIT;
1315 case 0x4:
1316 cfg->host_caps |= MMC_MODE_4BIT;
1317 break;
1318 default:
1319 printf("error: invalid bus-width property\n");
1320 return -ENOENT;
1321 }
1322
1323 cfg->f_min = 400000;
1324 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
1325 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1326 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1327 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1328 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1329 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1330 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1331
1332 #ifdef OMAP_HSMMC_USE_GPIO
1333 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1334 #endif
1335
1336 return 0;
1337 }
1338 #endif
1339
1340 #ifdef CONFIG_BLK
1341
1342 static int omap_hsmmc_bind(struct udevice *dev)
1343 {
1344 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1345
1346 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1347 }
1348 #endif
1349 static int omap_hsmmc_probe(struct udevice *dev)
1350 {
1351 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1352 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1353 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1354 struct mmc_config *cfg = &plat->cfg;
1355 struct mmc *mmc;
1356
1357 cfg->name = "OMAP SD/MMC";
1358 priv->base_addr = plat->base_addr;
1359 #ifdef OMAP_HSMMC_USE_GPIO
1360 priv->cd_inverted = plat->cd_inverted;
1361 #endif
1362
1363 #ifdef CONFIG_BLK
1364 mmc = &plat->mmc;
1365 #else
1366 mmc = mmc_create(cfg, priv);
1367 if (mmc == NULL)
1368 return -1;
1369 #endif
1370
1371 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1372 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1373 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1374 #endif
1375
1376 mmc->dev = dev;
1377 upriv->mmc = mmc;
1378
1379 return omap_hsmmc_init_setup(mmc);
1380 }
1381
1382 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1383 static const struct udevice_id omap_hsmmc_ids[] = {
1384 { .compatible = "ti,omap3-hsmmc" },
1385 { .compatible = "ti,omap4-hsmmc" },
1386 { .compatible = "ti,am33xx-hsmmc" },
1387 { }
1388 };
1389 #endif
1390
1391 U_BOOT_DRIVER(omap_hsmmc) = {
1392 .name = "omap_hsmmc",
1393 .id = UCLASS_MMC,
1394 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1395 .of_match = omap_hsmmc_ids,
1396 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1397 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1398 #endif
1399 #ifdef CONFIG_BLK
1400 .bind = omap_hsmmc_bind,
1401 #endif
1402 .ops = &omap_hsmmc_ops,
1403 .probe = omap_hsmmc_probe,
1404 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1405 .flags = DM_FLAG_PRE_RELOC,
1406 };
1407 #endif
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