3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
35 #include <asm/arch/mmc_host_def.h>
36 #if !defined(CONFIG_SOC_KEYSTONE)
38 #include <asm/arch/sys_proto.h>
40 #ifdef CONFIG_MMC_OMAP36XX_PINS
41 #include <asm/arch/mux.h>
45 DECLARE_GLOBAL_DATA_PTR
;
47 /* simplify defines to OMAP_HSMMC_USE_GPIO */
48 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
49 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
50 #define OMAP_HSMMC_USE_GPIO
52 #undef OMAP_HSMMC_USE_GPIO
55 /* common definitions for all OMAPs */
56 #define SYSCTL_SRC (1 << 25)
57 #define SYSCTL_SRD (1 << 26)
59 struct omap_hsmmc_data
{
60 struct hsmmc
*base_addr
;
61 #if !CONFIG_IS_ENABLED(DM_MMC)
62 struct mmc_config cfg
;
64 #ifdef OMAP_HSMMC_USE_GPIO
65 #if CONFIG_IS_ENABLED(DM_MMC)
66 struct gpio_desc cd_gpio
; /* Change Detect GPIO */
67 struct gpio_desc wp_gpio
; /* Write Protect GPIO */
76 /* If we fail after 1 second wait, something is really bad */
77 #define MAX_RETRY_MS 1000
79 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
);
80 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
83 static inline struct omap_hsmmc_data
*omap_hsmmc_get_data(struct mmc
*mmc
)
85 #if CONFIG_IS_ENABLED(DM_MMC)
86 return dev_get_priv(mmc
->dev
);
88 return (struct omap_hsmmc_data
*)mmc
->priv
;
91 static inline struct mmc_config
*omap_hsmmc_get_cfg(struct mmc
*mmc
)
93 #if CONFIG_IS_ENABLED(DM_MMC)
94 struct omap_hsmmc_plat
*plat
= dev_get_platdata(mmc
->dev
);
97 return &((struct omap_hsmmc_data
*)mmc
->priv
)->cfg
;
101 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
102 static int omap_mmc_setup_gpio_in(int gpio
, const char *label
)
106 #ifndef CONFIG_DM_GPIO
107 if (!gpio_is_valid(gpio
))
110 ret
= gpio_request(gpio
, label
);
114 ret
= gpio_direction_input(gpio
);
122 static unsigned char mmc_board_init(struct mmc
*mmc
)
124 #if defined(CONFIG_OMAP34XX)
125 struct mmc_config
*cfg
= omap_hsmmc_get_cfg(mmc
);
126 t2_t
*t2_base
= (t2_t
*)T2_BASE
;
127 struct prcm
*prcm_base
= (struct prcm
*)PRCM_BASE
;
129 #ifdef CONFIG_MMC_OMAP36XX_PINS
130 u32 wkup_ctrl
= readl(OMAP34XX_CTRL_WKUP_CTRL
);
133 pbias_lite
= readl(&t2_base
->pbias_lite
);
134 pbias_lite
&= ~(PBIASLITEPWRDNZ1
| PBIASLITEPWRDNZ0
);
135 #ifdef CONFIG_TARGET_OMAP3_CAIRO
136 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
137 pbias_lite
&= ~PBIASLITEVMODE0
;
139 #ifdef CONFIG_MMC_OMAP36XX_PINS
140 if (get_cpu_family() == CPU_OMAP36XX
) {
141 /* Disable extended drain IO before changing PBIAS */
142 wkup_ctrl
&= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ
;
143 writel(wkup_ctrl
, OMAP34XX_CTRL_WKUP_CTRL
);
146 writel(pbias_lite
, &t2_base
->pbias_lite
);
148 writel(pbias_lite
| PBIASLITEPWRDNZ1
|
149 PBIASSPEEDCTRL0
| PBIASLITEPWRDNZ0
,
150 &t2_base
->pbias_lite
);
152 #ifdef CONFIG_MMC_OMAP36XX_PINS
153 if (get_cpu_family() == CPU_OMAP36XX
)
154 /* Enable extended drain IO after changing PBIAS */
156 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ
,
157 OMAP34XX_CTRL_WKUP_CTRL
);
159 writel(readl(&t2_base
->devconf0
) | MMCSDIO1ADPCLKISEL
,
162 writel(readl(&t2_base
->devconf1
) | MMCSDIO2ADPCLKISEL
,
165 /* Change from default of 52MHz to 26MHz if necessary */
166 if (!(cfg
->host_caps
& MMC_MODE_HS_52MHz
))
167 writel(readl(&t2_base
->ctl_prog_io1
) & ~CTLPROGIO1SPEEDCTRL
,
168 &t2_base
->ctl_prog_io1
);
170 writel(readl(&prcm_base
->fclken1_core
) |
171 EN_MMC1
| EN_MMC2
| EN_MMC3
,
172 &prcm_base
->fclken1_core
);
174 writel(readl(&prcm_base
->iclken1_core
) |
175 EN_MMC1
| EN_MMC2
| EN_MMC3
,
176 &prcm_base
->iclken1_core
);
179 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
180 /* PBIAS config needed for MMC1 only */
181 if (mmc_get_blk_desc(mmc
)->devnum
== 0)
182 vmmc_pbias_config(LDO_VOLT_3V0
);
188 void mmc_init_stream(struct hsmmc
*mmc_base
)
192 writel(readl(&mmc_base
->con
) | INIT_INITSTREAM
, &mmc_base
->con
);
194 writel(MMC_CMD0
, &mmc_base
->cmd
);
195 start
= get_timer(0);
196 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
197 if (get_timer(0) - start
> MAX_RETRY_MS
) {
198 printf("%s: timedout waiting for cc!\n", __func__
);
202 writel(CC_MASK
, &mmc_base
->stat
)
204 writel(MMC_CMD0
, &mmc_base
->cmd
)
206 start
= get_timer(0);
207 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
208 if (get_timer(0) - start
> MAX_RETRY_MS
) {
209 printf("%s: timedout waiting for cc2!\n", __func__
);
213 writel(readl(&mmc_base
->con
) & ~INIT_INITSTREAM
, &mmc_base
->con
);
216 static int omap_hsmmc_init_setup(struct mmc
*mmc
)
218 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
219 struct hsmmc
*mmc_base
;
220 unsigned int reg_val
;
224 mmc_base
= priv
->base_addr
;
227 writel(readl(&mmc_base
->sysconfig
) | MMC_SOFTRESET
,
228 &mmc_base
->sysconfig
);
229 start
= get_timer(0);
230 while ((readl(&mmc_base
->sysstatus
) & RESETDONE
) == 0) {
231 if (get_timer(0) - start
> MAX_RETRY_MS
) {
232 printf("%s: timedout waiting for cc2!\n", __func__
);
236 writel(readl(&mmc_base
->sysctl
) | SOFTRESETALL
, &mmc_base
->sysctl
);
237 start
= get_timer(0);
238 while ((readl(&mmc_base
->sysctl
) & SOFTRESETALL
) != 0x0) {
239 if (get_timer(0) - start
> MAX_RETRY_MS
) {
240 printf("%s: timedout waiting for softresetall!\n",
245 writel(DTW_1_BITMODE
| SDBP_PWROFF
| SDVS_3V0
, &mmc_base
->hctl
);
246 writel(readl(&mmc_base
->capa
) | VS30_3V0SUP
| VS18_1V8SUP
,
249 reg_val
= readl(&mmc_base
->con
) & RESERVED_MASK
;
251 writel(CTPL_MMC_SD
| reg_val
| WPP_ACTIVEHIGH
| CDP_ACTIVEHIGH
|
252 MIT_CTO
| DW8_1_4BITMODE
| MODE_FUNC
| STR_BLOCK
|
253 HR_NOHOSTRESP
| INIT_NOINIT
| NOOPENDRAIN
, &mmc_base
->con
);
256 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
257 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
258 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
259 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
260 start
= get_timer(0);
261 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
262 if (get_timer(0) - start
> MAX_RETRY_MS
) {
263 printf("%s: timedout waiting for ics!\n", __func__
);
267 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
269 writel(readl(&mmc_base
->hctl
) | SDBP_PWRON
, &mmc_base
->hctl
);
271 writel(IE_BADA
| IE_CERR
| IE_DEB
| IE_DCRC
| IE_DTO
| IE_CIE
|
272 IE_CEB
| IE_CCRC
| IE_CTO
| IE_BRR
| IE_BWR
| IE_TC
| IE_CC
,
275 mmc_init_stream(mmc_base
);
281 * MMC controller internal finite state machine reset
283 * Used to reset command or data internal state machines, using respectively
284 * SRC or SRD bit of SYSCTL register
286 static void mmc_reset_controller_fsm(struct hsmmc
*mmc_base
, u32 bit
)
290 mmc_reg_out(&mmc_base
->sysctl
, bit
, bit
);
293 * CMD(DAT) lines reset procedures are slightly different
294 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
295 * According to OMAP3 TRM:
296 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
298 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
299 * procedure steps must be as follows:
300 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
301 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
302 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
303 * 3. Wait until the SRC (SRD) bit returns to 0x0
304 * (reset procedure is completed).
306 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
307 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
308 if (!(readl(&mmc_base
->sysctl
) & bit
)) {
309 start
= get_timer(0);
310 while (!(readl(&mmc_base
->sysctl
) & bit
)) {
311 if (get_timer(0) - start
> MAX_RETRY_MS
)
316 start
= get_timer(0);
317 while ((readl(&mmc_base
->sysctl
) & bit
) != 0) {
318 if (get_timer(0) - start
> MAX_RETRY_MS
) {
319 printf("%s: timedout waiting for sysctl %x to clear\n",
325 #if !CONFIG_IS_ENABLED(DM_MMC)
326 static int omap_hsmmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
327 struct mmc_data
*data
)
329 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
331 static int omap_hsmmc_send_cmd(struct udevice
*dev
, struct mmc_cmd
*cmd
,
332 struct mmc_data
*data
)
334 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
336 struct hsmmc
*mmc_base
;
337 unsigned int flags
, mmc_stat
;
340 mmc_base
= priv
->base_addr
;
341 start
= get_timer(0);
342 while ((readl(&mmc_base
->pstate
) & (DATI_MASK
| CMDI_MASK
)) != 0) {
343 if (get_timer(0) - start
> MAX_RETRY_MS
) {
344 printf("%s: timedout waiting on cmd inhibit to clear\n",
349 writel(0xFFFFFFFF, &mmc_base
->stat
);
350 start
= get_timer(0);
351 while (readl(&mmc_base
->stat
)) {
352 if (get_timer(0) - start
> MAX_RETRY_MS
) {
353 printf("%s: timedout waiting for STAT (%x) to clear\n",
354 __func__
, readl(&mmc_base
->stat
));
360 * CMDIDX[13:8] : Command index
361 * DATAPRNT[5] : Data Present Select
362 * ENCMDIDX[4] : Command Index Check Enable
363 * ENCMDCRC[3] : Command CRC Check Enable
368 * 11 = Length 48 Check busy after response
370 /* Delay added before checking the status of frq change
371 * retry not supported by mmc.c(core file)
373 if (cmd
->cmdidx
== SD_CMD_APP_SEND_SCR
)
374 udelay(50000); /* wait 50 ms */
376 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
378 else if (cmd
->resp_type
& MMC_RSP_136
)
379 flags
= RSP_TYPE_LGHT136
| CICE_NOCHECK
;
380 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
381 flags
= RSP_TYPE_LGHT48B
;
383 flags
= RSP_TYPE_LGHT48
;
385 /* enable default flags */
386 flags
= flags
| (CMD_TYPE_NORMAL
| CICE_NOCHECK
| CCCE_NOCHECK
|
387 MSBS_SGLEBLK
| ACEN_DISABLE
| BCE_DISABLE
| DE_DISABLE
);
389 if (cmd
->resp_type
& MMC_RSP_CRC
)
391 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
395 if ((cmd
->cmdidx
== MMC_CMD_READ_MULTIPLE_BLOCK
) ||
396 (cmd
->cmdidx
== MMC_CMD_WRITE_MULTIPLE_BLOCK
)) {
397 flags
|= (MSBS_MULTIBLK
| BCE_ENABLE
);
398 data
->blocksize
= 512;
399 writel(data
->blocksize
| (data
->blocks
<< 16),
402 writel(data
->blocksize
| NBLK_STPCNT
, &mmc_base
->blk
);
404 if (data
->flags
& MMC_DATA_READ
)
405 flags
|= (DP_DATA
| DDIR_READ
);
407 flags
|= (DP_DATA
| DDIR_WRITE
);
410 writel(cmd
->cmdarg
, &mmc_base
->arg
);
411 udelay(20); /* To fix "No status update" error on eMMC */
412 writel((cmd
->cmdidx
<< 24) | flags
, &mmc_base
->cmd
);
414 start
= get_timer(0);
416 mmc_stat
= readl(&mmc_base
->stat
);
417 if (get_timer(0) - start
> MAX_RETRY_MS
) {
418 printf("%s : timeout: No status update\n", __func__
);
423 if ((mmc_stat
& IE_CTO
) != 0) {
424 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRC
);
426 } else if ((mmc_stat
& ERRI_MASK
) != 0)
429 if (mmc_stat
& CC_MASK
) {
430 writel(CC_MASK
, &mmc_base
->stat
);
431 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
432 if (cmd
->resp_type
& MMC_RSP_136
) {
433 /* response type 2 */
434 cmd
->response
[3] = readl(&mmc_base
->rsp10
);
435 cmd
->response
[2] = readl(&mmc_base
->rsp32
);
436 cmd
->response
[1] = readl(&mmc_base
->rsp54
);
437 cmd
->response
[0] = readl(&mmc_base
->rsp76
);
439 /* response types 1, 1b, 3, 4, 5, 6 */
440 cmd
->response
[0] = readl(&mmc_base
->rsp10
);
444 if (data
&& (data
->flags
& MMC_DATA_READ
)) {
445 mmc_read_data(mmc_base
, data
->dest
,
446 data
->blocksize
* data
->blocks
);
447 } else if (data
&& (data
->flags
& MMC_DATA_WRITE
)) {
448 mmc_write_data(mmc_base
, data
->src
,
449 data
->blocksize
* data
->blocks
);
454 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
)
456 unsigned int *output_buf
= (unsigned int *)buf
;
457 unsigned int mmc_stat
;
463 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
467 ulong start
= get_timer(0);
469 mmc_stat
= readl(&mmc_base
->stat
);
470 if (get_timer(0) - start
> MAX_RETRY_MS
) {
471 printf("%s: timedout waiting for status!\n",
475 } while (mmc_stat
== 0);
477 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
478 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
480 if ((mmc_stat
& ERRI_MASK
) != 0)
483 if (mmc_stat
& BRR_MASK
) {
486 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
488 for (k
= 0; k
< count
; k
++) {
489 *output_buf
= readl(&mmc_base
->data
);
495 if (mmc_stat
& BWR_MASK
)
496 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
499 if (mmc_stat
& TC_MASK
) {
500 writel(readl(&mmc_base
->stat
) | TC_MASK
,
508 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
511 unsigned int *input_buf
= (unsigned int *)buf
;
512 unsigned int mmc_stat
;
518 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
522 ulong start
= get_timer(0);
524 mmc_stat
= readl(&mmc_base
->stat
);
525 if (get_timer(0) - start
> MAX_RETRY_MS
) {
526 printf("%s: timedout waiting for status!\n",
530 } while (mmc_stat
== 0);
532 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
533 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
535 if ((mmc_stat
& ERRI_MASK
) != 0)
538 if (mmc_stat
& BWR_MASK
) {
541 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
543 for (k
= 0; k
< count
; k
++) {
544 writel(*input_buf
, &mmc_base
->data
);
550 if (mmc_stat
& BRR_MASK
)
551 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
554 if (mmc_stat
& TC_MASK
) {
555 writel(readl(&mmc_base
->stat
) | TC_MASK
,
563 #if !CONFIG_IS_ENABLED(DM_MMC)
564 static int omap_hsmmc_set_ios(struct mmc
*mmc
)
566 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
568 static int omap_hsmmc_set_ios(struct udevice
*dev
)
570 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
571 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
572 struct mmc
*mmc
= upriv
->mmc
;
574 struct hsmmc
*mmc_base
;
575 unsigned int dsor
= 0;
578 mmc_base
= priv
->base_addr
;
579 /* configue bus width */
580 switch (mmc
->bus_width
) {
582 writel(readl(&mmc_base
->con
) | DTW_8_BITMODE
,
587 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
589 writel(readl(&mmc_base
->hctl
) | DTW_4_BITMODE
,
595 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
597 writel(readl(&mmc_base
->hctl
) & ~DTW_4_BITMODE
,
602 /* configure clock with 96Mhz system clock.
604 if (mmc
->clock
!= 0) {
605 dsor
= (MMC_CLOCK_REFERENCE
* 1000000 / mmc
->clock
);
606 if ((MMC_CLOCK_REFERENCE
* 1000000) / dsor
> mmc
->clock
)
610 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
611 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
613 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
614 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
616 start
= get_timer(0);
617 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
618 if (get_timer(0) - start
> MAX_RETRY_MS
) {
619 printf("%s: timedout waiting for ics!\n", __func__
);
623 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
628 #ifdef OMAP_HSMMC_USE_GPIO
629 #if CONFIG_IS_ENABLED(DM_MMC)
630 static int omap_hsmmc_getcd(struct udevice
*dev
)
632 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
635 value
= dm_gpio_get_value(&priv
->cd_gpio
);
636 /* if no CD return as 1 */
640 if (priv
->cd_inverted
)
645 static int omap_hsmmc_getwp(struct udevice
*dev
)
647 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
650 value
= dm_gpio_get_value(&priv
->wp_gpio
);
651 /* if no WP return as 0 */
657 static int omap_hsmmc_getcd(struct mmc
*mmc
)
659 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
662 /* if no CD return as 1 */
663 cd_gpio
= priv
->cd_gpio
;
667 /* NOTE: assumes card detect signal is active-low */
668 return !gpio_get_value(cd_gpio
);
671 static int omap_hsmmc_getwp(struct mmc
*mmc
)
673 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
676 /* if no WP return as 0 */
677 wp_gpio
= priv
->wp_gpio
;
681 /* NOTE: assumes write protect signal is active-high */
682 return gpio_get_value(wp_gpio
);
687 #if CONFIG_IS_ENABLED(DM_MMC)
688 static const struct dm_mmc_ops omap_hsmmc_ops
= {
689 .send_cmd
= omap_hsmmc_send_cmd
,
690 .set_ios
= omap_hsmmc_set_ios
,
691 #ifdef OMAP_HSMMC_USE_GPIO
692 .get_cd
= omap_hsmmc_getcd
,
693 .get_wp
= omap_hsmmc_getwp
,
697 static const struct mmc_ops omap_hsmmc_ops
= {
698 .send_cmd
= omap_hsmmc_send_cmd
,
699 .set_ios
= omap_hsmmc_set_ios
,
700 .init
= omap_hsmmc_init_setup
,
701 #ifdef OMAP_HSMMC_USE_GPIO
702 .getcd
= omap_hsmmc_getcd
,
703 .getwp
= omap_hsmmc_getwp
,
708 #if !CONFIG_IS_ENABLED(DM_MMC)
709 int omap_mmc_init(int dev_index
, uint host_caps_mask
, uint f_max
, int cd_gpio
,
713 struct omap_hsmmc_data
*priv
;
714 struct mmc_config
*cfg
;
717 priv
= malloc(sizeof(*priv
));
721 host_caps_val
= MMC_MODE_4BIT
| MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
725 priv
->base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
727 #ifdef OMAP_HSMMC2_BASE
729 priv
->base_addr
= (struct hsmmc
*)OMAP_HSMMC2_BASE
;
730 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
731 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
732 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
733 defined(CONFIG_HSMMC2_8BIT)
734 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
735 host_caps_val
|= MMC_MODE_8BIT
;
739 #ifdef OMAP_HSMMC3_BASE
741 priv
->base_addr
= (struct hsmmc
*)OMAP_HSMMC3_BASE
;
742 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
743 /* Enable 8-bit interface for eMMC on DRA7XX */
744 host_caps_val
|= MMC_MODE_8BIT
;
749 priv
->base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
752 #ifdef OMAP_HSMMC_USE_GPIO
753 /* on error gpio values are set to -1, which is what we want */
754 priv
->cd_gpio
= omap_mmc_setup_gpio_in(cd_gpio
, "mmc_cd");
755 priv
->wp_gpio
= omap_mmc_setup_gpio_in(wp_gpio
, "mmc_wp");
760 cfg
->name
= "OMAP SD/MMC";
761 cfg
->ops
= &omap_hsmmc_ops
;
763 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
764 cfg
->host_caps
= host_caps_val
& ~host_caps_mask
;
771 if (cfg
->host_caps
& MMC_MODE_HS
) {
772 if (cfg
->host_caps
& MMC_MODE_HS_52MHz
)
773 cfg
->f_max
= 52000000;
775 cfg
->f_max
= 26000000;
777 cfg
->f_max
= 20000000;
780 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
782 #if defined(CONFIG_OMAP34XX)
784 * Silicon revs 2.1 and older do not support multiblock transfers.
786 if ((get_cpu_family() == CPU_OMAP34XX
) && (get_cpu_rev() <= CPU_3XX_ES21
))
789 mmc
= mmc_create(cfg
, priv
);
796 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
797 static int omap_hsmmc_ofdata_to_platdata(struct udevice
*dev
)
799 struct omap_hsmmc_plat
*plat
= dev_get_platdata(dev
);
800 struct mmc_config
*cfg
= &plat
->cfg
;
801 const void *fdt
= gd
->fdt_blob
;
802 int node
= dev_of_offset(dev
);
805 plat
->base_addr
= map_physmem(devfdt_get_addr(dev
),
806 sizeof(struct hsmmc
*),
809 cfg
->host_caps
= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
810 val
= fdtdec_get_int(fdt
, node
, "bus-width", -1);
812 printf("error: bus-width property missing\n");
818 cfg
->host_caps
|= MMC_MODE_8BIT
;
820 cfg
->host_caps
|= MMC_MODE_4BIT
;
823 printf("error: invalid bus-width property\n");
828 cfg
->f_max
= fdtdec_get_int(fdt
, node
, "max-frequency", 52000000);
829 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
830 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
832 #ifdef OMAP_HSMMC_USE_GPIO
833 plat
->cd_inverted
= fdtdec_get_bool(fdt
, node
, "cd-inverted");
842 static int omap_hsmmc_bind(struct udevice
*dev
)
844 struct omap_hsmmc_plat
*plat
= dev_get_platdata(dev
);
846 return mmc_bind(dev
, &plat
->mmc
, &plat
->cfg
);
849 static int omap_hsmmc_probe(struct udevice
*dev
)
851 struct omap_hsmmc_plat
*plat
= dev_get_platdata(dev
);
852 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
853 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
854 struct mmc_config
*cfg
= &plat
->cfg
;
857 cfg
->name
= "OMAP SD/MMC";
858 priv
->base_addr
= plat
->base_addr
;
859 #ifdef OMAP_HSMMC_USE_GPIO
860 priv
->cd_inverted
= plat
->cd_inverted
;
866 mmc
= mmc_create(cfg
, priv
);
871 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
872 gpio_request_by_name(dev
, "cd-gpios", 0, &priv
->cd_gpio
, GPIOD_IS_IN
);
873 gpio_request_by_name(dev
, "wp-gpios", 0, &priv
->wp_gpio
, GPIOD_IS_IN
);
879 return omap_hsmmc_init_setup(mmc
);
882 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
883 static const struct udevice_id omap_hsmmc_ids
[] = {
884 { .compatible
= "ti,omap3-hsmmc" },
885 { .compatible
= "ti,omap4-hsmmc" },
886 { .compatible
= "ti,am33xx-hsmmc" },
891 U_BOOT_DRIVER(omap_hsmmc
) = {
892 .name
= "omap_hsmmc",
894 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
895 .of_match
= omap_hsmmc_ids
,
896 .ofdata_to_platdata
= omap_hsmmc_ofdata_to_platdata
,
897 .platdata_auto_alloc_size
= sizeof(struct omap_hsmmc_plat
),
900 .bind
= omap_hsmmc_bind
,
902 .ops
= &omap_hsmmc_ops
,
903 .probe
= omap_hsmmc_probe
,
904 .priv_auto_alloc_size
= sizeof(struct omap_hsmmc_data
),
905 .flags
= DM_FLAG_PRE_RELOC
,