drivers/mmc/s5p_mmc.c

   1 /*
   2  * (C) Copyright 2009 SAMSUNG Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  * Jaehoon Chung <jh80.chung@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 #include <common.h>
  22 #include <mmc.h>
  23 #include <asm/io.h>
  24 #include <asm/arch/mmc.h>
  25
  26 /* support 4 mmc hosts */
  27 struct mmc mmc_dev[4];
  28 struct mmc_host mmc_host[4];
  29
  30 static inline struct s5p_mmc *s5p_get_base_mmc(int dev_index)
  31 {
  32         unsigned long offset = dev_index * sizeof(struct s5p_mmc);
  33         return (struct s5p_mmc *)(samsung_get_base_mmc() + offset);
  34 }
  35
  36 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
  37 {
  38         unsigned char ctrl;
  39
  40         debug("data->dest: %08x\n", (u32)data->dest);
  41         writel((u32)data->dest, &host->reg->sysad);
  42         /*
  43          * DMASEL[4:3]
  44          * 00 = Selects SDMA
  45          * 01 = Reserved
  46          * 10 = Selects 32-bit Address ADMA2
  47          * 11 = Selects 64-bit Address ADMA2
  48          */
  49         ctrl = readb(&host->reg->hostctl);
  50         ctrl &= ~(3 << 3);
  51         writeb(ctrl, &host->reg->hostctl);
  52
  53         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  54         writew((7 << 12) | (512 << 0), &host->reg->blksize);
  55         writew(data->blocks, &host->reg->blkcnt);
  56 }
  57
  58 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
  59 {
  60         unsigned short mode;
  61
  62         /*
  63          * TRNMOD
  64          * MUL1SIN0[5]  : Multi/Single Block Select
  65          * RD1WT0[4]    : Data Transfer Direction Select
  66          *      1 = read
  67          *      0 = write
  68          * ENACMD12[2]  : Auto CMD12 Enable
  69          * ENBLKCNT[1]  : Block Count Enable
  70          * ENDMA[0]     : DMA Enable
  71          */
  72         mode = (1 << 1) | (1 << 0);
  73         if (data->blocks > 1)
  74                 mode |= (1 << 5);
  75         if (data->flags & MMC_DATA_READ)
  76                 mode |= (1 << 4);
  77
  78         writew(mode, &host->reg->trnmod);
  79 }
  80
  81 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  82                         struct mmc_data *data)
  83 {
  84         struct mmc_host *host = (struct mmc_host *)mmc->priv;
  85         int flags, i;
  86         unsigned int timeout;
  87         unsigned int mask;
  88         unsigned int retry = 0x100000;
  89
  90         /* Wait max 10 ms */
  91         timeout = 10;
  92
  93         /*
  94          * PRNSTS
  95          * CMDINHDAT[1] : Command Inhibit (DAT)
  96          * CMDINHCMD[0] : Command Inhibit (CMD)
  97          */
  98         mask = (1 << 0);
  99         if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
 100                 mask |= (1 << 1);
 101
 102         /*
 103          * We shouldn't wait for data inihibit for stop commands, even
 104          * though they might use busy signaling
 105          */
 106         if (data)
 107                 mask &= ~(1 << 1);
 108
 109         while (readl(&host->reg->prnsts) & mask) {
 110                 if (timeout == 0) {
 111                         printf("%s: timeout error\n", __func__);
 112                         return -1;
 113                 }
 114                 timeout--;
 115                 udelay(1000);
 116         }
 117
 118         if (data)
 119                 mmc_prepare_data(host, data);
 120
 121         debug("cmd->arg: %08x\n", cmd->cmdarg);
 122         writel(cmd->cmdarg, &host->reg->argument);
 123
 124         if (data)
 125                 mmc_set_transfer_mode(host, data);
 126
 127         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 128                 return -1;
 129
 130         /*
 131          * CMDREG
 132          * CMDIDX[13:8] : Command index
 133          * DATAPRNT[5]  : Data Present Select
 134          * ENCMDIDX[4]  : Command Index Check Enable
 135          * ENCMDCRC[3]  : Command CRC Check Enable
 136          * RSPTYP[1:0]
 137          *      00 = No Response
 138          *      01 = Length 136
 139          *      10 = Length 48
 140          *      11 = Length 48 Check busy after response
 141          */
 142         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 143                 flags = 0;
 144         else if (cmd->resp_type & MMC_RSP_136)
 145                 flags = (1 << 0);
 146         else if (cmd->resp_type & MMC_RSP_BUSY)
 147                 flags = (3 << 0);
 148         else
 149                 flags = (2 << 0);
 150
 151         if (cmd->resp_type & MMC_RSP_CRC)
 152                 flags |= (1 << 3);
 153         if (cmd->resp_type & MMC_RSP_OPCODE)
 154                 flags |= (1 << 4);
 155         if (data)
 156                 flags |= (1 << 5);
 157
 158         debug("cmd: %d\n", cmd->cmdidx);
 159
 160         writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
 161
 162         for (i = 0; i < retry; i++) {
 163                 mask = readl(&host->reg->norintsts);
 164                 /* Command Complete */
 165                 if (mask & (1 << 0)) {
 166                         if (!data)
 167                                 writel(mask, &host->reg->norintsts);
 168                         break;
 169                 }
 170         }
 171
 172         if (i == retry) {
 173                 printf("%s: waiting for status update\n", __func__);
 174                 return TIMEOUT;
 175         }
 176
 177         if (mask & (1 << 16)) {
 178                 /* Timeout Error */
 179                 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
 180                 return TIMEOUT;
 181         } else if (mask & (1 << 15)) {
 182                 /* Error Interrupt */
 183                 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
 184                 return -1;
 185         }
 186
 187         if (cmd->resp_type & MMC_RSP_PRESENT) {
 188                 if (cmd->resp_type & MMC_RSP_136) {
 189                         /* CRC is stripped so we need to do some shifting. */
 190                         for (i = 0; i < 4; i++) {
 191                                 unsigned int offset =
 192                                         (unsigned int)(&host->reg->rspreg3 - i);
 193                                 cmd->response[i] = readl(offset) << 8;
 194
 195                                 if (i != 3) {
 196                                         cmd->response[i] |=
 197                                                 readb(offset - 1);
 198                                 }
 199                                 debug("cmd->resp[%d]: %08x\n",
 200                                                 i, cmd->response[i]);
 201                         }
 202                 } else if (cmd->resp_type & MMC_RSP_BUSY) {
 203                         for (i = 0; i < retry; i++) {
 204                                 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
 205                                 if (readl(&host->reg->prnsts)
 206                                         & (1 << 20))    /* DAT[0] */
 207                                         break;
 208                         }
 209
 210                         if (i == retry) {
 211                                 printf("%s: card is still busy\n", __func__);
 212                                 return TIMEOUT;
 213                         }
 214
 215                         cmd->response[0] = readl(&host->reg->rspreg0);
 216                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 217                 } else {
 218                         cmd->response[0] = readl(&host->reg->rspreg0);
 219                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 220                 }
 221         }
 222
 223         if (data) {
 224                 while (1) {
 225                         mask = readl(&host->reg->norintsts);
 226
 227                         if (mask & (1 << 15)) {
 228                                 /* Error Interrupt */
 229                                 writel(mask, &host->reg->norintsts);
 230                                 printf("%s: error during transfer: 0x%08x\n",
 231                                                 __func__, mask);
 232                                 return -1;
 233                         } else if (mask & (1 << 3)) {
 234                                 /* DMA Interrupt */
 235                                 debug("DMA end\n");
 236                                 break;
 237                         } else if (mask & (1 << 1)) {
 238                                 /* Transfer Complete */
 239                                 debug("r/w is done\n");
 240                                 break;
 241                         }
 242                 }
 243                 writel(mask, &host->reg->norintsts);
 244         }
 245
 246         udelay(1000);
 247         return 0;
 248 }
 249
 250 static void mmc_change_clock(struct mmc_host *host, uint clock)
 251 {
 252         int div;
 253         unsigned short clk;
 254         unsigned long timeout;
 255         unsigned long ctrl2;
 256
 257         /*
 258          * SELBASECLK[5:4]
 259          * 00/01 = HCLK
 260          * 10 = EPLL
 261          * 11 = XTI or XEXTCLK
 262          */
 263         ctrl2 = readl(&host->reg->control2);
 264         ctrl2 &= ~(3 << 4);
 265         ctrl2 |= (2 << 4);
 266         writel(ctrl2, &host->reg->control2);
 267
 268         writew(0, &host->reg->clkcon);
 269
 270         /* XXX: we assume that clock is between 40MHz and 50MHz */
 271         if (clock == 0)
 272                 goto out;
 273         else if (clock <= 400000)
 274                 div = 0x100;
 275         else if (clock <= 20000000)
 276                 div = 4;
 277         else if (clock <= 26000000)
 278                 div = 2;
 279         else
 280                 div = 1;
 281         debug("div: %d\n", div);
 282
 283         div >>= 1;
 284         /*
 285          * CLKCON
 286          * SELFREQ[15:8]        : base clock divied by value
 287          * ENSDCLK[2]           : SD Clock Enable
 288          * STBLINTCLK[1]        : Internal Clock Stable
 289          * ENINTCLK[0]          : Internal Clock Enable
 290          */
 291         clk = (div << 8) | (1 << 0);
 292         writew(clk, &host->reg->clkcon);
 293
 294         /* Wait max 10 ms */
 295         timeout = 10;
 296         while (!(readw(&host->reg->clkcon) & (1 << 1))) {
 297                 if (timeout == 0) {
 298                         printf("%s: timeout error\n", __func__);
 299                         return;
 300                 }
 301                 timeout--;
 302                 udelay(1000);
 303         }
 304
 305         clk |= (1 << 2);
 306         writew(clk, &host->reg->clkcon);
 307
 308 out:
 309         host->clock = clock;
 310 }
 311
 312 static void mmc_set_ios(struct mmc *mmc)
 313 {
 314         struct mmc_host *host = mmc->priv;
 315         unsigned char ctrl;
 316         unsigned long val;
 317
 318         debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
 319
 320         /*
 321          * SELCLKPADDS[17:16]
 322          * 00 = 2mA
 323          * 01 = 4mA
 324          * 10 = 7mA
 325          * 11 = 9mA
 326          */
 327         writel(0x3 << 16, &host->reg->control4);
 328
 329         val = readl(&host->reg->control2);
 330         val &= (0x3 << 4);
 331
 332         val |=  (1 << 31) |     /* write status clear async mode enable */
 333                 (1 << 30) |     /* command conflict mask enable */
 334                 (1 << 14) |     /* Feedback Clock Enable for Rx Clock */
 335                 (1 << 8);       /* SDCLK hold enable */
 336
 337         writel(val, &host->reg->control2);
 338
 339         /*
 340          * FCSEL1[15] FCSEL0[7]
 341          * FCSel[1:0] : Rx Feedback Clock Delay Control
 342          *      Inverter delay means10ns delay if SDCLK 50MHz setting
 343          *      01 = Delay1 (basic delay)
 344          *      11 = Delay2 (basic delay + 2ns)
 345          *      00 = Delay3 (inverter delay)
 346          *      10 = Delay4 (inverter delay + 2ns)
 347          */
 348         writel(0x8080, &host->reg->control3);
 349
 350         mmc_change_clock(host, mmc->clock);
 351
 352         ctrl = readb(&host->reg->hostctl);
 353
 354         /*
 355          * WIDE4[1]
 356          * 1 = 4-bit mode
 357          * 0 = 1-bit mode
 358          */
 359         if (mmc->bus_width == 4)
 360                 ctrl |= (1 << 1);
 361         else
 362                 ctrl &= ~(1 << 1);
 363
 364         /*
 365          * OUTEDGEINV[2]
 366          * 1 = Riging edge output
 367          * 0 = Falling edge output
 368          */
 369         ctrl &= ~(1 << 2);
 370
 371         writeb(ctrl, &host->reg->hostctl);
 372 }
 373
 374 static void mmc_reset(struct mmc_host *host)
 375 {
 376         unsigned int timeout;
 377
 378         /*
 379          * RSTALL[0] : Software reset for all
 380          * 1 = reset
 381          * 0 = work
 382          */
 383         writeb((1 << 0), &host->reg->swrst);
 384
 385         host->clock = 0;
 386
 387         /* Wait max 100 ms */
 388         timeout = 100;
 389
 390         /* hw clears the bit when it's done */
 391         while (readb(&host->reg->swrst) & (1 << 0)) {
 392                 if (timeout == 0) {
 393                         printf("%s: timeout error\n", __func__);
 394                         return;
 395                 }
 396                 timeout--;
 397                 udelay(1000);
 398         }
 399 }
 400
 401 static int mmc_core_init(struct mmc *mmc)
 402 {
 403         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 404         unsigned int mask;
 405
 406         mmc_reset(host);
 407
 408         host->version = readw(&host->reg->hcver);
 409
 410         /* mask all */
 411         writel(0xffffffff, &host->reg->norintstsen);
 412         writel(0xffffffff, &host->reg->norintsigen);
 413
 414         writeb(0xe, &host->reg->timeoutcon);    /* TMCLK * 2^27 */
 415
 416         /*
 417          * NORMAL Interrupt Status Enable Register init
 418          * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
 419          * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
 420          * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
 421          * [0] ENSTACMDCMPLT : Command Complete Status Enable
 422         */
 423         mask = readl(&host->reg->norintstsen);
 424         mask &= ~(0xffff);
 425         mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
 426         writel(mask, &host->reg->norintstsen);
 427
 428         /*
 429          * NORMAL Interrupt Signal Enable Register init
 430          * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
 431          */
 432         mask = readl(&host->reg->norintsigen);
 433         mask &= ~(0xffff);
 434         mask |= (1 << 1);
 435         writel(mask, &host->reg->norintsigen);
 436
 437         return 0;
 438 }
 439
 440 static int s5p_mmc_initialize(int dev_index)
 441 {
 442         struct mmc *mmc;
 443
 444         mmc = &mmc_dev[dev_index];
 445
 446         sprintf(mmc->name, "SAMSUNG SD/MMC");
 447         mmc->priv = &mmc_host[dev_index];
 448         mmc->send_cmd = mmc_send_cmd;
 449         mmc->set_ios = mmc_set_ios;
 450         mmc->init = mmc_core_init;
 451
 452         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 453         mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
 454
 455         mmc->f_min = 400000;
 456         mmc->f_max = 52000000;
 457
 458         mmc_host[dev_index].clock = 0;
 459         mmc_host[dev_index].reg = s5p_get_base_mmc(dev_index);
 460         mmc_register(mmc);
 461
 462         return 0;
 463 }
 464
 465 int s5p_mmc_init(int dev_index)
 466 {
 467         return s5p_mmc_initialize(dev_index);
 468 }