2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
18 void *aligned_buffer
= (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
;
23 static void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
25 unsigned long timeout
;
29 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
30 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
32 printf("%s: Reset 0x%x never completed.\n",
41 static void sdhci_cmd_done(struct sdhci_host
*host
, struct mmc_cmd
*cmd
)
44 if (cmd
->resp_type
& MMC_RSP_136
) {
45 /* CRC is stripped so we need to do some shifting. */
46 for (i
= 0; i
< 4; i
++) {
47 cmd
->response
[i
] = sdhci_readl(host
,
48 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
50 cmd
->response
[i
] |= sdhci_readb(host
,
51 SDHCI_RESPONSE
+ (3-i
)*4-1);
54 cmd
->response
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
58 static void sdhci_transfer_pio(struct sdhci_host
*host
, struct mmc_data
*data
)
62 for (i
= 0; i
< data
->blocksize
; i
+= 4) {
63 offs
= data
->dest
+ i
;
64 if (data
->flags
== MMC_DATA_READ
)
65 *(u32
*)offs
= sdhci_readl(host
, SDHCI_BUFFER
);
67 sdhci_writel(host
, *(u32
*)offs
, SDHCI_BUFFER
);
71 static int sdhci_transfer_data(struct sdhci_host
*host
, struct mmc_data
*data
,
72 unsigned int start_addr
)
74 unsigned int stat
, rdy
, mask
, timeout
, block
= 0;
75 #ifdef CONFIG_MMC_SDMA
77 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
78 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
79 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
83 rdy
= SDHCI_INT_SPACE_AVAIL
| SDHCI_INT_DATA_AVAIL
;
84 mask
= SDHCI_DATA_AVAILABLE
| SDHCI_SPACE_AVAILABLE
;
86 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
87 if (stat
& SDHCI_INT_ERROR
) {
88 printf("%s: Error detected in status(0x%X)!\n",
93 if (!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
))
95 sdhci_writel(host
, rdy
, SDHCI_INT_STATUS
);
96 sdhci_transfer_pio(host
, data
);
97 data
->dest
+= data
->blocksize
;
98 if (++block
>= data
->blocks
)
101 #ifdef CONFIG_MMC_SDMA
102 if (stat
& SDHCI_INT_DMA_END
) {
103 sdhci_writel(host
, SDHCI_INT_DMA_END
, SDHCI_INT_STATUS
);
104 start_addr
&= ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1);
105 start_addr
+= SDHCI_DEFAULT_BOUNDARY_SIZE
;
106 sdhci_writel(host
, start_addr
, SDHCI_DMA_ADDRESS
);
112 printf("%s: Transfer data timeout\n", __func__
);
115 } while (!(stat
& SDHCI_INT_DATA_END
));
120 * No command will be sent by driver if card is busy, so driver must wait
121 * for card ready state.
122 * Every time when card is busy after timeout then (last) timeout value will be
123 * increased twice but only if it doesn't exceed global defined maximum.
124 * Each function call will use last timeout value. Max timeout can be redefined
125 * in board config file.
127 #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
128 #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200
130 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
131 #define SDHCI_READ_STATUS_TIMEOUT 1000
133 #ifdef CONFIG_DM_MMC_OPS
134 static int sdhci_send_command(struct udevice
*dev
, struct mmc_cmd
*cmd
,
135 struct mmc_data
*data
)
137 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
140 static int sdhci_send_command(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
141 struct mmc_data
*data
)
144 struct sdhci_host
*host
= mmc
->priv
;
145 unsigned int stat
= 0;
147 int trans_bytes
= 0, is_aligned
= 1;
148 u32 mask
, flags
, mode
;
149 unsigned int time
= 0, start_addr
= 0;
150 int mmc_dev
= mmc_get_blk_desc(mmc
)->devnum
;
151 unsigned start
= get_timer(0);
153 /* Timeout unit - ms */
154 static unsigned int cmd_timeout
= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT
;
156 sdhci_writel(host
, SDHCI_INT_ALL_MASK
, SDHCI_INT_STATUS
);
157 mask
= SDHCI_CMD_INHIBIT
| SDHCI_DATA_INHIBIT
;
159 /* We shouldn't wait for data inihibit for stop commands, even
160 though they might use busy signaling */
161 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
162 mask
&= ~SDHCI_DATA_INHIBIT
;
164 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
165 if (time
>= cmd_timeout
) {
166 printf("%s: MMC: %d busy ", __func__
, mmc_dev
);
167 if (2 * cmd_timeout
<= CONFIG_SDHCI_CMD_MAX_TIMEOUT
) {
168 cmd_timeout
+= cmd_timeout
;
169 printf("timeout increasing to: %u ms.\n",
180 mask
= SDHCI_INT_RESPONSE
;
181 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
182 flags
= SDHCI_CMD_RESP_NONE
;
183 else if (cmd
->resp_type
& MMC_RSP_136
)
184 flags
= SDHCI_CMD_RESP_LONG
;
185 else if (cmd
->resp_type
& MMC_RSP_BUSY
) {
186 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
187 mask
|= SDHCI_INT_DATA_END
;
189 flags
= SDHCI_CMD_RESP_SHORT
;
191 if (cmd
->resp_type
& MMC_RSP_CRC
)
192 flags
|= SDHCI_CMD_CRC
;
193 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
194 flags
|= SDHCI_CMD_INDEX
;
196 flags
|= SDHCI_CMD_DATA
;
198 /* Set Transfer mode regarding to data flag */
200 sdhci_writeb(host
, 0xe, SDHCI_TIMEOUT_CONTROL
);
201 mode
= SDHCI_TRNS_BLK_CNT_EN
;
202 trans_bytes
= data
->blocks
* data
->blocksize
;
203 if (data
->blocks
> 1)
204 mode
|= SDHCI_TRNS_MULTI
;
206 if (data
->flags
== MMC_DATA_READ
)
207 mode
|= SDHCI_TRNS_READ
;
209 #ifdef CONFIG_MMC_SDMA
210 if (data
->flags
== MMC_DATA_READ
)
211 start_addr
= (unsigned long)data
->dest
;
213 start_addr
= (unsigned long)data
->src
;
214 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) &&
215 (start_addr
& 0x7) != 0x0) {
217 start_addr
= (unsigned long)aligned_buffer
;
218 if (data
->flags
!= MMC_DATA_READ
)
219 memcpy(aligned_buffer
, data
->src
, trans_bytes
);
222 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
224 * Always use this bounce-buffer when
225 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
228 start_addr
= (unsigned long)aligned_buffer
;
229 if (data
->flags
!= MMC_DATA_READ
)
230 memcpy(aligned_buffer
, data
->src
, trans_bytes
);
233 sdhci_writel(host
, start_addr
, SDHCI_DMA_ADDRESS
);
234 mode
|= SDHCI_TRNS_DMA
;
236 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG
,
239 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
240 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
241 } else if (cmd
->resp_type
& MMC_RSP_BUSY
) {
242 sdhci_writeb(host
, 0xe, SDHCI_TIMEOUT_CONTROL
);
245 sdhci_writel(host
, cmd
->cmdarg
, SDHCI_ARGUMENT
);
246 #ifdef CONFIG_MMC_SDMA
247 flush_cache(start_addr
, trans_bytes
);
249 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->cmdidx
, flags
), SDHCI_COMMAND
);
250 start
= get_timer(0);
252 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
253 if (stat
& SDHCI_INT_ERROR
)
255 } while (((stat
& mask
) != mask
) &&
256 (get_timer(start
) < SDHCI_READ_STATUS_TIMEOUT
));
258 if (get_timer(start
) >= SDHCI_READ_STATUS_TIMEOUT
) {
259 if (host
->quirks
& SDHCI_QUIRK_BROKEN_R1B
)
262 printf("%s: Timeout for status update!\n", __func__
);
267 if ((stat
& (SDHCI_INT_ERROR
| mask
)) == mask
) {
268 sdhci_cmd_done(host
, cmd
);
269 sdhci_writel(host
, mask
, SDHCI_INT_STATUS
);
274 ret
= sdhci_transfer_data(host
, data
, start_addr
);
276 if (host
->quirks
& SDHCI_QUIRK_WAIT_SEND_CMD
)
279 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
280 sdhci_writel(host
, SDHCI_INT_ALL_MASK
, SDHCI_INT_STATUS
);
282 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) &&
283 !is_aligned
&& (data
->flags
== MMC_DATA_READ
))
284 memcpy(data
->dest
, aligned_buffer
, trans_bytes
);
288 sdhci_reset(host
, SDHCI_RESET_CMD
);
289 sdhci_reset(host
, SDHCI_RESET_DATA
);
290 if (stat
& SDHCI_INT_TIMEOUT
)
296 static int sdhci_set_clock(struct mmc
*mmc
, unsigned int clock
)
298 struct sdhci_host
*host
= mmc
->priv
;
299 unsigned int div
, clk
, timeout
, reg
;
303 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
304 (SDHCI_CMD_INHIBIT
| SDHCI_DATA_INHIBIT
)) {
306 printf("%s: Timeout to wait cmd & data inhibit\n",
315 reg
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
316 reg
&= ~SDHCI_CLOCK_CARD_EN
;
317 sdhci_writew(host
, reg
, SDHCI_CLOCK_CONTROL
);
322 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) {
323 /* Version 3.00 divisors must be a multiple of 2. */
324 if (mmc
->cfg
->f_max
<= clock
)
327 for (div
= 2; div
< SDHCI_MAX_DIV_SPEC_300
; div
+= 2) {
328 if ((mmc
->cfg
->f_max
/ div
) <= clock
)
333 /* Version 2.00 divisors must be a power of 2. */
334 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
335 if ((mmc
->cfg
->f_max
/ div
) <= clock
)
342 host
->set_clock(host
->index
, div
);
344 clk
= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
345 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
346 << SDHCI_DIVIDER_HI_SHIFT
;
347 clk
|= SDHCI_CLOCK_INT_EN
;
348 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
352 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
353 & SDHCI_CLOCK_INT_STABLE
)) {
355 printf("%s: Internal clock never stabilised.\n",
363 clk
|= SDHCI_CLOCK_CARD_EN
;
364 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
368 static void sdhci_set_power(struct sdhci_host
*host
, unsigned short power
)
372 if (power
!= (unsigned short)-1) {
373 switch (1 << power
) {
374 case MMC_VDD_165_195
:
375 pwr
= SDHCI_POWER_180
;
379 pwr
= SDHCI_POWER_300
;
383 pwr
= SDHCI_POWER_330
;
389 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
393 if (host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
)
394 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
396 pwr
|= SDHCI_POWER_ON
;
398 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
401 #ifdef CONFIG_DM_MMC_OPS
402 static int sdhci_set_ios(struct udevice
*dev
)
404 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
406 static void sdhci_set_ios(struct mmc
*mmc
)
410 struct sdhci_host
*host
= mmc
->priv
;
412 if (host
->set_control_reg
)
413 host
->set_control_reg(host
);
415 if (mmc
->clock
!= host
->clock
)
416 sdhci_set_clock(mmc
, mmc
->clock
);
419 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
420 if (mmc
->bus_width
== 8) {
421 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
422 if ((SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) ||
423 (host
->quirks
& SDHCI_QUIRK_USE_WIDE8
))
424 ctrl
|= SDHCI_CTRL_8BITBUS
;
426 if ((SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) ||
427 (host
->quirks
& SDHCI_QUIRK_USE_WIDE8
))
428 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
429 if (mmc
->bus_width
== 4)
430 ctrl
|= SDHCI_CTRL_4BITBUS
;
432 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
435 if (mmc
->clock
> 26000000)
436 ctrl
|= SDHCI_CTRL_HISPD
;
438 ctrl
&= ~SDHCI_CTRL_HISPD
;
440 if (host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
)
441 ctrl
&= ~SDHCI_CTRL_HISPD
;
443 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
444 #ifdef CONFIG_DM_MMC_OPS
449 static int sdhci_init(struct mmc
*mmc
)
451 struct sdhci_host
*host
= mmc
->priv
;
453 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) && !aligned_buffer
) {
454 aligned_buffer
= memalign(8, 512*1024);
455 if (!aligned_buffer
) {
456 printf("%s: Aligned buffer alloc failed!!!\n",
462 sdhci_set_power(host
, fls(mmc
->cfg
->voltages
) - 1);
464 if (host
->quirks
& SDHCI_QUIRK_NO_CD
) {
465 #if defined(CONFIG_PIC32_SDHCI)
466 /* PIC32 SDHCI CD errata:
467 * - set CD_TEST and clear CD_TEST_INS bit
469 sdhci_writeb(host
, SDHCI_CTRL_CD_TEST
, SDHCI_HOST_CONTROL
);
473 sdhci_writeb(host
, SDHCI_CTRL_CD_TEST_INS
| SDHCI_CTRL_CD_TEST
,
476 status
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
477 while ((!(status
& SDHCI_CARD_PRESENT
)) ||
478 (!(status
& SDHCI_CARD_STATE_STABLE
)) ||
479 (!(status
& SDHCI_CARD_DETECT_PIN_LEVEL
)))
480 status
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
484 /* Enable only interrupts served by the SD controller */
485 sdhci_writel(host
, SDHCI_INT_DATA_MASK
| SDHCI_INT_CMD_MASK
,
487 /* Mask all sdhci interrupt sources */
488 sdhci_writel(host
, 0x0, SDHCI_SIGNAL_ENABLE
);
493 #ifdef CONFIG_DM_MMC_OPS
494 int sdhci_probe(struct udevice
*dev
)
496 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
498 return sdhci_init(mmc
);
501 const struct dm_mmc_ops sdhci_ops
= {
502 .send_cmd
= sdhci_send_command
,
503 .set_ios
= sdhci_set_ios
,
506 static const struct mmc_ops sdhci_ops
= {
507 .send_cmd
= sdhci_send_command
,
508 .set_ios
= sdhci_set_ios
,
513 int sdhci_setup_cfg(struct mmc_config
*cfg
, const char *name
, int buswidth
,
514 uint caps
, u32 max_clk
, u32 min_clk
, uint version
,
515 uint quirks
, uint host_caps
)
518 #ifndef CONFIG_DM_MMC_OPS
519 cfg
->ops
= &sdhci_ops
;
522 cfg
->f_max
= max_clk
;
524 if (version
>= SDHCI_SPEC_300
)
525 cfg
->f_max
= (caps
& SDHCI_CLOCK_V3_BASE_MASK
) >>
526 SDHCI_CLOCK_BASE_SHIFT
;
528 cfg
->f_max
= (caps
& SDHCI_CLOCK_BASE_MASK
) >>
529 SDHCI_CLOCK_BASE_SHIFT
;
530 cfg
->f_max
*= 1000000;
535 cfg
->f_min
= min_clk
;
537 if (version
>= SDHCI_SPEC_300
)
538 cfg
->f_min
= cfg
->f_max
/ SDHCI_MAX_DIV_SPEC_300
;
540 cfg
->f_min
= cfg
->f_max
/ SDHCI_MAX_DIV_SPEC_200
;
543 if (caps
& SDHCI_CAN_VDD_330
)
544 cfg
->voltages
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
545 if (caps
& SDHCI_CAN_VDD_300
)
546 cfg
->voltages
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
547 if (caps
& SDHCI_CAN_VDD_180
)
548 cfg
->voltages
|= MMC_VDD_165_195
;
550 cfg
->host_caps
= MMC_MODE_HS
| MMC_MODE_HS_52MHz
| MMC_MODE_4BIT
;
551 if (version
>= SDHCI_SPEC_300
) {
552 if (caps
& SDHCI_CAN_DO_8BIT
)
553 cfg
->host_caps
|= MMC_MODE_8BIT
;
556 if (quirks
& SDHCI_QUIRK_NO_HISPD_BIT
)
557 cfg
->host_caps
&= ~(MMC_MODE_HS
| MMC_MODE_HS_52MHz
);
560 cfg
->host_caps
|= host_caps
;
563 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
569 int sdhci_bind(struct udevice
*dev
, struct mmc
*mmc
, struct mmc_config
*cfg
)
571 return mmc_bind(dev
, mmc
, cfg
);
574 int add_sdhci(struct sdhci_host
*host
, u32 max_clk
, u32 min_clk
)
578 caps
= sdhci_readl(host
, SDHCI_CAPABILITIES
);
579 #ifdef CONFIG_MMC_SDMA
580 if (!(caps
& SDHCI_CAN_DO_SDMA
)) {
581 printf("%s: Your controller doesn't support SDMA!!\n",
587 if (sdhci_setup_cfg(&host
->cfg
, host
->name
, host
->bus_width
, caps
,
588 max_clk
, min_clk
, SDHCI_GET_VERSION(host
),
589 host
->quirks
, host
->host_caps
)) {
590 printf("%s: Hardware doesn't specify base clock frequency\n",
595 if (host
->quirks
& SDHCI_QUIRK_BROKEN_VOLTAGE
)
596 host
->cfg
.voltages
|= host
->voltages
;
598 sdhci_reset(host
, SDHCI_RESET_ALL
);
600 host
->mmc
= mmc_create(&host
->cfg
, host
);
601 if (host
->mmc
== NULL
) {
602 printf("%s: mmc create fail!\n", __func__
);