drivers/mmc/sh_mmcif.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * MMCIF driver.
   4  *
   5  * Copyright (C)  2011 Renesas Solutions Corp.
   6  */
   7
   8 #ifndef _SH_MMCIF_H_
   9 #define _SH_MMCIF_H_
  10
  11 struct sh_mmcif_regs {
  12         unsigned long ce_cmd_set;
  13         unsigned long reserved;
  14         unsigned long ce_arg;
  15         unsigned long ce_arg_cmd12;
  16         unsigned long ce_cmd_ctrl;
  17         unsigned long ce_block_set;
  18         unsigned long ce_clk_ctrl;
  19         unsigned long ce_buf_acc;
  20         unsigned long ce_resp3;
  21         unsigned long ce_resp2;
  22         unsigned long ce_resp1;
  23         unsigned long ce_resp0;
  24         unsigned long ce_resp_cmd12;
  25         unsigned long ce_data;
  26         unsigned long reserved2[2];
  27         unsigned long ce_int;
  28         unsigned long ce_int_mask;
  29         unsigned long ce_host_sts1;
  30         unsigned long ce_host_sts2;
  31         unsigned long reserved3[11];
  32         unsigned long ce_version;
  33 };
  34
  35 /* CE_CMD_SET */
  36 #define CMD_MASK                0x3f000000
  37 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
  38 /* R1/R1b/R3/R4/R5 */
  39 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22))
  40 /* R2 */
  41 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22))
  42 /* R1b */
  43 #define CMD_SET_RBSY            (1 << 21)
  44 #define CMD_SET_CCSEN           (1 << 20)
  45 /* 1: on data, 0: no data */
  46 #define CMD_SET_WDAT            (1 << 19)
  47 /* 1: write to card, 0: read from card */
  48 #define CMD_SET_DWEN            (1 << 18)
  49 /* 1: multi block trans, 0: single */
  50 #define CMD_SET_CMLTE           (1 << 17)
  51 /* 1: CMD12 auto issue */
  52 #define CMD_SET_CMD12EN         (1 << 16)
  53 /* index check */
  54 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14))
  55 /* check bits check */
  56 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14))
  57 /* no check */
  58 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14))
  59 /* 1: CRC7 check*/
  60 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12))
  61 /* 1: check bits check*/
  62 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12))
  63 /* 1: internal CRC7 check*/
  64 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12))
  65 /* 1: CRC16 check*/
  66 #define CMD_SET_CRC16C          (1 << 10)
  67 /* 1: not receive CRC status */
  68 #define CMD_SET_CRCSTE          (1 << 8)
  69 /* 1: tran mission bit "Low" */
  70 #define CMD_SET_TBIT            (1 << 7)
  71 /* 1: open/drain */
  72 #define CMD_SET_OPDM            (1 << 6)
  73 #define CMD_SET_CCSH            (1 << 5)
  74 /* 1bit */
  75 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0))
  76 /* 4bit */
  77 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0))
  78 /* 8bit */
  79 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0))
  80
  81 /* CE_CMD_CTRL */
  82 #define CMD_CTRL_BREAK          (1 << 0)
  83
  84 /* CE_BLOCK_SET */
  85 #define BLOCK_SIZE_MASK         0x0000ffff
  86
  87 /* CE_CLK_CTRL */
  88 #define CLK_ENABLE              (1 << 24)
  89 #define CLK_CLEAR               ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
  90 #define CLK_PCLK                ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
  91 /* respons timeout */
  92 #define SRSPTO_256              ((1 << 13) | (0 << 12))
  93 /* respons busy timeout */
  94 #define SRBSYTO_29              ((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8))
  95 /* read/write timeout */
  96 #define SRWDTO_29               ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
  97 /* ccs timeout */
  98 #define SCCSTO_29               ((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0))
  99
 100 /* CE_BUF_ACC */
 101 #define BUF_ACC_DMAWEN          (1 << 25)
 102 #define BUF_ACC_DMAREN          (1 << 24)
 103 #define BUF_ACC_BUSW_32         (0 << 17)
 104 #define BUF_ACC_BUSW_16         (1 << 17)
 105 #define BUF_ACC_ATYP            (1 << 16)
 106
 107 /* CE_INT */
 108 #define INT_CCSDE               (1 << 29)
 109 #define INT_CMD12DRE            (1 << 26)
 110 #define INT_CMD12RBE            (1 << 25)
 111 #define INT_CMD12CRE            (1 << 24)
 112 #define INT_DTRANE              (1 << 23)
 113 #define INT_BUFRE               (1 << 22)
 114 #define INT_BUFWEN              (1 << 21)
 115 #define INT_BUFREN              (1 << 20)
 116 #define INT_CCSRCV              (1 << 19)
 117 #define INT_RBSYE               (1 << 17)
 118 #define INT_CRSPE               (1 << 16)
 119 #define INT_CMDVIO              (1 << 15)
 120 #define INT_BUFVIO              (1 << 14)
 121 #define INT_WDATERR             (1 << 11)
 122 #define INT_RDATERR             (1 << 10)
 123 #define INT_RIDXERR             (1 << 9)
 124 #define INT_RSPERR              (1 << 8)
 125 #define INT_CCSTO               (1 << 5)
 126 #define INT_CRCSTO              (1 << 4)
 127 #define INT_WDATTO              (1 << 3)
 128 #define INT_RDATTO              (1 << 2)
 129 #define INT_RBSYTO              (1 << 1)
 130 #define INT_RSPTO               (1 << 0)
 131 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
 132                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
 133                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
 134                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
 135 #define INT_START_MAGIC         0xD80430C0
 136
 137 /* CE_INT_MASK */
 138 #define MASK_ALL                0x00000000
 139 #define MASK_MCCSDE             (1 << 29)
 140 #define MASK_MCMD12DRE          (1 << 26)
 141 #define MASK_MCMD12RBE          (1 << 25)
 142 #define MASK_MCMD12CRE          (1 << 24)
 143 #define MASK_MDTRANE            (1 << 23)
 144 #define MASK_MBUFRE             (1 << 22)
 145 #define MASK_MBUFWEN            (1 << 21)
 146 #define MASK_MBUFREN            (1 << 20)
 147 #define MASK_MCCSRCV            (1 << 19)
 148 #define MASK_MRBSYE             (1 << 17)
 149 #define MASK_MCRSPE             (1 << 16)
 150 #define MASK_MCMDVIO            (1 << 15)
 151 #define MASK_MBUFVIO            (1 << 14)
 152 #define MASK_MWDATERR           (1 << 11)
 153 #define MASK_MRDATERR           (1 << 10)
 154 #define MASK_MRIDXERR           (1 << 9)
 155 #define MASK_MRSPERR            (1 << 8)
 156 #define MASK_MCCSTO             (1 << 5)
 157 #define MASK_MCRCSTO            (1 << 4)
 158 #define MASK_MWDATTO            (1 << 3)
 159 #define MASK_MRDATTO            (1 << 2)
 160 #define MASK_MRBSYTO            (1 << 1)
 161 #define MASK_MRSPTO             (1 << 0)
 162
 163 /* CE_HOST_STS1 */
 164 #define STS1_CMDSEQ             (1 << 31)
 165
 166 /* CE_HOST_STS2 */
 167 #define STS2_CRCSTE             (1 << 31)
 168 #define STS2_CRC16E             (1 << 30)
 169 #define STS2_AC12CRCE           (1 << 29)
 170 #define STS2_RSPCRC7E           (1 << 28)
 171 #define STS2_CRCSTEBE           (1 << 27)
 172 #define STS2_RDATEBE            (1 << 26)
 173 #define STS2_AC12REBE           (1 << 25)
 174 #define STS2_RSPEBE             (1 << 24)
 175 #define STS2_AC12IDXE           (1 << 23)
 176 #define STS2_RSPIDXE            (1 << 22)
 177 #define STS2_CCSTO              (1 << 15)
 178 #define STS2_RDATTO             (1 << 14)
 179 #define STS2_DATBSYTO           (1 << 13)
 180 #define STS2_CRCSTTO            (1 << 12)
 181 #define STS2_AC12BSYTO          (1 << 11)
 182 #define STS2_RSPBSYTO           (1 << 10)
 183 #define STS2_AC12RSPTO          (1 << 9)
 184 #define STS2_RSPTO              (1 << 8)
 185
 186 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
 187                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
 188 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
 189                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
 190                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
 191                                  STS2_AC12RSPTO | STS2_RSPTO)
 192
 193 /* CE_VERSION */
 194 #define SOFT_RST_ON             (1 << 31)
 195 #define SOFT_RST_OFF            (0 << 31)
 196
 197 #define CLKDEV_EMMC_DATA        52000000        /* 52MHz */
 198 #ifdef CONFIG_ARCH_RMOBILE
 199 #define MMC_CLK_DIV_MIN(clk)    (clk / (1 << 9))
 200 #define MMC_CLK_DIV_MAX(clk)    (clk / (1 << 1))
 201 #else
 202 #define MMC_CLK_DIV_MIN(clk)    (clk / (1 << 8))
 203 #define MMC_CLK_DIV_MAX(clk)    CLKDEV_EMMC_DATA
 204 #endif
 205
 206 #define MMC_BUS_WIDTH_1         0
 207 #define MMC_BUS_WIDTH_4         2
 208 #define MMC_BUS_WIDTH_8         3
 209
 210 struct sh_mmcif_host {
 211         struct mmc_data         *data;
 212         struct sh_mmcif_regs    *regs;
 213         unsigned int            clk;
 214         int                     bus_width;
 215         u16                     wait_int;
 216         u16                     sd_error;
 217         u8                      last_cmd;
 218 };
 219
 220 static inline u32 sh_mmcif_read(unsigned long *reg)
 221 {
 222         return readl(reg);
 223 }
 224
 225 static inline void sh_mmcif_write(u32 val, unsigned long *reg)
 226 {
 227         writel(val, reg);
 228 }
 229
 230 static inline void sh_mmcif_bitset(u32 val, unsigned long *reg)
 231 {
 232         sh_mmcif_write(val | sh_mmcif_read(reg), reg);
 233 }
 234
 235 static inline void sh_mmcif_bitclr(u32 val, unsigned long *reg)
 236 {
 237         sh_mmcif_write(~val & sh_mmcif_read(reg), reg);
 238 }
 239
 240 #endif /* _SH_MMCIF_H_ */