3 * Patrice Chotard <patrice.chotard@st.com>
5 * SPDX-License-Identifier: GPL-2.0
11 #include <reset-uclass.h>
13 #include <asm/arch/sdhci.h>
15 DECLARE_GLOBAL_DATA_PTR
;
17 struct sti_sdhci_plat
{
18 struct mmc_config cfg
;
20 struct reset_ctl reset
;
25 * sti_mmc_core_config: configure the Arasan HC
28 * Description: this function is to configure the Arasan MMC HC.
29 * This should be called when the system starts in case of, on the SoC,
30 * it is needed to configure the host controller.
31 * This happens on some SoCs, i.e. StiH410, where the MMC0 inside the flashSS
32 * needs to be configured as MMC 4.5 to have full capabilities.
33 * W/o these settings the SDHCI could configure and use the embedded controller
34 * with limited features.
36 static int sti_mmc_core_config(struct udevice
*dev
)
38 struct sti_sdhci_plat
*plat
= dev_get_platdata(dev
);
39 struct sdhci_host
*host
= dev_get_priv(dev
);
42 /* only MMC1 has a reset line */
44 ret
= reset_deassert(&plat
->reset
);
46 pr_err("MMC1 deassert failed: %d", ret
);
51 writel(STI_FLASHSS_MMC_CORE_CONFIG_1
,
52 host
->ioaddr
+ FLASHSS_MMC_CORE_CONFIG_1
);
55 writel(STI_FLASHSS_MMC_CORE_CONFIG2
,
56 host
->ioaddr
+ FLASHSS_MMC_CORE_CONFIG_2
);
57 writel(STI_FLASHSS_MMC_CORE_CONFIG3
,
58 host
->ioaddr
+ FLASHSS_MMC_CORE_CONFIG_3
);
60 writel(STI_FLASHSS_SDCARD_CORE_CONFIG2
,
61 host
->ioaddr
+ FLASHSS_MMC_CORE_CONFIG_2
);
62 writel(STI_FLASHSS_SDCARD_CORE_CONFIG3
,
63 host
->ioaddr
+ FLASHSS_MMC_CORE_CONFIG_3
);
65 writel(STI_FLASHSS_MMC_CORE_CONFIG4
,
66 host
->ioaddr
+ FLASHSS_MMC_CORE_CONFIG_4
);
71 static int sti_sdhci_probe(struct udevice
*dev
)
73 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
74 struct sti_sdhci_plat
*plat
= dev_get_platdata(dev
);
75 struct sdhci_host
*host
= dev_get_priv(dev
);
79 * identify current mmc instance, mmc1 has a reset, not mmc0
80 * MMC0 is wired to the SD slot,
81 * MMC1 is wired on the high speed connector
83 ret
= reset_get_by_index(dev
, 0, &plat
->reset
);
92 ret
= sti_mmc_core_config(dev
);
96 host
->quirks
= SDHCI_QUIRK_WAIT_SEND_CMD
|
97 SDHCI_QUIRK_32BIT_DMA_ADDR
|
98 SDHCI_QUIRK_NO_HISPD_BIT
;
100 host
->host_caps
= MMC_MODE_DDR_52MHz
;
102 ret
= sdhci_setup_cfg(&plat
->cfg
, host
, 50000000, 400000);
106 host
->mmc
= &plat
->mmc
;
107 host
->mmc
->priv
= host
;
108 host
->mmc
->dev
= dev
;
109 upriv
->mmc
= host
->mmc
;
111 return sdhci_probe(dev
);
114 static int sti_sdhci_ofdata_to_platdata(struct udevice
*dev
)
116 struct sdhci_host
*host
= dev_get_priv(dev
);
118 host
->name
= strdup(dev
->name
);
119 host
->ioaddr
= (void *)devfdt_get_addr(dev
);
121 host
->bus_width
= fdtdec_get_int(gd
->fdt_blob
, dev_of_offset(dev
),
127 static int sti_sdhci_bind(struct udevice
*dev
)
129 struct sti_sdhci_plat
*plat
= dev_get_platdata(dev
);
131 return sdhci_bind(dev
, &plat
->mmc
, &plat
->cfg
);
134 static const struct udevice_id sti_sdhci_ids
[] = {
135 { .compatible
= "st,sdhci" },
139 U_BOOT_DRIVER(sti_mmc
) = {
142 .of_match
= sti_sdhci_ids
,
143 .bind
= sti_sdhci_bind
,
145 .ofdata_to_platdata
= sti_sdhci_ofdata_to_platdata
,
146 .probe
= sti_sdhci_probe
,
147 .priv_auto_alloc_size
= sizeof(struct sdhci_host
),
148 .platdata_auto_alloc_size
= sizeof(struct sti_sdhci_plat
),