2 * (C) Copyright 2007-2011
3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4 * Aaron <leafy.myeh@allwinnertech.com>
6 * MMC driver for allwinner sunxi platform.
8 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/mmc.h>
20 #include <asm-generic/gpio.h>
22 struct sunxi_mmc_host
{
26 struct sunxi_mmc
*reg
;
27 struct mmc_config cfg
;
30 /* support 4 mmc hosts */
31 struct sunxi_mmc_host mmc_host
[4];
33 static int sunxi_mmc_getcd_gpio(int sdc_no
)
36 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN
);
37 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN
);
38 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN
);
39 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN
);
44 static int mmc_resource_init(int sdc_no
)
46 struct sunxi_mmc_host
*mmchost
= &mmc_host
[sdc_no
];
47 struct sunxi_ccm_reg
*ccm
= (struct sunxi_ccm_reg
*)SUNXI_CCM_BASE
;
50 debug("init mmc %d resource\n", sdc_no
);
54 mmchost
->reg
= (struct sunxi_mmc
*)SUNXI_MMC0_BASE
;
55 mmchost
->mclkreg
= &ccm
->sd0_clk_cfg
;
58 mmchost
->reg
= (struct sunxi_mmc
*)SUNXI_MMC1_BASE
;
59 mmchost
->mclkreg
= &ccm
->sd1_clk_cfg
;
62 mmchost
->reg
= (struct sunxi_mmc
*)SUNXI_MMC2_BASE
;
63 mmchost
->mclkreg
= &ccm
->sd2_clk_cfg
;
66 mmchost
->reg
= (struct sunxi_mmc
*)SUNXI_MMC3_BASE
;
67 mmchost
->mclkreg
= &ccm
->sd3_clk_cfg
;
70 printf("Wrong mmc number %d\n", sdc_no
);
73 mmchost
->mmc_no
= sdc_no
;
75 cd_pin
= sunxi_mmc_getcd_gpio(sdc_no
);
77 ret
= gpio_request(cd_pin
, "mmc_cd");
79 sunxi_gpio_set_pull(cd_pin
, SUNXI_GPIO_PULL_UP
);
80 ret
= gpio_direction_input(cd_pin
);
87 static int mmc_set_mod_clk(struct sunxi_mmc_host
*mmchost
, unsigned int hz
)
89 unsigned int pll
, pll_hz
, div
, n
, oclk_dly
, sclk_dly
;
92 pll
= CCM_MMC_CTRL_OSCM24
;
95 #ifdef CONFIG_MACH_SUN9I
96 pll
= CCM_MMC_CTRL_PLL_PERIPH0
;
97 pll_hz
= clock_get_pll4_periph0();
99 pll
= CCM_MMC_CTRL_PLL6
;
100 pll_hz
= clock_get_pll6();
115 printf("mmc %u error cannot set clock to %u\n",
116 mmchost
->mmc_no
, hz
);
120 /* determine delays */
124 } else if (hz
<= 25000000) {
127 #ifdef CONFIG_MACH_SUN9I
128 } else if (hz
<= 50000000) {
136 } else if (hz
<= 50000000) {
146 writel(CCM_MMC_CTRL_ENABLE
| pll
| CCM_MMC_CTRL_SCLK_DLY(sclk_dly
) |
147 CCM_MMC_CTRL_N(n
) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly
) |
148 CCM_MMC_CTRL_M(div
), mmchost
->mclkreg
);
150 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
151 mmchost
->mmc_no
, hz
, pll_hz
, 1u << n
, div
,
152 pll_hz
/ (1u << n
) / div
);
157 static int mmc_clk_io_on(int sdc_no
)
159 struct sunxi_mmc_host
*mmchost
= &mmc_host
[sdc_no
];
160 struct sunxi_ccm_reg
*ccm
= (struct sunxi_ccm_reg
*)SUNXI_CCM_BASE
;
162 debug("init mmc %d clock and io\n", sdc_no
);
164 /* config ahb clock */
165 setbits_le32(&ccm
->ahb_gate0
, 1 << AHB_GATE_OFFSET_MMC(sdc_no
));
167 #ifdef CONFIG_SUNXI_GEN_SUN6I
169 setbits_le32(&ccm
->ahb_reset0_cfg
, 1 << AHB_RESET_OFFSET_MMC(sdc_no
));
171 #if defined(CONFIG_MACH_SUN9I)
172 /* sun9i has a mmc-common module, also set the gate and reset there */
173 writel(SUNXI_MMC_COMMON_CLK_GATE
| SUNXI_MMC_COMMON_RESET
,
174 SUNXI_MMC_COMMON_BASE
+ 4 * sdc_no
);
177 return mmc_set_mod_clk(mmchost
, 24000000);
180 static int mmc_update_clk(struct mmc
*mmc
)
182 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
184 unsigned timeout_msecs
= 2000;
186 cmd
= SUNXI_MMC_CMD_START
|
187 SUNXI_MMC_CMD_UPCLK_ONLY
|
188 SUNXI_MMC_CMD_WAIT_PRE_OVER
;
189 writel(cmd
, &mmchost
->reg
->cmd
);
190 while (readl(&mmchost
->reg
->cmd
) & SUNXI_MMC_CMD_START
) {
191 if (!timeout_msecs
--)
196 /* clock update sets various irq status bits, clear these */
197 writel(readl(&mmchost
->reg
->rint
), &mmchost
->reg
->rint
);
202 static int mmc_config_clock(struct mmc
*mmc
)
204 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
205 unsigned rval
= readl(&mmchost
->reg
->clkcr
);
208 rval
&= ~SUNXI_MMC_CLK_ENABLE
;
209 writel(rval
, &mmchost
->reg
->clkcr
);
210 if (mmc_update_clk(mmc
))
213 /* Set mod_clk to new rate */
214 if (mmc_set_mod_clk(mmchost
, mmc
->clock
))
217 /* Clear internal divider */
218 rval
&= ~SUNXI_MMC_CLK_DIVIDER_MASK
;
219 writel(rval
, &mmchost
->reg
->clkcr
);
221 /* Re-enable Clock */
222 rval
|= SUNXI_MMC_CLK_ENABLE
;
223 writel(rval
, &mmchost
->reg
->clkcr
);
224 if (mmc_update_clk(mmc
))
230 static int sunxi_mmc_set_ios(struct mmc
*mmc
)
232 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
234 debug("set ios: bus_width: %x, clock: %d\n",
235 mmc
->bus_width
, mmc
->clock
);
237 /* Change clock first */
238 if (mmc
->clock
&& mmc_config_clock(mmc
) != 0) {
239 mmchost
->fatal_err
= 1;
243 /* Change bus width */
244 if (mmc
->bus_width
== 8)
245 writel(0x2, &mmchost
->reg
->width
);
246 else if (mmc
->bus_width
== 4)
247 writel(0x1, &mmchost
->reg
->width
);
249 writel(0x0, &mmchost
->reg
->width
);
254 static int sunxi_mmc_core_init(struct mmc
*mmc
)
256 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
258 /* Reset controller */
259 writel(SUNXI_MMC_GCTRL_RESET
, &mmchost
->reg
->gctrl
);
265 static int mmc_trans_data_by_cpu(struct mmc
*mmc
, struct mmc_data
*data
)
267 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
268 const int reading
= !!(data
->flags
& MMC_DATA_READ
);
269 const uint32_t status_bit
= reading
? SUNXI_MMC_STATUS_FIFO_EMPTY
:
270 SUNXI_MMC_STATUS_FIFO_FULL
;
272 unsigned *buff
= (unsigned int *)(reading
? data
->dest
: data
->src
);
273 unsigned byte_cnt
= data
->blocksize
* data
->blocks
;
274 unsigned timeout_usecs
= (byte_cnt
>> 8) * 1000;
275 if (timeout_usecs
< 2000000)
276 timeout_usecs
= 2000000;
278 /* Always read / write data through the CPU */
279 setbits_le32(&mmchost
->reg
->gctrl
, SUNXI_MMC_GCTRL_ACCESS_BY_AHB
);
281 for (i
= 0; i
< (byte_cnt
>> 2); i
++) {
282 while (readl(&mmchost
->reg
->status
) & status_bit
) {
283 if (!timeout_usecs
--)
289 buff
[i
] = readl(&mmchost
->reg
->fifo
);
291 writel(buff
[i
], &mmchost
->reg
->fifo
);
297 static int mmc_rint_wait(struct mmc
*mmc
, unsigned int timeout_msecs
,
298 unsigned int done_bit
, const char *what
)
300 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
304 status
= readl(&mmchost
->reg
->rint
);
305 if (!timeout_msecs
-- ||
306 (status
& SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT
)) {
307 debug("%s timeout %x\n", what
,
308 status
& SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT
);
312 } while (!(status
& done_bit
));
317 static int sunxi_mmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
318 struct mmc_data
*data
)
320 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
321 unsigned int cmdval
= SUNXI_MMC_CMD_START
;
322 unsigned int timeout_msecs
;
324 unsigned int status
= 0;
325 unsigned int bytecnt
= 0;
327 if (mmchost
->fatal_err
)
329 if (cmd
->resp_type
& MMC_RSP_BUSY
)
330 debug("mmc cmd %d check rsp busy\n", cmd
->cmdidx
);
331 if (cmd
->cmdidx
== 12)
335 cmdval
|= SUNXI_MMC_CMD_SEND_INIT_SEQ
;
336 if (cmd
->resp_type
& MMC_RSP_PRESENT
)
337 cmdval
|= SUNXI_MMC_CMD_RESP_EXPIRE
;
338 if (cmd
->resp_type
& MMC_RSP_136
)
339 cmdval
|= SUNXI_MMC_CMD_LONG_RESPONSE
;
340 if (cmd
->resp_type
& MMC_RSP_CRC
)
341 cmdval
|= SUNXI_MMC_CMD_CHK_RESPONSE_CRC
;
344 if ((u32
)(long)data
->dest
& 0x3) {
349 cmdval
|= SUNXI_MMC_CMD_DATA_EXPIRE
|SUNXI_MMC_CMD_WAIT_PRE_OVER
;
350 if (data
->flags
& MMC_DATA_WRITE
)
351 cmdval
|= SUNXI_MMC_CMD_WRITE
;
352 if (data
->blocks
> 1)
353 cmdval
|= SUNXI_MMC_CMD_AUTO_STOP
;
354 writel(data
->blocksize
, &mmchost
->reg
->blksz
);
355 writel(data
->blocks
* data
->blocksize
, &mmchost
->reg
->bytecnt
);
358 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost
->mmc_no
,
359 cmd
->cmdidx
, cmdval
| cmd
->cmdidx
, cmd
->cmdarg
);
360 writel(cmd
->cmdarg
, &mmchost
->reg
->arg
);
363 writel(cmdval
| cmd
->cmdidx
, &mmchost
->reg
->cmd
);
366 * transfer data and check status
367 * STATREG[2] : FIFO empty
368 * STATREG[3] : FIFO full
373 bytecnt
= data
->blocksize
* data
->blocks
;
374 debug("trans data %d bytes\n", bytecnt
);
375 writel(cmdval
| cmd
->cmdidx
, &mmchost
->reg
->cmd
);
376 ret
= mmc_trans_data_by_cpu(mmc
, data
);
378 error
= readl(&mmchost
->reg
->rint
) & \
379 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT
;
385 error
= mmc_rint_wait(mmc
, 1000, SUNXI_MMC_RINT_COMMAND_DONE
, "cmd");
391 debug("cacl timeout %x msec\n", timeout_msecs
);
392 error
= mmc_rint_wait(mmc
, timeout_msecs
,
394 SUNXI_MMC_RINT_AUTO_COMMAND_DONE
:
395 SUNXI_MMC_RINT_DATA_OVER
,
401 if (cmd
->resp_type
& MMC_RSP_BUSY
) {
402 timeout_msecs
= 2000;
404 status
= readl(&mmchost
->reg
->status
);
405 if (!timeout_msecs
--) {
406 debug("busy timeout\n");
411 } while (status
& SUNXI_MMC_STATUS_CARD_DATA_BUSY
);
414 if (cmd
->resp_type
& MMC_RSP_136
) {
415 cmd
->response
[0] = readl(&mmchost
->reg
->resp3
);
416 cmd
->response
[1] = readl(&mmchost
->reg
->resp2
);
417 cmd
->response
[2] = readl(&mmchost
->reg
->resp1
);
418 cmd
->response
[3] = readl(&mmchost
->reg
->resp0
);
419 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
420 cmd
->response
[3], cmd
->response
[2],
421 cmd
->response
[1], cmd
->response
[0]);
423 cmd
->response
[0] = readl(&mmchost
->reg
->resp0
);
424 debug("mmc resp 0x%08x\n", cmd
->response
[0]);
428 writel(SUNXI_MMC_GCTRL_RESET
, &mmchost
->reg
->gctrl
);
431 writel(0xffffffff, &mmchost
->reg
->rint
);
432 writel(readl(&mmchost
->reg
->gctrl
) | SUNXI_MMC_GCTRL_FIFO_RESET
,
433 &mmchost
->reg
->gctrl
);
438 static int sunxi_mmc_getcd(struct mmc
*mmc
)
440 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
443 cd_pin
= sunxi_mmc_getcd_gpio(mmchost
->mmc_no
);
447 return !gpio_get_value(cd_pin
);
450 static const struct mmc_ops sunxi_mmc_ops
= {
451 .send_cmd
= sunxi_mmc_send_cmd
,
452 .set_ios
= sunxi_mmc_set_ios
,
453 .init
= sunxi_mmc_core_init
,
454 .getcd
= sunxi_mmc_getcd
,
457 struct mmc
*sunxi_mmc_init(int sdc_no
)
459 struct mmc_config
*cfg
= &mmc_host
[sdc_no
].cfg
;
461 memset(&mmc_host
[sdc_no
], 0, sizeof(struct sunxi_mmc_host
));
463 cfg
->name
= "SUNXI SD/MMC";
464 cfg
->ops
= &sunxi_mmc_ops
;
466 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
467 cfg
->host_caps
= MMC_MODE_4BIT
;
468 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
470 cfg
->host_caps
= MMC_MODE_8BIT
;
472 cfg
->host_caps
|= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
473 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
476 cfg
->f_max
= 52000000;
478 if (mmc_resource_init(sdc_no
) != 0)
481 mmc_clk_io_on(sdc_no
);
483 return mmc_create(cfg
, &mmc_host
[sdc_no
]);