2 * (C) Copyright 2007-2011
3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4 * Aaron <leafy.myeh@allwinnertech.com>
6 * MMC driver for allwinner sunxi platform.
8 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/mmc.h>
20 #include <asm-generic/gpio.h>
22 struct sunxi_mmc_host
{
26 struct sunxi_mmc
*reg
;
27 struct mmc_config cfg
;
30 /* support 4 mmc hosts */
31 struct sunxi_mmc_host mmc_host
[4];
33 static int sunxi_mmc_getcd_gpio(int sdc_no
)
36 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN
);
37 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN
);
38 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN
);
39 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN
);
44 static int mmc_resource_init(int sdc_no
)
46 struct sunxi_mmc_host
*mmchost
= &mmc_host
[sdc_no
];
47 struct sunxi_ccm_reg
*ccm
= (struct sunxi_ccm_reg
*)SUNXI_CCM_BASE
;
50 debug("init mmc %d resource\n", sdc_no
);
54 mmchost
->reg
= (struct sunxi_mmc
*)SUNXI_MMC0_BASE
;
55 mmchost
->mclkreg
= &ccm
->sd0_clk_cfg
;
58 mmchost
->reg
= (struct sunxi_mmc
*)SUNXI_MMC1_BASE
;
59 mmchost
->mclkreg
= &ccm
->sd1_clk_cfg
;
62 mmchost
->reg
= (struct sunxi_mmc
*)SUNXI_MMC2_BASE
;
63 mmchost
->mclkreg
= &ccm
->sd2_clk_cfg
;
66 mmchost
->reg
= (struct sunxi_mmc
*)SUNXI_MMC3_BASE
;
67 mmchost
->mclkreg
= &ccm
->sd3_clk_cfg
;
70 printf("Wrong mmc number %d\n", sdc_no
);
73 mmchost
->mmc_no
= sdc_no
;
75 cd_pin
= sunxi_mmc_getcd_gpio(sdc_no
);
77 ret
= gpio_request(cd_pin
, "mmc_cd");
79 sunxi_gpio_set_pull(cd_pin
, SUNXI_GPIO_PULL_UP
);
80 ret
= gpio_direction_input(cd_pin
);
87 static int mmc_set_mod_clk(struct sunxi_mmc_host
*mmchost
, unsigned int hz
)
89 unsigned int pll
, pll_hz
, div
, n
, oclk_dly
, sclk_dly
;
92 pll
= CCM_MMC_CTRL_OSCM24
;
95 #ifdef CONFIG_MACH_SUN9I
96 pll
= CCM_MMC_CTRL_PLL_PERIPH0
;
97 pll_hz
= clock_get_pll4_periph0();
99 pll
= CCM_MMC_CTRL_PLL6
;
100 pll_hz
= clock_get_pll6();
115 printf("mmc %u error cannot set clock to %u\n",
116 mmchost
->mmc_no
, hz
);
120 /* determine delays */
124 } else if (hz
<= 25000000) {
127 } else if (hz
<= 50000000) {
136 writel(CCM_MMC_CTRL_ENABLE
| pll
| CCM_MMC_CTRL_SCLK_DLY(sclk_dly
) |
137 CCM_MMC_CTRL_N(n
) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly
) |
138 CCM_MMC_CTRL_M(div
), mmchost
->mclkreg
);
140 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
141 mmchost
->mmc_no
, hz
, pll_hz
, 1u << n
, div
,
142 pll_hz
/ (1u << n
) / div
);
147 static int mmc_clk_io_on(int sdc_no
)
149 struct sunxi_mmc_host
*mmchost
= &mmc_host
[sdc_no
];
150 struct sunxi_ccm_reg
*ccm
= (struct sunxi_ccm_reg
*)SUNXI_CCM_BASE
;
152 debug("init mmc %d clock and io\n", sdc_no
);
154 /* config ahb clock */
155 setbits_le32(&ccm
->ahb_gate0
, 1 << AHB_GATE_OFFSET_MMC(sdc_no
));
157 #ifdef CONFIG_SUNXI_GEN_SUN6I
159 setbits_le32(&ccm
->ahb_reset0_cfg
, 1 << AHB_RESET_OFFSET_MMC(sdc_no
));
161 #if defined(CONFIG_MACH_SUN9I)
162 /* sun9i has a mmc-common module, also set the gate and reset there */
163 writel(SUNXI_MMC_COMMON_CLK_GATE
| SUNXI_MMC_COMMON_RESET
,
164 SUNXI_MMC_COMMON_BASE
+ 4 * sdc_no
);
167 return mmc_set_mod_clk(mmchost
, 24000000);
170 static int mmc_update_clk(struct mmc
*mmc
)
172 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
174 unsigned timeout_msecs
= 2000;
176 cmd
= SUNXI_MMC_CMD_START
|
177 SUNXI_MMC_CMD_UPCLK_ONLY
|
178 SUNXI_MMC_CMD_WAIT_PRE_OVER
;
179 writel(cmd
, &mmchost
->reg
->cmd
);
180 while (readl(&mmchost
->reg
->cmd
) & SUNXI_MMC_CMD_START
) {
181 if (!timeout_msecs
--)
186 /* clock update sets various irq status bits, clear these */
187 writel(readl(&mmchost
->reg
->rint
), &mmchost
->reg
->rint
);
192 static int mmc_config_clock(struct mmc
*mmc
)
194 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
195 unsigned rval
= readl(&mmchost
->reg
->clkcr
);
198 rval
&= ~SUNXI_MMC_CLK_ENABLE
;
199 writel(rval
, &mmchost
->reg
->clkcr
);
200 if (mmc_update_clk(mmc
))
203 /* Set mod_clk to new rate */
204 if (mmc_set_mod_clk(mmchost
, mmc
->clock
))
207 /* Clear internal divider */
208 rval
&= ~SUNXI_MMC_CLK_DIVIDER_MASK
;
209 writel(rval
, &mmchost
->reg
->clkcr
);
211 /* Re-enable Clock */
212 rval
|= SUNXI_MMC_CLK_ENABLE
;
213 writel(rval
, &mmchost
->reg
->clkcr
);
214 if (mmc_update_clk(mmc
))
220 static void sunxi_mmc_set_ios(struct mmc
*mmc
)
222 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
224 debug("set ios: bus_width: %x, clock: %d\n",
225 mmc
->bus_width
, mmc
->clock
);
227 /* Change clock first */
228 if (mmc
->clock
&& mmc_config_clock(mmc
) != 0) {
229 mmchost
->fatal_err
= 1;
233 /* Change bus width */
234 if (mmc
->bus_width
== 8)
235 writel(0x2, &mmchost
->reg
->width
);
236 else if (mmc
->bus_width
== 4)
237 writel(0x1, &mmchost
->reg
->width
);
239 writel(0x0, &mmchost
->reg
->width
);
242 static int sunxi_mmc_core_init(struct mmc
*mmc
)
244 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
246 /* Reset controller */
247 writel(SUNXI_MMC_GCTRL_RESET
, &mmchost
->reg
->gctrl
);
253 static int mmc_trans_data_by_cpu(struct mmc
*mmc
, struct mmc_data
*data
)
255 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
256 const int reading
= !!(data
->flags
& MMC_DATA_READ
);
257 const uint32_t status_bit
= reading
? SUNXI_MMC_STATUS_FIFO_EMPTY
:
258 SUNXI_MMC_STATUS_FIFO_FULL
;
260 unsigned byte_cnt
= data
->blocksize
* data
->blocks
;
261 unsigned timeout_msecs
= 2000;
262 unsigned *buff
= (unsigned int *)(reading
? data
->dest
: data
->src
);
264 /* Always read / write data through the CPU */
265 setbits_le32(&mmchost
->reg
->gctrl
, SUNXI_MMC_GCTRL_ACCESS_BY_AHB
);
267 for (i
= 0; i
< (byte_cnt
>> 2); i
++) {
268 while (readl(&mmchost
->reg
->status
) & status_bit
) {
269 if (!timeout_msecs
--)
275 buff
[i
] = readl(&mmchost
->reg
->fifo
);
277 writel(buff
[i
], &mmchost
->reg
->fifo
);
283 static int mmc_rint_wait(struct mmc
*mmc
, unsigned int timeout_msecs
,
284 unsigned int done_bit
, const char *what
)
286 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
290 status
= readl(&mmchost
->reg
->rint
);
291 if (!timeout_msecs
-- ||
292 (status
& SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT
)) {
293 debug("%s timeout %x\n", what
,
294 status
& SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT
);
298 } while (!(status
& done_bit
));
303 static int sunxi_mmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
304 struct mmc_data
*data
)
306 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
307 unsigned int cmdval
= SUNXI_MMC_CMD_START
;
308 unsigned int timeout_msecs
;
310 unsigned int status
= 0;
311 unsigned int bytecnt
= 0;
313 if (mmchost
->fatal_err
)
315 if (cmd
->resp_type
& MMC_RSP_BUSY
)
316 debug("mmc cmd %d check rsp busy\n", cmd
->cmdidx
);
317 if (cmd
->cmdidx
== 12)
321 cmdval
|= SUNXI_MMC_CMD_SEND_INIT_SEQ
;
322 if (cmd
->resp_type
& MMC_RSP_PRESENT
)
323 cmdval
|= SUNXI_MMC_CMD_RESP_EXPIRE
;
324 if (cmd
->resp_type
& MMC_RSP_136
)
325 cmdval
|= SUNXI_MMC_CMD_LONG_RESPONSE
;
326 if (cmd
->resp_type
& MMC_RSP_CRC
)
327 cmdval
|= SUNXI_MMC_CMD_CHK_RESPONSE_CRC
;
330 if ((u32
) data
->dest
& 0x3) {
335 cmdval
|= SUNXI_MMC_CMD_DATA_EXPIRE
|SUNXI_MMC_CMD_WAIT_PRE_OVER
;
336 if (data
->flags
& MMC_DATA_WRITE
)
337 cmdval
|= SUNXI_MMC_CMD_WRITE
;
338 if (data
->blocks
> 1)
339 cmdval
|= SUNXI_MMC_CMD_AUTO_STOP
;
340 writel(data
->blocksize
, &mmchost
->reg
->blksz
);
341 writel(data
->blocks
* data
->blocksize
, &mmchost
->reg
->bytecnt
);
344 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost
->mmc_no
,
345 cmd
->cmdidx
, cmdval
| cmd
->cmdidx
, cmd
->cmdarg
);
346 writel(cmd
->cmdarg
, &mmchost
->reg
->arg
);
349 writel(cmdval
| cmd
->cmdidx
, &mmchost
->reg
->cmd
);
352 * transfer data and check status
353 * STATREG[2] : FIFO empty
354 * STATREG[3] : FIFO full
359 bytecnt
= data
->blocksize
* data
->blocks
;
360 debug("trans data %d bytes\n", bytecnt
);
361 writel(cmdval
| cmd
->cmdidx
, &mmchost
->reg
->cmd
);
362 ret
= mmc_trans_data_by_cpu(mmc
, data
);
364 error
= readl(&mmchost
->reg
->rint
) & \
365 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT
;
371 error
= mmc_rint_wait(mmc
, 1000, SUNXI_MMC_RINT_COMMAND_DONE
, "cmd");
377 debug("cacl timeout %x msec\n", timeout_msecs
);
378 error
= mmc_rint_wait(mmc
, timeout_msecs
,
380 SUNXI_MMC_RINT_AUTO_COMMAND_DONE
:
381 SUNXI_MMC_RINT_DATA_OVER
,
387 if (cmd
->resp_type
& MMC_RSP_BUSY
) {
388 timeout_msecs
= 2000;
390 status
= readl(&mmchost
->reg
->status
);
391 if (!timeout_msecs
--) {
392 debug("busy timeout\n");
397 } while (status
& SUNXI_MMC_STATUS_CARD_DATA_BUSY
);
400 if (cmd
->resp_type
& MMC_RSP_136
) {
401 cmd
->response
[0] = readl(&mmchost
->reg
->resp3
);
402 cmd
->response
[1] = readl(&mmchost
->reg
->resp2
);
403 cmd
->response
[2] = readl(&mmchost
->reg
->resp1
);
404 cmd
->response
[3] = readl(&mmchost
->reg
->resp0
);
405 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
406 cmd
->response
[3], cmd
->response
[2],
407 cmd
->response
[1], cmd
->response
[0]);
409 cmd
->response
[0] = readl(&mmchost
->reg
->resp0
);
410 debug("mmc resp 0x%08x\n", cmd
->response
[0]);
414 writel(SUNXI_MMC_GCTRL_RESET
, &mmchost
->reg
->gctrl
);
417 writel(0xffffffff, &mmchost
->reg
->rint
);
418 writel(readl(&mmchost
->reg
->gctrl
) | SUNXI_MMC_GCTRL_FIFO_RESET
,
419 &mmchost
->reg
->gctrl
);
424 static int sunxi_mmc_getcd(struct mmc
*mmc
)
426 struct sunxi_mmc_host
*mmchost
= mmc
->priv
;
429 cd_pin
= sunxi_mmc_getcd_gpio(mmchost
->mmc_no
);
433 return !gpio_get_value(cd_pin
);
436 int sunxi_mmc_has_egon_boot_signature(struct mmc
*mmc
)
438 char *buf
= malloc(512);
439 int valid_signature
= 0;
442 panic("Failed to allocate memory\n");
444 if (mmc_getcd(mmc
) && mmc_init(mmc
) == 0 &&
445 mmc
->block_dev
.block_read(mmc
->block_dev
.dev
, 16, 1, buf
) == 1 &&
446 strncmp(&buf
[4], "eGON.BT0", 8) == 0)
450 return valid_signature
;
453 static const struct mmc_ops sunxi_mmc_ops
= {
454 .send_cmd
= sunxi_mmc_send_cmd
,
455 .set_ios
= sunxi_mmc_set_ios
,
456 .init
= sunxi_mmc_core_init
,
457 .getcd
= sunxi_mmc_getcd
,
460 struct mmc
*sunxi_mmc_init(int sdc_no
)
462 struct mmc_config
*cfg
= &mmc_host
[sdc_no
].cfg
;
464 memset(&mmc_host
[sdc_no
], 0, sizeof(struct sunxi_mmc_host
));
466 cfg
->name
= "SUNXI SD/MMC";
467 cfg
->ops
= &sunxi_mmc_ops
;
469 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
470 cfg
->host_caps
= MMC_MODE_4BIT
;
471 cfg
->host_caps
|= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
472 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
475 cfg
->f_max
= 52000000;
477 if (mmc_resource_init(sdc_no
) != 0)
480 mmc_clk_io_on(sdc_no
);
482 return mmc_create(cfg
, &mmc_host
[sdc_no
]);