2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Jaehoon Chung <jh80.chung@samsung.com>
5 * Portions Copyright 2011-2015 NVIDIA Corporation
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <bouncebuf.h>
12 #include <dm/device.h>
16 #ifndef CONFIG_TEGRA186
17 #include <asm/arch/clock.h>
18 #include <asm/arch-tegra/clk_rst.h>
20 #include <asm/arch-tegra/mmc.h>
21 #include <asm/arch-tegra/tegra_mmc.h>
25 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
26 * should not be present. These are needed because newer Tegra SoCs support
27 * only the standard clock/reset APIs, whereas older Tegra SoCs support only
28 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
29 * fixed to implement the standard APIs, and all drivers converted to solely
30 * use the new standard APIs, with no ifdefs.
33 DECLARE_GLOBAL_DATA_PTR
;
35 struct mmc_host mmc_host
[CONFIG_SYS_MMC_MAX_DEVICE
];
37 #if !CONFIG_IS_ENABLED(OF_CONTROL)
38 #error "Please enable device tree support to use this driver"
41 static void mmc_set_power(struct mmc_host
*host
, unsigned short power
)
44 debug("%s: power = %x\n", __func__
, power
);
46 if (power
!= (unsigned short)-1) {
49 pwr
= TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8
;
53 pwr
= TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0
;
57 pwr
= TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3
;
61 debug("%s: pwr = %X\n", __func__
, pwr
);
63 /* Set the bus voltage first (if any) */
64 writeb(pwr
, &host
->reg
->pwrcon
);
68 /* Now enable bus power */
69 pwr
|= TEGRA_MMC_PWRCTL_SD_BUS_POWER
;
70 writeb(pwr
, &host
->reg
->pwrcon
);
73 static void mmc_prepare_data(struct mmc_host
*host
, struct mmc_data
*data
,
74 struct bounce_buffer
*bbstate
)
79 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
80 bbstate
->bounce_buffer
, bbstate
->user_buffer
, data
->blocks
,
83 writel((u32
)(unsigned long)bbstate
->bounce_buffer
, &host
->reg
->sysad
);
88 * 10 = Selects 32-bit Address ADMA2
89 * 11 = Selects 64-bit Address ADMA2
91 ctrl
= readb(&host
->reg
->hostctl
);
92 ctrl
&= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK
;
93 ctrl
|= TEGRA_MMC_HOSTCTL_DMASEL_SDMA
;
94 writeb(ctrl
, &host
->reg
->hostctl
);
96 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
97 writew((7 << 12) | (data
->blocksize
& 0xFFF), &host
->reg
->blksize
);
98 writew(data
->blocks
, &host
->reg
->blkcnt
);
101 static void mmc_set_transfer_mode(struct mmc_host
*host
, struct mmc_data
*data
)
104 debug(" mmc_set_transfer_mode called\n");
107 * MUL1SIN0[5] : Multi/Single Block Select
108 * RD1WT0[4] : Data Transfer Direction Select
111 * ENACMD12[2] : Auto CMD12 Enable
112 * ENBLKCNT[1] : Block Count Enable
113 * ENDMA[0] : DMA Enable
115 mode
= (TEGRA_MMC_TRNMOD_DMA_ENABLE
|
116 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE
);
118 if (data
->blocks
> 1)
119 mode
|= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT
;
121 if (data
->flags
& MMC_DATA_READ
)
122 mode
|= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ
;
124 writew(mode
, &host
->reg
->trnmod
);
127 static int mmc_wait_inhibit(struct mmc_host
*host
,
129 struct mmc_data
*data
,
130 unsigned int timeout
)
134 * CMDINHDAT[1] : Command Inhibit (DAT)
135 * CMDINHCMD[0] : Command Inhibit (CMD)
137 unsigned int mask
= TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD
;
140 * We shouldn't wait for data inhibit for stop commands, even
141 * though they might use busy signaling
143 if ((data
== NULL
) && (cmd
->resp_type
& MMC_RSP_BUSY
))
144 mask
|= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT
;
146 while (readl(&host
->reg
->prnsts
) & mask
) {
148 printf("%s: timeout error\n", __func__
);
158 static int mmc_send_cmd_bounced(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
159 struct mmc_data
*data
, struct bounce_buffer
*bbstate
)
161 struct mmc_host
*host
= mmc
->priv
;
164 unsigned int mask
= 0;
165 unsigned int retry
= 0x100000;
166 debug(" mmc_send_cmd called\n");
168 result
= mmc_wait_inhibit(host
, cmd
, data
, 10 /* ms */);
174 mmc_prepare_data(host
, data
, bbstate
);
176 debug("cmd->arg: %08x\n", cmd
->cmdarg
);
177 writel(cmd
->cmdarg
, &host
->reg
->argument
);
180 mmc_set_transfer_mode(host
, data
);
182 if ((cmd
->resp_type
& MMC_RSP_136
) && (cmd
->resp_type
& MMC_RSP_BUSY
))
187 * CMDIDX[13:8] : Command index
188 * DATAPRNT[5] : Data Present Select
189 * ENCMDIDX[4] : Command Index Check Enable
190 * ENCMDCRC[3] : Command CRC Check Enable
195 * 11 = Length 48 Check busy after response
197 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
198 flags
= TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE
;
199 else if (cmd
->resp_type
& MMC_RSP_136
)
200 flags
= TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136
;
201 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
202 flags
= TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY
;
204 flags
= TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48
;
206 if (cmd
->resp_type
& MMC_RSP_CRC
)
207 flags
|= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK
;
208 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
209 flags
|= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK
;
211 flags
|= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER
;
213 debug("cmd: %d\n", cmd
->cmdidx
);
215 writew((cmd
->cmdidx
<< 8) | flags
, &host
->reg
->cmdreg
);
217 for (i
= 0; i
< retry
; i
++) {
218 mask
= readl(&host
->reg
->norintsts
);
219 /* Command Complete */
220 if (mask
& TEGRA_MMC_NORINTSTS_CMD_COMPLETE
) {
222 writel(mask
, &host
->reg
->norintsts
);
228 printf("%s: waiting for status update\n", __func__
);
229 writel(mask
, &host
->reg
->norintsts
);
233 if (mask
& TEGRA_MMC_NORINTSTS_CMD_TIMEOUT
) {
235 debug("timeout: %08x cmd %d\n", mask
, cmd
->cmdidx
);
236 writel(mask
, &host
->reg
->norintsts
);
238 } else if (mask
& TEGRA_MMC_NORINTSTS_ERR_INTERRUPT
) {
239 /* Error Interrupt */
240 debug("error: %08x cmd %d\n", mask
, cmd
->cmdidx
);
241 writel(mask
, &host
->reg
->norintsts
);
245 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
246 if (cmd
->resp_type
& MMC_RSP_136
) {
247 /* CRC is stripped so we need to do some shifting. */
248 for (i
= 0; i
< 4; i
++) {
249 unsigned long offset
=
250 (unsigned long)(&host
->reg
->rspreg3
- i
);
251 cmd
->response
[i
] = readl(offset
) << 8;
257 debug("cmd->resp[%d]: %08x\n",
258 i
, cmd
->response
[i
]);
260 } else if (cmd
->resp_type
& MMC_RSP_BUSY
) {
261 for (i
= 0; i
< retry
; i
++) {
262 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
263 if (readl(&host
->reg
->prnsts
)
264 & (1 << 20)) /* DAT[0] */
269 printf("%s: card is still busy\n", __func__
);
270 writel(mask
, &host
->reg
->norintsts
);
274 cmd
->response
[0] = readl(&host
->reg
->rspreg0
);
275 debug("cmd->resp[0]: %08x\n", cmd
->response
[0]);
277 cmd
->response
[0] = readl(&host
->reg
->rspreg0
);
278 debug("cmd->resp[0]: %08x\n", cmd
->response
[0]);
283 unsigned long start
= get_timer(0);
286 mask
= readl(&host
->reg
->norintsts
);
288 if (mask
& TEGRA_MMC_NORINTSTS_ERR_INTERRUPT
) {
289 /* Error Interrupt */
290 writel(mask
, &host
->reg
->norintsts
);
291 printf("%s: error during transfer: 0x%08x\n",
294 } else if (mask
& TEGRA_MMC_NORINTSTS_DMA_INTERRUPT
) {
296 * DMA Interrupt, restart the transfer where
297 * it was interrupted.
299 unsigned int address
= readl(&host
->reg
->sysad
);
302 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT
,
303 &host
->reg
->norintsts
);
304 writel(address
, &host
->reg
->sysad
);
305 } else if (mask
& TEGRA_MMC_NORINTSTS_XFER_COMPLETE
) {
306 /* Transfer Complete */
307 debug("r/w is done\n");
309 } else if (get_timer(start
) > 8000UL) {
310 writel(mask
, &host
->reg
->norintsts
);
311 printf("%s: MMC Timeout\n"
312 " Interrupt status 0x%08x\n"
313 " Interrupt status enable 0x%08x\n"
314 " Interrupt signal enable 0x%08x\n"
315 " Present status 0x%08x\n",
317 readl(&host
->reg
->norintstsen
),
318 readl(&host
->reg
->norintsigen
),
319 readl(&host
->reg
->prnsts
));
323 writel(mask
, &host
->reg
->norintsts
);
330 static int tegra_mmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
331 struct mmc_data
*data
)
334 unsigned int bbflags
;
336 struct bounce_buffer bbstate
;
340 if (data
->flags
& MMC_DATA_READ
) {
342 bbflags
= GEN_BB_WRITE
;
344 buf
= (void *)data
->src
;
345 bbflags
= GEN_BB_READ
;
347 len
= data
->blocks
* data
->blocksize
;
349 bounce_buffer_start(&bbstate
, buf
, len
, bbflags
);
352 ret
= mmc_send_cmd_bounced(mmc
, cmd
, data
, &bbstate
);
355 bounce_buffer_stop(&bbstate
);
360 static void mmc_change_clock(struct mmc_host
*host
, uint clock
)
364 unsigned long timeout
;
366 debug(" mmc_change_clock called\n");
369 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
373 #ifdef CONFIG_TEGRA186
375 ulong rate
= clk_set_rate(&host
->clk
, clock
);
376 div
= (rate
+ clock
- 1) / clock
;
379 clock_adjust_periph_pll_div(host
->mmc_id
, CLOCK_ID_PERIPH
, clock
,
382 debug("div = %d\n", div
);
384 writew(0, &host
->reg
->clkcon
);
388 * SELFREQ[15:8] : base clock divided by value
389 * ENSDCLK[2] : SD Clock Enable
390 * STBLINTCLK[1] : Internal Clock Stable
391 * ENINTCLK[0] : Internal Clock Enable
394 clk
= ((div
<< TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT
) |
395 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE
);
396 writew(clk
, &host
->reg
->clkcon
);
400 while (!(readw(&host
->reg
->clkcon
) &
401 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE
)) {
403 printf("%s: timeout error\n", __func__
);
410 clk
|= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE
;
411 writew(clk
, &host
->reg
->clkcon
);
413 debug("mmc_change_clock: clkcon = %08X\n", clk
);
419 static void tegra_mmc_set_ios(struct mmc
*mmc
)
421 struct mmc_host
*host
= mmc
->priv
;
423 debug(" mmc_set_ios called\n");
425 debug("bus_width: %x, clock: %d\n", mmc
->bus_width
, mmc
->clock
);
427 /* Change clock first */
428 mmc_change_clock(host
, mmc
->clock
);
430 ctrl
= readb(&host
->reg
->hostctl
);
434 * 0 = Depend on WIDE4
440 if (mmc
->bus_width
== 8)
442 else if (mmc
->bus_width
== 4)
447 writeb(ctrl
, &host
->reg
->hostctl
);
448 debug("mmc_set_ios: hostctl = %08X\n", ctrl
);
451 static void mmc_reset(struct mmc_host
*host
, struct mmc
*mmc
)
453 unsigned int timeout
;
454 debug(" mmc_reset called\n");
457 * RSTALL[0] : Software reset for all
461 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL
, &host
->reg
->swrst
);
465 /* Wait max 100 ms */
468 /* hw clears the bit when it's done */
469 while (readb(&host
->reg
->swrst
) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL
) {
471 printf("%s: timeout error\n", __func__
);
478 /* Set SD bus voltage & enable bus power */
479 mmc_set_power(host
, fls(mmc
->cfg
->voltages
) - 1);
480 debug("%s: power control = %02X, host control = %02X\n", __func__
,
481 readb(&host
->reg
->pwrcon
), readb(&host
->reg
->hostctl
));
483 /* Make sure SDIO pads are set up */
487 static int tegra_mmc_core_init(struct mmc
*mmc
)
489 struct mmc_host
*host
= mmc
->priv
;
491 debug(" mmc_core_init called\n");
493 mmc_reset(host
, mmc
);
495 host
->version
= readw(&host
->reg
->hcver
);
496 debug("host version = %x\n", host
->version
);
499 writel(0xffffffff, &host
->reg
->norintstsen
);
500 writel(0xffffffff, &host
->reg
->norintsigen
);
502 writeb(0xe, &host
->reg
->timeoutcon
); /* TMCLK * 2^27 */
504 * NORMAL Interrupt Status Enable Register init
505 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
506 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
507 * [3] ENSTADMAINT : DMA boundary interrupt
508 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
509 * [0] ENSTACMDCMPLT : Command Complete Status Enable
511 mask
= readl(&host
->reg
->norintstsen
);
513 mask
|= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE
|
514 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE
|
515 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT
|
516 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY
|
517 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY
);
518 writel(mask
, &host
->reg
->norintstsen
);
521 * NORMAL Interrupt Signal Enable Register init
522 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
524 mask
= readl(&host
->reg
->norintsigen
);
526 mask
|= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE
;
527 writel(mask
, &host
->reg
->norintsigen
);
532 static int tegra_mmc_getcd(struct mmc
*mmc
)
534 struct mmc_host
*host
= mmc
->priv
;
536 debug("tegra_mmc_getcd called\n");
538 if (dm_gpio_is_valid(&host
->cd_gpio
))
539 return dm_gpio_get_value(&host
->cd_gpio
);
544 static const struct mmc_ops tegra_mmc_ops
= {
545 .send_cmd
= tegra_mmc_send_cmd
,
546 .set_ios
= tegra_mmc_set_ios
,
547 .init
= tegra_mmc_core_init
,
548 .getcd
= tegra_mmc_getcd
,
551 static int do_mmc_init(int dev_index
, bool removable
)
553 struct mmc_host
*host
;
555 #ifdef CONFIG_TEGRA186
559 /* DT should have been read & host config filled in */
560 host
= &mmc_host
[dev_index
];
564 debug(" do_mmc_init: index %d, bus width %d pwr_gpio %d cd_gpio %d\n",
565 dev_index
, host
->width
, gpio_get_number(&host
->pwr_gpio
),
566 gpio_get_number(&host
->cd_gpio
));
570 #ifdef CONFIG_TEGRA186
571 ret
= reset_assert(&host
->reset_ctl
);
574 ret
= clk_enable(&host
->clk
);
577 ret
= clk_set_rate(&host
->clk
, 20000000);
578 if (IS_ERR_VALUE(ret
))
580 ret
= reset_deassert(&host
->reset_ctl
);
584 clock_start_periph_pll(host
->mmc_id
, CLOCK_ID_PERIPH
, 20000000);
587 if (dm_gpio_is_valid(&host
->pwr_gpio
))
588 dm_gpio_set_value(&host
->pwr_gpio
, 1);
590 memset(&host
->cfg
, 0, sizeof(host
->cfg
));
592 host
->cfg
.name
= "Tegra SD/MMC";
593 host
->cfg
.ops
= &tegra_mmc_ops
;
595 host
->cfg
.voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
596 host
->cfg
.host_caps
= 0;
597 if (host
->width
== 8)
598 host
->cfg
.host_caps
|= MMC_MODE_8BIT
;
599 if (host
->width
>= 4)
600 host
->cfg
.host_caps
|= MMC_MODE_4BIT
;
601 host
->cfg
.host_caps
|= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
604 * min freq is for card identification, and is the highest
605 * low-speed SDIO card frequency (actually 400KHz)
606 * max freq is highest HS eMMC clock as per the SD/MMC spec
609 host
->cfg
.f_min
= 375000;
610 host
->cfg
.f_max
= 48000000;
612 host
->cfg
.b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
614 mmc
= mmc_create(&host
->cfg
, host
);
615 mmc
->block_dev
.removable
= removable
;
623 * Get the host address and peripheral ID for a node.
625 * @param blob fdt blob
626 * @param node Device index (0-3)
627 * @param host Structure to fill in (reg, width, mmc_id)
629 static int mmc_get_config(const void *blob
, int node
, struct mmc_host
*host
,
632 debug("%s: node = %d\n", __func__
, node
);
634 host
->enabled
= fdtdec_get_is_enabled(blob
, node
);
636 host
->reg
= (struct tegra_mmc
*)fdtdec_get_addr(blob
, node
, "reg");
637 if ((fdt_addr_t
)host
->reg
== FDT_ADDR_T_NONE
) {
638 debug("%s: no sdmmc base reg info found\n", __func__
);
639 return -FDT_ERR_NOTFOUND
;
642 #ifdef CONFIG_TEGRA186
645 * FIXME: This variable should go away when the MMC device
646 * actually is a udevice.
650 dev
.of_offset
= node
;
651 ret
= reset_get_by_name(&dev
, "sdhci", &host
->reset_ctl
);
653 debug("reset_get_by_name() failed: %d\n", ret
);
656 ret
= clk_get_by_index(&dev
, 0, &host
->clk
);
658 debug("clk_get_by_index() failed: %d\n", ret
);
663 host
->mmc_id
= clock_decode_periph_id(blob
, node
);
664 if (host
->mmc_id
== PERIPH_ID_NONE
) {
665 debug("%s: could not decode periph id\n", __func__
);
666 return -FDT_ERR_NOTFOUND
;
671 * NOTE: mmc->bus_width is determined by mmc.c dynamically.
672 * TBD: Override it with this value?
674 host
->width
= fdtdec_get_int(blob
, node
, "bus-width", 0);
676 debug("%s: no sdmmc width found\n", __func__
);
678 /* These GPIOs are optional */
679 gpio_request_by_name_nodev(blob
, node
, "cd-gpios", 0, &host
->cd_gpio
,
681 gpio_request_by_name_nodev(blob
, node
, "wp-gpios", 0, &host
->wp_gpio
,
683 gpio_request_by_name_nodev(blob
, node
, "power-gpios", 0,
684 &host
->pwr_gpio
, GPIOD_IS_OUT
);
685 *removablep
= !fdtdec_get_bool(blob
, node
, "non-removable");
687 debug("%s: found controller at %p, width = %d, periph_id = %d\n",
688 __func__
, host
->reg
, host
->width
,
689 #ifndef CONFIG_TEGRA186
699 * Process a list of nodes, adding them to our list of SDMMC ports.
701 * @param blob fdt blob
702 * @param node_list list of nodes to process (any <=0 are ignored)
703 * @param count number of nodes to process
704 * @return 0 if ok, -1 on error
706 static int process_nodes(const void *blob
, int node_list
[], int count
)
708 struct mmc_host
*host
;
712 debug("%s: count = %d\n", __func__
, count
);
714 /* build mmc_host[] for each controller */
715 for (i
= 0; i
< count
; i
++) {
723 if (mmc_get_config(blob
, node
, host
, &removable
)) {
724 printf("%s: failed to decode dev %d\n", __func__
, i
);
727 do_mmc_init(i
, removable
);
732 void tegra_mmc_init(void)
734 int node_list
[CONFIG_SYS_MMC_MAX_DEVICE
], count
;
735 const void *blob
= gd
->fdt_blob
;
736 debug("%s entry\n", __func__
);
738 /* See if any Tegra186 MMC controllers are present */
739 count
= fdtdec_find_aliases_for_id(blob
, "sdhci",
740 COMPAT_NVIDIA_TEGRA186_SDMMC
, node_list
,
741 CONFIG_SYS_MMC_MAX_DEVICE
);
742 debug("%s: count of Tegra186 sdhci nodes is %d\n", __func__
, count
);
743 if (process_nodes(blob
, node_list
, count
)) {
744 printf("%s: Error processing T186 mmc node(s)!\n", __func__
);
748 /* See if any Tegra210 MMC controllers are present */
749 count
= fdtdec_find_aliases_for_id(blob
, "sdhci",
750 COMPAT_NVIDIA_TEGRA210_SDMMC
, node_list
,
751 CONFIG_SYS_MMC_MAX_DEVICE
);
752 debug("%s: count of Tegra210 sdhci nodes is %d\n", __func__
, count
);
753 if (process_nodes(blob
, node_list
, count
)) {
754 printf("%s: Error processing T210 mmc node(s)!\n", __func__
);
758 /* See if any Tegra124 MMC controllers are present */
759 count
= fdtdec_find_aliases_for_id(blob
, "sdhci",
760 COMPAT_NVIDIA_TEGRA124_SDMMC
, node_list
,
761 CONFIG_SYS_MMC_MAX_DEVICE
);
762 debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__
, count
);
763 if (process_nodes(blob
, node_list
, count
)) {
764 printf("%s: Error processing T124 mmc node(s)!\n", __func__
);
768 /* See if any Tegra30 MMC controllers are present */
769 count
= fdtdec_find_aliases_for_id(blob
, "sdhci",
770 COMPAT_NVIDIA_TEGRA30_SDMMC
, node_list
,
771 CONFIG_SYS_MMC_MAX_DEVICE
);
772 debug("%s: count of T30 sdhci nodes is %d\n", __func__
, count
);
773 if (process_nodes(blob
, node_list
, count
)) {
774 printf("%s: Error processing T30 mmc node(s)!\n", __func__
);
778 /* Now look for any Tegra20 MMC controllers */
779 count
= fdtdec_find_aliases_for_id(blob
, "sdhci",
780 COMPAT_NVIDIA_TEGRA20_SDMMC
, node_list
,
781 CONFIG_SYS_MMC_MAX_DEVICE
);
782 debug("%s: count of T20 sdhci nodes is %d\n", __func__
, count
);
783 if (process_nodes(blob
, node_list
, count
)) {
784 printf("%s: Error processing T20 mmc node(s)!\n", __func__
);