drivers/mmc/tegra_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009 SAMSUNG Electronics
   4  * Minkyu Kang <mk7.kang@samsung.com>
   5  * Jaehoon Chung <jh80.chung@samsung.com>
   6  * Portions Copyright 2011-2019 NVIDIA Corporation
   7  */
   8
   9 #include <bouncebuf.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <mmc.h>
  15 #include <asm/gpio.h>
  16 #include <asm/io.h>
  17 #include <asm/arch-tegra/tegra_mmc.h>
  18 #include <linux/bitops.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
  22 #include <asm/arch/clock.h>
  23 #endif
  24
  25 struct tegra_mmc_plat {
  26         struct mmc_config cfg;
  27         struct mmc mmc;
  28 };
  29
  30 struct tegra_mmc_priv {
  31         struct tegra_mmc *reg;
  32         struct reset_ctl reset_ctl;
  33         struct clk clk;
  34         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  35         struct gpio_desc pwr_gpio;      /* Power GPIO */
  36         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  37         unsigned int version;   /* SDHCI spec. version */
  38         unsigned int clock;     /* Current clock (MHz) */
  39         int mmc_id;             /* peripheral id */
  40 };
  41
  42 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
  43                                 unsigned short power)
  44 {
  45         u8 pwr = 0;
  46         debug("%s: power = %x\n", __func__, power);
  47
  48         if (power != (unsigned short)-1) {
  49                 switch (1 << power) {
  50                 case MMC_VDD_165_195:
  51                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
  52                         break;
  53                 case MMC_VDD_29_30:
  54                 case MMC_VDD_30_31:
  55                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
  56                         break;
  57                 case MMC_VDD_32_33:
  58                 case MMC_VDD_33_34:
  59                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
  60                         break;
  61                 }
  62         }
  63         debug("%s: pwr = %X\n", __func__, pwr);
  64
  65         /* Set the bus voltage first (if any) */
  66         writeb(pwr, &priv->reg->pwrcon);
  67         if (pwr == 0)
  68                 return;
  69
  70         /* Now enable bus power */
  71         pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
  72         writeb(pwr, &priv->reg->pwrcon);
  73 }
  74
  75 static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
  76                                    struct mmc_data *data,
  77                                    struct bounce_buffer *bbstate)
  78 {
  79         unsigned char ctrl;
  80
  81
  82         debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
  83                 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
  84                 data->blocksize);
  85
  86         writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
  87         /*
  88          * DMASEL[4:3]
  89          * 00 = Selects SDMA
  90          * 01 = Reserved
  91          * 10 = Selects 32-bit Address ADMA2
  92          * 11 = Selects 64-bit Address ADMA2
  93          */
  94         ctrl = readb(&priv->reg->hostctl);
  95         ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  96         ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  97         writeb(ctrl, &priv->reg->hostctl);
  98
  99         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 100         writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
 101         writew(data->blocks, &priv->reg->blkcnt);
 102 }
 103
 104 static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
 105                                         struct mmc_data *data)
 106 {
 107         unsigned short mode;
 108         debug(" mmc_set_transfer_mode called\n");
 109         /*
 110          * TRNMOD
 111          * MUL1SIN0[5]  : Multi/Single Block Select
 112          * RD1WT0[4]    : Data Transfer Direction Select
 113          *      1 = read
 114          *      0 = write
 115          * ENACMD12[2]  : Auto CMD12 Enable
 116          * ENBLKCNT[1]  : Block Count Enable
 117          * ENDMA[0]     : DMA Enable
 118          */
 119         mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
 120                 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
 121
 122         if (data->blocks > 1)
 123                 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
 124
 125         if (data->flags & MMC_DATA_READ)
 126                 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
 127
 128         writew(mode, &priv->reg->trnmod);
 129 }
 130
 131 static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
 132                                   struct mmc_cmd *cmd,
 133                                   struct mmc_data *data,
 134                                   unsigned int timeout)
 135 {
 136         /*
 137          * PRNSTS
 138          * CMDINHDAT[1] : Command Inhibit (DAT)
 139          * CMDINHCMD[0] : Command Inhibit (CMD)
 140          */
 141         unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
 142
 143         /*
 144          * We shouldn't wait for data inhibit for stop commands, even
 145          * though they might use busy signaling
 146          */
 147         if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
 148                 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
 149
 150         while (readl(&priv->reg->prnsts) & mask) {
 151                 if (timeout == 0) {
 152                         printf("%s: timeout error\n", __func__);
 153                         return -1;
 154                 }
 155                 timeout--;
 156                 udelay(1000);
 157         }
 158
 159         return 0;
 160 }
 161
 162 static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
 163                                       struct mmc_data *data,
 164                                       struct bounce_buffer *bbstate)
 165 {
 166         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 167         int flags, i;
 168         int result;
 169         unsigned int mask = 0;
 170         unsigned int retry = 0x100000;
 171         debug(" mmc_send_cmd called\n");
 172
 173         result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
 174
 175         if (result < 0)
 176                 return result;
 177
 178         if (data)
 179                 tegra_mmc_prepare_data(priv, data, bbstate);
 180
 181         debug("cmd->arg: %08x\n", cmd->cmdarg);
 182         writel(cmd->cmdarg, &priv->reg->argument);
 183
 184         if (data)
 185                 tegra_mmc_set_transfer_mode(priv, data);
 186
 187         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 188                 return -1;
 189
 190         /*
 191          * CMDREG
 192          * CMDIDX[13:8] : Command index
 193          * DATAPRNT[5]  : Data Present Select
 194          * ENCMDIDX[4]  : Command Index Check Enable
 195          * ENCMDCRC[3]  : Command CRC Check Enable
 196          * RSPTYP[1:0]
 197          *      00 = No Response
 198          *      01 = Length 136
 199          *      10 = Length 48
 200          *      11 = Length 48 Check busy after response
 201          */
 202         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 203                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
 204         else if (cmd->resp_type & MMC_RSP_136)
 205                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
 206         else if (cmd->resp_type & MMC_RSP_BUSY)
 207                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
 208         else
 209                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
 210
 211         if (cmd->resp_type & MMC_RSP_CRC)
 212                 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
 213         if (cmd->resp_type & MMC_RSP_OPCODE)
 214                 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
 215         if (data)
 216                 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
 217
 218         debug("cmd: %d\n", cmd->cmdidx);
 219
 220         writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
 221
 222         for (i = 0; i < retry; i++) {
 223                 mask = readl(&priv->reg->norintsts);
 224                 /* Command Complete */
 225                 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
 226                         if (!data)
 227                                 writel(mask, &priv->reg->norintsts);
 228                         break;
 229                 }
 230         }
 231
 232         if (i == retry) {
 233                 printf("%s: waiting for status update\n", __func__);
 234                 writel(mask, &priv->reg->norintsts);
 235                 return -ETIMEDOUT;
 236         }
 237
 238         if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
 239                 /* Timeout Error */
 240                 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
 241                 writel(mask, &priv->reg->norintsts);
 242                 return -ETIMEDOUT;
 243         } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 244                 /* Error Interrupt */
 245                 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
 246                 writel(mask, &priv->reg->norintsts);
 247                 return -1;
 248         }
 249
 250         if (cmd->resp_type & MMC_RSP_PRESENT) {
 251                 if (cmd->resp_type & MMC_RSP_136) {
 252                         /* CRC is stripped so we need to do some shifting. */
 253                         for (i = 0; i < 4; i++) {
 254                                 unsigned long offset = (unsigned long)
 255                                         (&priv->reg->rspreg3 - i);
 256                                 cmd->response[i] = readl(offset) << 8;
 257
 258                                 if (i != 3) {
 259                                         cmd->response[i] |=
 260                                                 readb(offset - 1);
 261                                 }
 262                                 debug("cmd->resp[%d]: %08x\n",
 263                                                 i, cmd->response[i]);
 264                         }
 265                 } else if (cmd->resp_type & MMC_RSP_BUSY) {
 266                         for (i = 0; i < retry; i++) {
 267                                 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
 268                                 if (readl(&priv->reg->prnsts)
 269                                         & (1 << 20))    /* DAT[0] */
 270                                         break;
 271                         }
 272
 273                         if (i == retry) {
 274                                 printf("%s: card is still busy\n", __func__);
 275                                 writel(mask, &priv->reg->norintsts);
 276                                 return -ETIMEDOUT;
 277                         }
 278
 279                         cmd->response[0] = readl(&priv->reg->rspreg0);
 280                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 281                 } else {
 282                         cmd->response[0] = readl(&priv->reg->rspreg0);
 283                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 284                 }
 285         }
 286
 287         if (data) {
 288                 unsigned long   start = get_timer(0);
 289
 290                 while (1) {
 291                         mask = readl(&priv->reg->norintsts);
 292
 293                         if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 294                                 /* Error Interrupt */
 295                                 writel(mask, &priv->reg->norintsts);
 296                                 printf("%s: error during transfer: 0x%08x\n",
 297                                                 __func__, mask);
 298                                 return -1;
 299                         } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
 300                                 /*
 301                                  * DMA Interrupt, restart the transfer where
 302                                  * it was interrupted.
 303                                  */
 304                                 unsigned int address = readl(&priv->reg->sysad);
 305
 306                                 debug("DMA end\n");
 307                                 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
 308                                        &priv->reg->norintsts);
 309                                 writel(address, &priv->reg->sysad);
 310                         } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
 311                                 /* Transfer Complete */
 312                                 debug("r/w is done\n");
 313                                 break;
 314                         } else if (get_timer(start) > 8000UL) {
 315                                 writel(mask, &priv->reg->norintsts);
 316                                 printf("%s: MMC Timeout\n"
 317                                        "    Interrupt status        0x%08x\n"
 318                                        "    Interrupt status enable 0x%08x\n"
 319                                        "    Interrupt signal enable 0x%08x\n"
 320                                        "    Present status          0x%08x\n",
 321                                        __func__, mask,
 322                                        readl(&priv->reg->norintstsen),
 323                                        readl(&priv->reg->norintsigen),
 324                                        readl(&priv->reg->prnsts));
 325                                 return -1;
 326                         }
 327                 }
 328                 writel(mask, &priv->reg->norintsts);
 329         }
 330
 331         udelay(1000);
 332         return 0;
 333 }
 334
 335 static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 336                               struct mmc_data *data)
 337 {
 338         void *buf;
 339         unsigned int bbflags;
 340         size_t len;
 341         struct bounce_buffer bbstate;
 342         int ret;
 343
 344         if (data) {
 345                 if (data->flags & MMC_DATA_READ) {
 346                         buf = data->dest;
 347                         bbflags = GEN_BB_WRITE;
 348                 } else {
 349                         buf = (void *)data->src;
 350                         bbflags = GEN_BB_READ;
 351                 }
 352                 len = data->blocks * data->blocksize;
 353
 354                 bounce_buffer_start(&bbstate, buf, len, bbflags);
 355         }
 356
 357         ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
 358
 359         if (data)
 360                 bounce_buffer_stop(&bbstate);
 361
 362         return ret;
 363 }
 364
 365 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
 366 {
 367         ulong rate;
 368         int div;
 369         unsigned short clk;
 370         unsigned long timeout;
 371
 372         debug(" mmc_change_clock called\n");
 373
 374         /*
 375          * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
 376          */
 377         if (clock == 0)
 378                 goto out;
 379
 380         rate = clk_set_rate(&priv->clk, clock);
 381         div = (rate + clock - 1) / clock;
 382
 383 #if defined(CONFIG_TEGRA210)
 384         if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
 385                 /* clock_adjust_periph_pll_div() chooses a 'bad' clock
 386                  * on SDMMC1 T210, so skip it here and force a clock
 387                  * that's been spec'd in the table in the TRM for
 388                  * card-detect (400KHz).
 389                  */
 390                 uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
 391                                 CLOCK_ID_PERIPH, 24727273, NULL);
 392                 div = 62;
 393
 394                 debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
 395                       __func__, effective_rate, div, clock);
 396         } else {
 397                 clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
 398                                             clock, &div);
 399         }
 400 #endif
 401         debug("div = %d\n", div);
 402
 403         writew(0, &priv->reg->clkcon);
 404
 405         /*
 406          * CLKCON
 407          * SELFREQ[15:8]        : base clock divided by value
 408          * ENSDCLK[2]           : SD Clock Enable
 409          * STBLINTCLK[1]        : Internal Clock Stable
 410          * ENINTCLK[0]          : Internal Clock Enable
 411          */
 412         div >>= 1;
 413         clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
 414                TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
 415         writew(clk, &priv->reg->clkcon);
 416
 417         /* Wait max 10 ms */
 418         timeout = 10;
 419         while (!(readw(&priv->reg->clkcon) &
 420                  TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
 421                 if (timeout == 0) {
 422                         printf("%s: timeout error\n", __func__);
 423                         return;
 424                 }
 425                 timeout--;
 426                 udelay(1000);
 427         }
 428
 429         clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 430         writew(clk, &priv->reg->clkcon);
 431
 432         debug("mmc_change_clock: clkcon = %08X\n", clk);
 433
 434 out:
 435         priv->clock = clock;
 436 }
 437
 438 static int tegra_mmc_set_ios(struct udevice *dev)
 439 {
 440         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 441         struct mmc *mmc = mmc_get_mmc_dev(dev);
 442         unsigned char ctrl;
 443         debug(" mmc_set_ios called\n");
 444
 445         debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
 446
 447         /* Change clock first */
 448         tegra_mmc_change_clock(priv, mmc->clock);
 449
 450         ctrl = readb(&priv->reg->hostctl);
 451
 452         /*
 453          * WIDE8[5]
 454          * 0 = Depend on WIDE4
 455          * 1 = 8-bit mode
 456          * WIDE4[1]
 457          * 1 = 4-bit mode
 458          * 0 = 1-bit mode
 459          */
 460         if (mmc->bus_width == 8)
 461                 ctrl |= (1 << 5);
 462         else if (mmc->bus_width == 4)
 463                 ctrl |= (1 << 1);
 464         else
 465                 ctrl &= ~(1 << 1 | 1 << 5);
 466
 467         writeb(ctrl, &priv->reg->hostctl);
 468         debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 469
 470         return 0;
 471 }
 472
 473 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
 474 {
 475 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
 476         u32 val;
 477         u16 clk_con;
 478         int timeout;
 479         int id = priv->mmc_id;
 480
 481         debug("%s: sdmmc address = %p, id = %d\n", __func__,
 482                 priv->reg, id);
 483
 484         /* Set the pad drive strength for SDMMC1 or 3 only */
 485         if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
 486                 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
 487                         __func__);
 488                 return;
 489         }
 490
 491         val = readl(&priv->reg->sdmemcmppadctl);
 492         val &= 0xFFFFFFF0;
 493         val |= MEMCOMP_PADCTRL_VREF;
 494         writel(val, &priv->reg->sdmemcmppadctl);
 495
 496         /* Disable SD Clock Enable before running auto-cal as per TRM */
 497         clk_con = readw(&priv->reg->clkcon);
 498         debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
 499         clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 500         writew(clk_con, &priv->reg->clkcon);
 501
 502         val = readl(&priv->reg->autocalcfg);
 503         val &= 0xFFFF0000;
 504         val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
 505         writel(val, &priv->reg->autocalcfg);
 506         val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
 507         writel(val, &priv->reg->autocalcfg);
 508         debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
 509         udelay(1);
 510         timeout = 100;                          /* 10 mSec max (100*100uS) */
 511         do {
 512                 val = readl(&priv->reg->autocalsts);
 513                 udelay(100);
 514         } while ((val & AUTO_CAL_ACTIVE) && --timeout);
 515         val = readl(&priv->reg->autocalsts);
 516         debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
 517               __func__, val, timeout);
 518
 519         /* Re-enable SD Clock Enable when auto-cal is done */
 520         clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 521         writew(clk_con, &priv->reg->clkcon);
 522         clk_con = readw(&priv->reg->clkcon);
 523         debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
 524
 525         if (timeout == 0) {
 526                 printf("%s: Warning: Autocal timed out!\n", __func__);
 527                 /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
 528         }
 529
 530 #if defined(CONFIG_TEGRA210)
 531         u32 tap_value, trim_value;
 532
 533         /* Set tap/trim values for SDMMC1/3 @ <48MHz here */
 534         val = readl(&priv->reg->venspictl);     /* aka VENDOR_SYS_SW_CNTL */
 535         val &= IO_TRIM_BYPASS_MASK;
 536         if (id == PERIPH_ID_SDMMC1) {
 537                 tap_value = 4;                  /* default */
 538                 if (val)
 539                         tap_value = 3;
 540                 trim_value = 2;
 541         } else {                                /* SDMMC3 */
 542                 tap_value = 3;
 543                 trim_value = 3;
 544         }
 545
 546         val = readl(&priv->reg->venclkctl);
 547         val &= ~TRIM_VAL_MASK;
 548         val |= (trim_value << TRIM_VAL_SHIFT);
 549         val &= ~TAP_VAL_MASK;
 550         val |= (tap_value << TAP_VAL_SHIFT);
 551         writel(val, &priv->reg->venclkctl);
 552         debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
 553 #endif  /* T210 */
 554 #endif  /* T30/T210 */
 555 }
 556
 557 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
 558 {
 559         unsigned int timeout;
 560         debug(" mmc_reset called\n");
 561
 562         /*
 563          * RSTALL[0] : Software reset for all
 564          * 1 = reset
 565          * 0 = work
 566          */
 567         writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
 568
 569         priv->clock = 0;
 570
 571         /* Wait max 100 ms */
 572         timeout = 100;
 573
 574         /* hw clears the bit when it's done */
 575         while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
 576                 if (timeout == 0) {
 577                         printf("%s: timeout error\n", __func__);
 578                         return;
 579                 }
 580                 timeout--;
 581                 udelay(1000);
 582         }
 583
 584         /* Set SD bus voltage & enable bus power */
 585         tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
 586         debug("%s: power control = %02X, host control = %02X\n", __func__,
 587                 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
 588
 589         /* Make sure SDIO pads are set up */
 590         tegra_mmc_pad_init(priv);
 591 }
 592
 593 static int tegra_mmc_init(struct udevice *dev)
 594 {
 595         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 596         struct mmc *mmc = mmc_get_mmc_dev(dev);
 597         unsigned int mask;
 598         debug(" tegra_mmc_init called\n");
 599
 600 #if defined(CONFIG_TEGRA210)
 601         priv->mmc_id = clock_decode_periph_id(dev);
 602         if (priv->mmc_id == PERIPH_ID_NONE) {
 603                 printf("%s: Missing/invalid peripheral ID\n", __func__);
 604                 return -EINVAL;
 605         }
 606 #endif
 607         tegra_mmc_reset(priv, mmc);
 608
 609 #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
 610         /*
 611          * Disable the external clock loopback and use the internal one on
 612          * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
 613          * bits being set to 0xfffd according to the TRM.
 614          *
 615          * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
 616          * approach once proper kernel integration made it mainline.
 617          */
 618         if (priv->reg == (void *)0x700b0400) {
 619                 mask = readl(&priv->reg->venmiscctl);
 620                 mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
 621                 writel(mask, &priv->reg->venmiscctl);
 622         }
 623 #endif
 624
 625         priv->version = readw(&priv->reg->hcver);
 626         debug("host version = %x\n", priv->version);
 627
 628         /* mask all */
 629         writel(0xffffffff, &priv->reg->norintstsen);
 630         writel(0xffffffff, &priv->reg->norintsigen);
 631
 632         writeb(0xe, &priv->reg->timeoutcon);    /* TMCLK * 2^27 */
 633         /*
 634          * NORMAL Interrupt Status Enable Register init
 635          * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
 636          * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
 637          * [3] ENSTADMAINT   : DMA boundary interrupt
 638          * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
 639          * [0] ENSTACMDCMPLT : Command Complete Status Enable
 640         */
 641         mask = readl(&priv->reg->norintstsen);
 642         mask &= ~(0xffff);
 643         mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
 644                  TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
 645                  TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
 646                  TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
 647                  TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
 648         writel(mask, &priv->reg->norintstsen);
 649
 650         /*
 651          * NORMAL Interrupt Signal Enable Register init
 652          * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
 653          */
 654         mask = readl(&priv->reg->norintsigen);
 655         mask &= ~(0xffff);
 656         mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
 657         writel(mask, &priv->reg->norintsigen);
 658
 659         return 0;
 660 }
 661
 662 static int tegra_mmc_getcd(struct udevice *dev)
 663 {
 664         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 665
 666         debug("tegra_mmc_getcd called\n");
 667
 668         if (dm_gpio_is_valid(&priv->cd_gpio))
 669                 return dm_gpio_get_value(&priv->cd_gpio);
 670
 671         return 1;
 672 }
 673
 674 static const struct dm_mmc_ops tegra_mmc_ops = {
 675         .send_cmd       = tegra_mmc_send_cmd,
 676         .set_ios        = tegra_mmc_set_ios,
 677         .get_cd         = tegra_mmc_getcd,
 678 };
 679
 680 static int tegra_mmc_probe(struct udevice *dev)
 681 {
 682         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 683         struct tegra_mmc_plat *plat = dev_get_plat(dev);
 684         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 685         struct mmc_config *cfg = &plat->cfg;
 686         int bus_width, ret;
 687
 688         cfg->name = dev->name;
 689
 690         bus_width = dev_read_u32_default(dev, "bus-width", 1);
 691
 692         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 693         cfg->host_caps = 0;
 694         if (bus_width == 8)
 695                 cfg->host_caps |= MMC_MODE_8BIT;
 696         if (bus_width >= 4)
 697                 cfg->host_caps |= MMC_MODE_4BIT;
 698         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 699
 700         /*
 701          * min freq is for card identification, and is the highest
 702          *  low-speed SDIO card frequency (actually 400KHz)
 703          * max freq is highest HS eMMC clock as per the SD/MMC spec
 704          *  (actually 52MHz)
 705          */
 706         cfg->f_min = 375000;
 707         cfg->f_max = 48000000;
 708
 709         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 710
 711         priv->reg = dev_read_addr_ptr(dev);
 712
 713         ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
 714         if (ret) {
 715                 debug("reset_get_by_name() failed: %d\n", ret);
 716                 return ret;
 717         }
 718         ret = clk_get_by_index(dev, 0, &priv->clk);
 719         if (ret) {
 720                 debug("clk_get_by_index() failed: %d\n", ret);
 721                 return ret;
 722         }
 723
 724         ret = reset_assert(&priv->reset_ctl);
 725         if (ret)
 726                 return ret;
 727         ret = clk_enable(&priv->clk);
 728         if (ret)
 729                 return ret;
 730         ret = clk_set_rate(&priv->clk, 20000000);
 731         if (IS_ERR_VALUE(ret))
 732                 return ret;
 733         ret = reset_deassert(&priv->reset_ctl);
 734         if (ret)
 735                 return ret;
 736
 737         /* These GPIOs are optional */
 738         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
 739         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
 740         gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
 741                              GPIOD_IS_OUT);
 742         if (dm_gpio_is_valid(&priv->pwr_gpio))
 743                 dm_gpio_set_value(&priv->pwr_gpio, 1);
 744
 745         upriv->mmc = &plat->mmc;
 746
 747         return tegra_mmc_init(dev);
 748 }
 749
 750 static int tegra_mmc_bind(struct udevice *dev)
 751 {
 752         struct tegra_mmc_plat *plat = dev_get_plat(dev);
 753
 754         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 755 }
 756
 757 static const struct udevice_id tegra_mmc_ids[] = {
 758         { .compatible = "nvidia,tegra20-sdhci" },
 759         { .compatible = "nvidia,tegra30-sdhci" },
 760         { .compatible = "nvidia,tegra114-sdhci" },
 761         { .compatible = "nvidia,tegra124-sdhci" },
 762         { .compatible = "nvidia,tegra210-sdhci" },
 763         { .compatible = "nvidia,tegra186-sdhci" },
 764         { }
 765 };
 766
 767 U_BOOT_DRIVER(tegra_mmc_drv) = {
 768         .name           = "tegra_mmc",
 769         .id             = UCLASS_MMC,
 770         .of_match       = tegra_mmc_ids,
 771         .bind           = tegra_mmc_bind,
 772         .probe          = tegra_mmc_probe,
 773         .ops            = &tegra_mmc_ops,
 774         .plat_auto      = sizeof(struct tegra_mmc_plat),
 775         .priv_auto      = sizeof(struct tegra_mmc_priv),
 776 };