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dm: core: Create a new header file for 'compat' features
[thirdparty/u-boot.git] / drivers / mmc / tmio-common.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 */
6
7 #include <asm/dma-mapping.h>
8 #include <common.h>
9 #include <clk.h>
10 #include <cpu_func.h>
11 #include <fdtdec.h>
12 #include <mmc.h>
13 #include <dm.h>
14 #include <dm/device_compat.h>
15 #include <dm/pinctrl.h>
16 #include <linux/compat.h>
17 #include <linux/dma-direction.h>
18 #include <linux/io.h>
19 #include <linux/sizes.h>
20 #include <power/regulator.h>
21 #include <asm/unaligned.h>
22
23 #include "tmio-common.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
28 {
29 return readq(priv->regbase + (reg << 1));
30 }
31
32 static void tmio_sd_writeq(struct tmio_sd_priv *priv,
33 u64 val, unsigned int reg)
34 {
35 writeq(val, priv->regbase + (reg << 1));
36 }
37
38 static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
39 {
40 return readw(priv->regbase + (reg >> 1));
41 }
42
43 static void tmio_sd_writew(struct tmio_sd_priv *priv,
44 u16 val, unsigned int reg)
45 {
46 writew(val, priv->regbase + (reg >> 1));
47 }
48
49 u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
50 {
51 u32 val;
52
53 if (priv->caps & TMIO_SD_CAP_64BIT)
54 return readl(priv->regbase + (reg << 1));
55 else if (priv->caps & TMIO_SD_CAP_16BIT) {
56 val = readw(priv->regbase + (reg >> 1)) & 0xffff;
57 if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
58 (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
59 val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
60 }
61 return val;
62 } else
63 return readl(priv->regbase + reg);
64 }
65
66 void tmio_sd_writel(struct tmio_sd_priv *priv,
67 u32 val, unsigned int reg)
68 {
69 if (priv->caps & TMIO_SD_CAP_64BIT)
70 writel(val, priv->regbase + (reg << 1));
71 else if (priv->caps & TMIO_SD_CAP_16BIT) {
72 writew(val & 0xffff, priv->regbase + (reg >> 1));
73 if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
74 reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
75 reg == TMIO_SD_ARG)
76 writew(val >> 16, priv->regbase + (reg >> 1) + 2);
77 } else
78 writel(val, priv->regbase + reg);
79 }
80
81 static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
82 {
83 struct tmio_sd_priv *priv = dev_get_priv(dev);
84 u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
85
86 if (info2 & TMIO_SD_INFO2_ERR_RTO) {
87 /*
88 * TIMEOUT must be returned for unsupported command. Do not
89 * display error log since this might be a part of sequence to
90 * distinguish between SD and MMC.
91 */
92 return -ETIMEDOUT;
93 }
94
95 if (info2 & TMIO_SD_INFO2_ERR_TO) {
96 dev_err(dev, "timeout error\n");
97 return -ETIMEDOUT;
98 }
99
100 if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
101 TMIO_SD_INFO2_ERR_IDX)) {
102 if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
103 (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
104 dev_err(dev, "communication out of sync\n");
105 return -EILSEQ;
106 }
107
108 if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
109 TMIO_SD_INFO2_ERR_ILW)) {
110 dev_err(dev, "illegal access\n");
111 return -EIO;
112 }
113
114 return 0;
115 }
116
117 static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
118 unsigned int reg, u32 flag)
119 {
120 struct tmio_sd_priv *priv = dev_get_priv(dev);
121 long wait = 1000000;
122 int ret;
123
124 while (!(tmio_sd_readl(priv, reg) & flag)) {
125 if (wait-- < 0) {
126 dev_err(dev, "timeout\n");
127 return -ETIMEDOUT;
128 }
129
130 ret = tmio_sd_check_error(dev, cmd);
131 if (ret)
132 return ret;
133
134 udelay(1);
135 }
136
137 return 0;
138 }
139
140 #define tmio_pio_read_fifo(__width, __suffix) \
141 static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
142 char *pbuf, uint blksz) \
143 { \
144 u##__width *buf = (u##__width *)pbuf; \
145 int i; \
146 \
147 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
148 for (i = 0; i < blksz / ((__width) / 8); i++) { \
149 *buf++ = tmio_sd_read##__suffix(priv, \
150 TMIO_SD_BUF); \
151 } \
152 } else { \
153 for (i = 0; i < blksz / ((__width) / 8); i++) { \
154 u##__width data; \
155 data = tmio_sd_read##__suffix(priv, \
156 TMIO_SD_BUF); \
157 put_unaligned(data, buf++); \
158 } \
159 } \
160 }
161
162 tmio_pio_read_fifo(64, q)
163 tmio_pio_read_fifo(32, l)
164 tmio_pio_read_fifo(16, w)
165
166 static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
167 char *pbuf, uint blocksize)
168 {
169 struct tmio_sd_priv *priv = dev_get_priv(dev);
170 int ret;
171
172 /* wait until the buffer is filled with data */
173 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
174 TMIO_SD_INFO2_BRE);
175 if (ret)
176 return ret;
177
178 /*
179 * Clear the status flag _before_ read the buffer out because
180 * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
181 */
182 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
183
184 if (priv->caps & TMIO_SD_CAP_64BIT)
185 tmio_pio_read_fifo_64(priv, pbuf, blocksize);
186 else if (priv->caps & TMIO_SD_CAP_16BIT)
187 tmio_pio_read_fifo_16(priv, pbuf, blocksize);
188 else
189 tmio_pio_read_fifo_32(priv, pbuf, blocksize);
190
191 return 0;
192 }
193
194 #define tmio_pio_write_fifo(__width, __suffix) \
195 static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
196 const char *pbuf, uint blksz)\
197 { \
198 const u##__width *buf = (const u##__width *)pbuf; \
199 int i; \
200 \
201 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
202 for (i = 0; i < blksz / ((__width) / 8); i++) { \
203 tmio_sd_write##__suffix(priv, *buf++, \
204 TMIO_SD_BUF); \
205 } \
206 } else { \
207 for (i = 0; i < blksz / ((__width) / 8); i++) { \
208 u##__width data = get_unaligned(buf++); \
209 tmio_sd_write##__suffix(priv, data, \
210 TMIO_SD_BUF); \
211 } \
212 } \
213 }
214
215 tmio_pio_write_fifo(64, q)
216 tmio_pio_write_fifo(32, l)
217 tmio_pio_write_fifo(16, w)
218
219 static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
220 const char *pbuf, uint blocksize)
221 {
222 struct tmio_sd_priv *priv = dev_get_priv(dev);
223 int ret;
224
225 /* wait until the buffer becomes empty */
226 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
227 TMIO_SD_INFO2_BWE);
228 if (ret)
229 return ret;
230
231 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
232
233 if (priv->caps & TMIO_SD_CAP_64BIT)
234 tmio_pio_write_fifo_64(priv, pbuf, blocksize);
235 else if (priv->caps & TMIO_SD_CAP_16BIT)
236 tmio_pio_write_fifo_16(priv, pbuf, blocksize);
237 else
238 tmio_pio_write_fifo_32(priv, pbuf, blocksize);
239
240 return 0;
241 }
242
243 static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
244 struct mmc_data *data)
245 {
246 const char *src = data->src;
247 char *dest = data->dest;
248 int i, ret;
249
250 for (i = 0; i < data->blocks; i++) {
251 if (data->flags & MMC_DATA_READ)
252 ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
253 data->blocksize);
254 else
255 ret = tmio_sd_pio_write_one_block(dev, cmd, src,
256 data->blocksize);
257 if (ret)
258 return ret;
259
260 if (data->flags & MMC_DATA_READ)
261 dest += data->blocksize;
262 else
263 src += data->blocksize;
264 }
265
266 return 0;
267 }
268
269 static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
270 dma_addr_t dma_addr)
271 {
272 u32 tmp;
273
274 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
275 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
276
277 /* enable DMA */
278 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
279 tmp |= TMIO_SD_EXTMODE_DMA_EN;
280 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
281
282 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
283
284 /* suppress the warning "right shift count >= width of type" */
285 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
286
287 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
288
289 tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
290 }
291
292 static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
293 unsigned int blocks)
294 {
295 struct tmio_sd_priv *priv = dev_get_priv(dev);
296 long wait = 1000000 + 10 * blocks;
297
298 while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
299 if (wait-- < 0) {
300 dev_err(dev, "timeout during DMA\n");
301 return -ETIMEDOUT;
302 }
303
304 udelay(10);
305 }
306
307 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
308 dev_err(dev, "error during DMA\n");
309 return -EIO;
310 }
311
312 return 0;
313 }
314
315 static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
316 {
317 struct tmio_sd_priv *priv = dev_get_priv(dev);
318 size_t len = data->blocks * data->blocksize;
319 void *buf;
320 enum dma_data_direction dir;
321 dma_addr_t dma_addr;
322 u32 poll_flag, tmp;
323 int ret;
324
325 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
326
327 if (data->flags & MMC_DATA_READ) {
328 buf = data->dest;
329 dir = DMA_FROM_DEVICE;
330 /*
331 * The DMA READ completion flag position differs on Socionext
332 * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
333 * bit 17 is a hardware bug and forbidden. It is either bit 17
334 * or bit 20 on Renesas SoCs, depending on SoC.
335 */
336 poll_flag = priv->read_poll_flag;
337 tmp |= TMIO_SD_DMA_MODE_DIR_RD;
338 } else {
339 buf = (void *)data->src;
340 dir = DMA_TO_DEVICE;
341 poll_flag = TMIO_SD_DMA_INFO1_END_WR;
342 tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
343 }
344
345 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
346
347 dma_addr = dma_map_single(buf, len, dir);
348
349 tmio_sd_dma_start(priv, dma_addr);
350
351 ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
352
353 if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
354 udelay(1);
355
356 dma_unmap_single(buf, len, dir);
357
358 return ret;
359 }
360
361 /* check if the address is DMA'able */
362 static bool tmio_sd_addr_is_dmaable(const char *src)
363 {
364 uintptr_t addr = (uintptr_t)src;
365
366 if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
367 return false;
368
369 #if defined(CONFIG_RCAR_GEN3)
370 /* Gen3 DMA has 32bit limit */
371 if (addr >> 32)
372 return false;
373 #endif
374
375 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
376 defined(CONFIG_SPL_BUILD)
377 /*
378 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
379 * of L2, which is unreachable from the DMA engine.
380 */
381 if (addr < CONFIG_SPL_STACK)
382 return false;
383 #endif
384
385 return true;
386 }
387
388 int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
389 struct mmc_data *data)
390 {
391 struct tmio_sd_priv *priv = dev_get_priv(dev);
392 int ret;
393 u32 tmp;
394
395 if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
396 dev_err(dev, "command busy\n");
397 return -EBUSY;
398 }
399
400 /* clear all status flags */
401 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
402 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
403
404 /* disable DMA once */
405 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
406 tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
407 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
408
409 tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
410
411 tmp = cmd->cmdidx;
412
413 if (data) {
414 tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
415 tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
416
417 /* Do not send CMD12 automatically */
418 tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
419
420 if (data->blocks > 1)
421 tmp |= TMIO_SD_CMD_MULTI;
422
423 if (data->flags & MMC_DATA_READ)
424 tmp |= TMIO_SD_CMD_RD;
425 }
426
427 /*
428 * Do not use the response type auto-detection on this hardware.
429 * CMD8, for example, has different response types on SD and eMMC,
430 * while this controller always assumes the response type for SD.
431 * Set the response type manually.
432 */
433 switch (cmd->resp_type) {
434 case MMC_RSP_NONE:
435 tmp |= TMIO_SD_CMD_RSP_NONE;
436 break;
437 case MMC_RSP_R1:
438 tmp |= TMIO_SD_CMD_RSP_R1;
439 break;
440 case MMC_RSP_R1b:
441 tmp |= TMIO_SD_CMD_RSP_R1B;
442 break;
443 case MMC_RSP_R2:
444 tmp |= TMIO_SD_CMD_RSP_R2;
445 break;
446 case MMC_RSP_R3:
447 tmp |= TMIO_SD_CMD_RSP_R3;
448 break;
449 default:
450 dev_err(dev, "unknown response type\n");
451 return -EINVAL;
452 }
453
454 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
455 cmd->cmdidx, tmp, cmd->cmdarg);
456 tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
457
458 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
459 TMIO_SD_INFO1_RSP);
460 if (ret)
461 return ret;
462
463 if (cmd->resp_type & MMC_RSP_136) {
464 u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
465 u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
466 u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
467 u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
468
469 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
470 ((rsp_103_72 & 0xff000000) >> 24);
471 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
472 ((rsp_71_40 & 0xff000000) >> 24);
473 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
474 ((rsp_39_8 & 0xff000000) >> 24);
475 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
476 } else {
477 /* bit 39-8 */
478 cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
479 }
480
481 if (data) {
482 /* use DMA if the HW supports it and the buffer is aligned */
483 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
484 tmio_sd_addr_is_dmaable(data->src))
485 ret = tmio_sd_dma_xfer(dev, data);
486 else
487 ret = tmio_sd_pio_xfer(dev, cmd, data);
488 if (ret)
489 return ret;
490
491 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
492 TMIO_SD_INFO1_CMP);
493 if (ret)
494 return ret;
495 }
496
497 return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
498 TMIO_SD_INFO2_SCLKDIVEN);
499 }
500
501 static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
502 struct mmc *mmc)
503 {
504 u32 val, tmp;
505
506 switch (mmc->bus_width) {
507 case 0:
508 case 1:
509 val = TMIO_SD_OPTION_WIDTH_1;
510 break;
511 case 4:
512 val = TMIO_SD_OPTION_WIDTH_4;
513 break;
514 case 8:
515 val = TMIO_SD_OPTION_WIDTH_8;
516 break;
517 default:
518 return -EINVAL;
519 }
520
521 tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
522 tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
523 tmp |= val;
524 tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
525
526 return 0;
527 }
528
529 static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
530 struct mmc *mmc)
531 {
532 u32 tmp;
533
534 tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
535 if (mmc->ddr_mode)
536 tmp |= TMIO_SD_IF_MODE_DDR;
537 else
538 tmp &= ~TMIO_SD_IF_MODE_DDR;
539 tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
540 }
541
542 static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
543 {
544 return priv->clk_get_rate(priv);
545 }
546
547 static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
548 {
549 unsigned int divisor;
550 u32 tmp, val = 0;
551 ulong mclk;
552
553 if (mmc->clock) {
554 mclk = tmio_sd_clk_get_rate(priv);
555
556 divisor = DIV_ROUND_UP(mclk, mmc->clock);
557
558 /* Do not set divider to 0xff in DDR mode */
559 if (mmc->ddr_mode && (divisor == 1))
560 divisor = 2;
561
562 if (divisor <= 1)
563 val = (priv->caps & TMIO_SD_CAP_RCAR) ?
564 TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
565 else if (divisor <= 2)
566 val = TMIO_SD_CLKCTL_DIV2;
567 else if (divisor <= 4)
568 val = TMIO_SD_CLKCTL_DIV4;
569 else if (divisor <= 8)
570 val = TMIO_SD_CLKCTL_DIV8;
571 else if (divisor <= 16)
572 val = TMIO_SD_CLKCTL_DIV16;
573 else if (divisor <= 32)
574 val = TMIO_SD_CLKCTL_DIV32;
575 else if (divisor <= 64)
576 val = TMIO_SD_CLKCTL_DIV64;
577 else if (divisor <= 128)
578 val = TMIO_SD_CLKCTL_DIV128;
579 else if (divisor <= 256)
580 val = TMIO_SD_CLKCTL_DIV256;
581 else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
582 val = TMIO_SD_CLKCTL_DIV512;
583 else
584 val = TMIO_SD_CLKCTL_DIV1024;
585 }
586
587 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
588 if (mmc->clock &&
589 !((tmp & TMIO_SD_CLKCTL_SCLKEN) &&
590 ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) {
591 /*
592 * Stop the clock before changing its rate
593 * to avoid a glitch signal
594 */
595 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
596 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
597
598 /* Change the clock rate. */
599 tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
600 tmp |= val;
601 }
602
603 /* Enable or Disable the clock */
604 if (mmc->clk_disable) {
605 tmp |= TMIO_SD_CLKCTL_OFFEN;
606 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
607 } else {
608 tmp &= ~TMIO_SD_CLKCTL_OFFEN;
609 tmp |= TMIO_SD_CLKCTL_SCLKEN;
610 }
611
612 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
613
614 udelay(1000);
615 }
616
617 static void tmio_sd_set_pins(struct udevice *dev)
618 {
619 __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
620
621 #ifdef CONFIG_DM_REGULATOR
622 struct tmio_sd_priv *priv = dev_get_priv(dev);
623
624 if (priv->vqmmc_dev) {
625 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
626 regulator_set_value(priv->vqmmc_dev, 1800000);
627 else
628 regulator_set_value(priv->vqmmc_dev, 3300000);
629 regulator_set_enable(priv->vqmmc_dev, true);
630 }
631 #endif
632
633 #ifdef CONFIG_PINCTRL
634 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
635 pinctrl_select_state(dev, "state_uhs");
636 else
637 pinctrl_select_state(dev, "default");
638 #endif
639 }
640
641 int tmio_sd_set_ios(struct udevice *dev)
642 {
643 struct tmio_sd_priv *priv = dev_get_priv(dev);
644 struct mmc *mmc = mmc_get_mmc_dev(dev);
645 int ret;
646
647 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
648 mmc->clock, mmc->ddr_mode, mmc->bus_width);
649
650 tmio_sd_set_clk_rate(priv, mmc);
651 ret = tmio_sd_set_bus_width(priv, mmc);
652 if (ret)
653 return ret;
654 tmio_sd_set_ddr_mode(priv, mmc);
655 tmio_sd_set_pins(dev);
656
657 return 0;
658 }
659
660 int tmio_sd_get_cd(struct udevice *dev)
661 {
662 struct tmio_sd_priv *priv = dev_get_priv(dev);
663
664 if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
665 return 1;
666
667 return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
668 TMIO_SD_INFO1_CD);
669 }
670
671 static void tmio_sd_host_init(struct tmio_sd_priv *priv)
672 {
673 u32 tmp;
674
675 /* soft reset of the host */
676 tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
677 tmp &= ~TMIO_SD_SOFT_RST_RSTX;
678 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
679 tmp |= TMIO_SD_SOFT_RST_RSTX;
680 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
681
682 /* FIXME: implement eMMC hw_reset */
683
684 tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
685
686 /*
687 * Connected to 32bit AXI.
688 * This register dropped backward compatibility at version 0x10.
689 * Write an appropriate value depending on the IP version.
690 */
691 if (priv->version >= 0x10) {
692 if (priv->caps & TMIO_SD_CAP_64BIT)
693 tmio_sd_writel(priv, 0x000, TMIO_SD_HOST_MODE);
694 else
695 tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
696 } else {
697 tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
698 }
699
700 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
701 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
702 tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
703 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
704 }
705 }
706
707 int tmio_sd_bind(struct udevice *dev)
708 {
709 struct tmio_sd_plat *plat = dev_get_platdata(dev);
710
711 return mmc_bind(dev, &plat->mmc, &plat->cfg);
712 }
713
714 int tmio_sd_probe(struct udevice *dev, u32 quirks)
715 {
716 struct tmio_sd_plat *plat = dev_get_platdata(dev);
717 struct tmio_sd_priv *priv = dev_get_priv(dev);
718 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
719 fdt_addr_t base;
720 ulong mclk;
721 int ret;
722
723 base = devfdt_get_addr(dev);
724 if (base == FDT_ADDR_T_NONE)
725 return -EINVAL;
726
727 priv->regbase = devm_ioremap(dev, base, SZ_2K);
728 if (!priv->regbase)
729 return -ENOMEM;
730
731 #ifdef CONFIG_DM_REGULATOR
732 device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
733 if (priv->vqmmc_dev)
734 regulator_set_value(priv->vqmmc_dev, 3300000);
735 #endif
736
737 ret = mmc_of_parse(dev, &plat->cfg);
738 if (ret < 0) {
739 dev_err(dev, "failed to parse host caps\n");
740 return ret;
741 }
742
743 plat->cfg.name = dev->name;
744 plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
745
746 if (quirks)
747 priv->caps = quirks;
748
749 priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
750 TMIO_SD_VERSION_IP;
751 dev_dbg(dev, "version %x\n", priv->version);
752 if (priv->version >= 0x10) {
753 priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
754 priv->caps |= TMIO_SD_CAP_DIV1024;
755 }
756
757 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
758 NULL))
759 priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
760
761 tmio_sd_host_init(priv);
762
763 mclk = tmio_sd_clk_get_rate(priv);
764
765 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
766 plat->cfg.f_min = mclk /
767 (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
768 plat->cfg.f_max = mclk;
769 if (quirks & TMIO_SD_CAP_16BIT)
770 plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
771 else
772 plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
773
774 upriv->mmc = &plat->mmc;
775
776 return 0;
777 }
"Das U-Boot" Source Tree