2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/compat.h>
14 #include <linux/dma-direction.h>
16 #include <linux/sizes.h>
17 #include <power/regulator.h>
18 #include <asm/unaligned.h>
20 DECLARE_GLOBAL_DATA_PTR
;
22 #define UNIPHIER_SD_CMD 0x000 /* command */
23 #define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
24 #define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */
25 #define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */
26 #define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */
27 #define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
28 #define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
29 #define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */
30 #define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
31 #define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
32 #define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
33 #define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
34 #define UNIPHIER_SD_ARG 0x008 /* command argument */
35 #define UNIPHIER_SD_STOP 0x010 /* stop action control */
36 #define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */
37 #define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */
38 #define UNIPHIER_SD_SECCNT 0x014 /* sector counter */
39 #define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */
40 #define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */
41 #define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */
42 #define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */
43 #define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */
44 #define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */
45 #define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */
46 #define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */
47 #define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */
48 #define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */
49 #define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */
50 #define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
51 #define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */
52 #define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */
53 #define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */
54 #define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
55 #define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */
56 #define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
57 #define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
58 #define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */
59 #define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */
60 #define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
61 #define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
62 #define UNIPHIER_SD_INFO1_MASK 0x040
63 #define UNIPHIER_SD_INFO2_MASK 0x044
64 #define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */
65 #define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff
66 #define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
67 #define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
68 #define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
69 #define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
70 #define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
71 #define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
72 #define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
73 #define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
74 #define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
75 #define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
76 #define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
77 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
78 #define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
79 #define UNIPHIER_SD_SIZE 0x04c /* block size */
80 #define UNIPHIER_SD_OPTION 0x050
81 #define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13)
82 #define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13)
83 #define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13)
84 #define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13)
85 #define UNIPHIER_SD_BUF 0x060 /* read/write buffer */
86 #define UNIPHIER_SD_EXTMODE 0x1b0
87 #define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
88 #define UNIPHIER_SD_SOFT_RST 0x1c0
89 #define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
90 #define UNIPHIER_SD_VERSION 0x1c4 /* version register */
91 #define UNIPHIER_SD_VERSION_IP 0xff /* IP version */
92 #define UNIPHIER_SD_HOST_MODE 0x1c8
93 #define UNIPHIER_SD_IF_MODE 0x1cc
94 #define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */
95 #define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */
96 #define UNIPHIER_SD_VOLT_MASK (3 << 0)
97 #define UNIPHIER_SD_VOLT_OFF (0 << 0)
98 #define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */
99 #define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */
100 #define UNIPHIER_SD_DMA_MODE 0x410
101 #define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
102 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
103 #define UNIPHIER_SD_DMA_CTL 0x414
104 #define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
105 #define UNIPHIER_SD_DMA_RST 0x418
106 #define UNIPHIER_SD_DMA_RST_RD BIT(9)
107 #define UNIPHIER_SD_DMA_RST_WR BIT(8)
108 #define UNIPHIER_SD_DMA_INFO1 0x420
109 #define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/
110 #define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */
111 #define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
112 #define UNIPHIER_SD_DMA_INFO1_MASK 0x424
113 #define UNIPHIER_SD_DMA_INFO2 0x428
114 #define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17)
115 #define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16)
116 #define UNIPHIER_SD_DMA_INFO2_MASK 0x42c
117 #define UNIPHIER_SD_DMA_ADDR_L 0x440
118 #define UNIPHIER_SD_DMA_ADDR_H 0x444
120 /* alignment required by the DMA engine of this controller */
121 #define UNIPHIER_SD_DMA_MINALIGN 0x10
123 struct uniphier_sd_plat
{
124 struct mmc_config cfg
;
128 struct uniphier_sd_priv
{
129 void __iomem
*regbase
;
131 unsigned int version
;
133 #define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
134 #define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
135 #define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
136 #define UNIPHIER_SD_CAP_64BIT BIT(3) /* Controller is 64bit */
139 static u64
uniphier_sd_readq(struct uniphier_sd_priv
*priv
, unsigned int reg
)
141 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
)
142 return readq(priv
->regbase
+ (reg
<< 1));
144 return readq(priv
->regbase
+ reg
);
147 static void uniphier_sd_writeq(struct uniphier_sd_priv
*priv
,
148 u64 val
, unsigned int reg
)
150 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
)
151 writeq(val
, priv
->regbase
+ (reg
<< 1));
153 writeq(val
, priv
->regbase
+ reg
);
156 static u32
uniphier_sd_readl(struct uniphier_sd_priv
*priv
, unsigned int reg
)
158 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
)
159 return readl(priv
->regbase
+ (reg
<< 1));
161 return readl(priv
->regbase
+ reg
);
164 static void uniphier_sd_writel(struct uniphier_sd_priv
*priv
,
165 u32 val
, unsigned int reg
)
167 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
)
168 writel(val
, priv
->regbase
+ (reg
<< 1));
170 writel(val
, priv
->regbase
+ reg
);
173 static dma_addr_t
__dma_map_single(void *ptr
, size_t size
,
174 enum dma_data_direction dir
)
176 unsigned long addr
= (unsigned long)ptr
;
178 if (dir
== DMA_FROM_DEVICE
)
179 invalidate_dcache_range(addr
, addr
+ size
);
181 flush_dcache_range(addr
, addr
+ size
);
186 static void __dma_unmap_single(dma_addr_t addr
, size_t size
,
187 enum dma_data_direction dir
)
189 if (dir
!= DMA_TO_DEVICE
)
190 invalidate_dcache_range(addr
, addr
+ size
);
193 static int uniphier_sd_check_error(struct udevice
*dev
)
195 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
196 u32 info2
= uniphier_sd_readl(priv
, UNIPHIER_SD_INFO2
);
198 if (info2
& UNIPHIER_SD_INFO2_ERR_RTO
) {
200 * TIMEOUT must be returned for unsupported command. Do not
201 * display error log since this might be a part of sequence to
202 * distinguish between SD and MMC.
207 if (info2
& UNIPHIER_SD_INFO2_ERR_TO
) {
208 dev_err(dev
, "timeout error\n");
212 if (info2
& (UNIPHIER_SD_INFO2_ERR_END
| UNIPHIER_SD_INFO2_ERR_CRC
|
213 UNIPHIER_SD_INFO2_ERR_IDX
)) {
214 dev_err(dev
, "communication out of sync\n");
218 if (info2
& (UNIPHIER_SD_INFO2_ERR_ILA
| UNIPHIER_SD_INFO2_ERR_ILR
|
219 UNIPHIER_SD_INFO2_ERR_ILW
)) {
220 dev_err(dev
, "illegal access\n");
227 static int uniphier_sd_wait_for_irq(struct udevice
*dev
, unsigned int reg
,
230 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
234 while (!(uniphier_sd_readl(priv
, reg
) & flag
)) {
236 dev_err(dev
, "timeout\n");
240 ret
= uniphier_sd_check_error(dev
);
250 static int uniphier_sd_pio_read_one_block(struct udevice
*dev
, char *pbuf
,
253 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
256 /* wait until the buffer is filled with data */
257 ret
= uniphier_sd_wait_for_irq(dev
, UNIPHIER_SD_INFO2
,
258 UNIPHIER_SD_INFO2_BRE
);
263 * Clear the status flag _before_ read the buffer out because
264 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered.
266 uniphier_sd_writel(priv
, 0, UNIPHIER_SD_INFO2
);
268 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
) {
269 u64
*buf
= (u64
*)pbuf
;
270 if (likely(IS_ALIGNED((uintptr_t)buf
, 8))) {
271 for (i
= 0; i
< blocksize
/ 8; i
++) {
272 *buf
++ = uniphier_sd_readq(priv
,
276 for (i
= 0; i
< blocksize
/ 8; i
++) {
278 data
= uniphier_sd_readq(priv
,
280 put_unaligned(data
, buf
++);
284 u32
*buf
= (u32
*)pbuf
;
285 if (likely(IS_ALIGNED((uintptr_t)buf
, 4))) {
286 for (i
= 0; i
< blocksize
/ 4; i
++) {
287 *buf
++ = uniphier_sd_readl(priv
,
291 for (i
= 0; i
< blocksize
/ 4; i
++) {
293 data
= uniphier_sd_readl(priv
, UNIPHIER_SD_BUF
);
294 put_unaligned(data
, buf
++);
302 static int uniphier_sd_pio_write_one_block(struct udevice
*dev
,
303 const char *pbuf
, uint blocksize
)
305 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
308 /* wait until the buffer becomes empty */
309 ret
= uniphier_sd_wait_for_irq(dev
, UNIPHIER_SD_INFO2
,
310 UNIPHIER_SD_INFO2_BWE
);
314 uniphier_sd_writel(priv
, 0, UNIPHIER_SD_INFO2
);
316 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
) {
317 const u64
*buf
= (const u64
*)pbuf
;
318 if (likely(IS_ALIGNED((uintptr_t)buf
, 8))) {
319 for (i
= 0; i
< blocksize
/ 8; i
++) {
320 uniphier_sd_writeq(priv
, *buf
++,
324 for (i
= 0; i
< blocksize
/ 8; i
++) {
325 u64 data
= get_unaligned(buf
++);
326 uniphier_sd_writeq(priv
, data
,
331 const u32
*buf
= (const u32
*)pbuf
;
332 if (likely(IS_ALIGNED((uintptr_t)buf
, 4))) {
333 for (i
= 0; i
< blocksize
/ 4; i
++) {
334 uniphier_sd_writel(priv
, *buf
++,
338 for (i
= 0; i
< blocksize
/ 4; i
++) {
339 u32 data
= get_unaligned(buf
++);
340 uniphier_sd_writel(priv
, data
,
349 static int uniphier_sd_pio_xfer(struct udevice
*dev
, struct mmc_data
*data
)
351 const char *src
= data
->src
;
352 char *dest
= data
->dest
;
355 for (i
= 0; i
< data
->blocks
; i
++) {
356 if (data
->flags
& MMC_DATA_READ
)
357 ret
= uniphier_sd_pio_read_one_block(dev
, dest
,
360 ret
= uniphier_sd_pio_write_one_block(dev
, src
,
365 if (data
->flags
& MMC_DATA_READ
)
366 dest
+= data
->blocksize
;
368 src
+= data
->blocksize
;
374 static void uniphier_sd_dma_start(struct uniphier_sd_priv
*priv
,
379 uniphier_sd_writel(priv
, 0, UNIPHIER_SD_DMA_INFO1
);
380 uniphier_sd_writel(priv
, 0, UNIPHIER_SD_DMA_INFO2
);
383 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_EXTMODE
);
384 tmp
|= UNIPHIER_SD_EXTMODE_DMA_EN
;
385 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_EXTMODE
);
387 uniphier_sd_writel(priv
, dma_addr
& U32_MAX
, UNIPHIER_SD_DMA_ADDR_L
);
389 /* suppress the warning "right shift count >= width of type" */
390 dma_addr
>>= min_t(int, 32, 8 * sizeof(dma_addr
));
392 uniphier_sd_writel(priv
, dma_addr
& U32_MAX
, UNIPHIER_SD_DMA_ADDR_H
);
394 uniphier_sd_writel(priv
, UNIPHIER_SD_DMA_CTL_START
, UNIPHIER_SD_DMA_CTL
);
397 static int uniphier_sd_dma_wait_for_irq(struct udevice
*dev
, u32 flag
,
400 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
401 long wait
= 1000000 + 10 * blocks
;
403 while (!(uniphier_sd_readl(priv
, UNIPHIER_SD_DMA_INFO1
) & flag
)) {
405 dev_err(dev
, "timeout during DMA\n");
412 if (uniphier_sd_readl(priv
, UNIPHIER_SD_DMA_INFO2
)) {
413 dev_err(dev
, "error during DMA\n");
420 static int uniphier_sd_dma_xfer(struct udevice
*dev
, struct mmc_data
*data
)
422 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
423 size_t len
= data
->blocks
* data
->blocksize
;
425 enum dma_data_direction dir
;
430 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_DMA_MODE
);
432 if (data
->flags
& MMC_DATA_READ
) {
434 dir
= DMA_FROM_DEVICE
;
435 poll_flag
= UNIPHIER_SD_DMA_INFO1_END_RD2
;
436 tmp
|= UNIPHIER_SD_DMA_MODE_DIR_RD
;
438 buf
= (void *)data
->src
;
440 poll_flag
= UNIPHIER_SD_DMA_INFO1_END_WR
;
441 tmp
&= ~UNIPHIER_SD_DMA_MODE_DIR_RD
;
444 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_DMA_MODE
);
446 dma_addr
= __dma_map_single(buf
, len
, dir
);
448 uniphier_sd_dma_start(priv
, dma_addr
);
450 ret
= uniphier_sd_dma_wait_for_irq(dev
, poll_flag
, data
->blocks
);
452 __dma_unmap_single(dma_addr
, len
, dir
);
457 /* check if the address is DMA'able */
458 static bool uniphier_sd_addr_is_dmaable(unsigned long addr
)
460 if (!IS_ALIGNED(addr
, UNIPHIER_SD_DMA_MINALIGN
))
463 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
464 defined(CONFIG_SPL_BUILD)
466 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
467 * of L2, which is unreachable from the DMA engine.
469 if (addr
< CONFIG_SPL_STACK
)
476 static int uniphier_sd_send_cmd(struct udevice
*dev
, struct mmc_cmd
*cmd
,
477 struct mmc_data
*data
)
479 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
483 if (uniphier_sd_readl(priv
, UNIPHIER_SD_INFO2
) & UNIPHIER_SD_INFO2_CBSY
) {
484 dev_err(dev
, "command busy\n");
488 /* clear all status flags */
489 uniphier_sd_writel(priv
, 0, UNIPHIER_SD_INFO1
);
490 uniphier_sd_writel(priv
, 0, UNIPHIER_SD_INFO2
);
492 /* disable DMA once */
493 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_EXTMODE
);
494 tmp
&= ~UNIPHIER_SD_EXTMODE_DMA_EN
;
495 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_EXTMODE
);
497 uniphier_sd_writel(priv
, cmd
->cmdarg
, UNIPHIER_SD_ARG
);
502 uniphier_sd_writel(priv
, data
->blocksize
, UNIPHIER_SD_SIZE
);
503 uniphier_sd_writel(priv
, data
->blocks
, UNIPHIER_SD_SECCNT
);
505 /* Do not send CMD12 automatically */
506 tmp
|= UNIPHIER_SD_CMD_NOSTOP
| UNIPHIER_SD_CMD_DATA
;
508 if (data
->blocks
> 1)
509 tmp
|= UNIPHIER_SD_CMD_MULTI
;
511 if (data
->flags
& MMC_DATA_READ
)
512 tmp
|= UNIPHIER_SD_CMD_RD
;
516 * Do not use the response type auto-detection on this hardware.
517 * CMD8, for example, has different response types on SD and eMMC,
518 * while this controller always assumes the response type for SD.
519 * Set the response type manually.
521 switch (cmd
->resp_type
) {
523 tmp
|= UNIPHIER_SD_CMD_RSP_NONE
;
526 tmp
|= UNIPHIER_SD_CMD_RSP_R1
;
529 tmp
|= UNIPHIER_SD_CMD_RSP_R1B
;
532 tmp
|= UNIPHIER_SD_CMD_RSP_R2
;
535 tmp
|= UNIPHIER_SD_CMD_RSP_R3
;
538 dev_err(dev
, "unknown response type\n");
542 dev_dbg(dev
, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
543 cmd
->cmdidx
, tmp
, cmd
->cmdarg
);
544 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_CMD
);
546 ret
= uniphier_sd_wait_for_irq(dev
, UNIPHIER_SD_INFO1
,
547 UNIPHIER_SD_INFO1_RSP
);
551 if (cmd
->resp_type
& MMC_RSP_136
) {
552 u32 rsp_127_104
= uniphier_sd_readl(priv
, UNIPHIER_SD_RSP76
);
553 u32 rsp_103_72
= uniphier_sd_readl(priv
, UNIPHIER_SD_RSP54
);
554 u32 rsp_71_40
= uniphier_sd_readl(priv
, UNIPHIER_SD_RSP32
);
555 u32 rsp_39_8
= uniphier_sd_readl(priv
, UNIPHIER_SD_RSP10
);
557 cmd
->response
[0] = ((rsp_127_104
& 0x00ffffff) << 8) |
558 ((rsp_103_72
& 0xff000000) >> 24);
559 cmd
->response
[1] = ((rsp_103_72
& 0x00ffffff) << 8) |
560 ((rsp_71_40
& 0xff000000) >> 24);
561 cmd
->response
[2] = ((rsp_71_40
& 0x00ffffff) << 8) |
562 ((rsp_39_8
& 0xff000000) >> 24);
563 cmd
->response
[3] = (rsp_39_8
& 0xffffff) << 8;
566 cmd
->response
[0] = uniphier_sd_readl(priv
, UNIPHIER_SD_RSP10
);
570 /* use DMA if the HW supports it and the buffer is aligned */
571 if (priv
->caps
& UNIPHIER_SD_CAP_DMA_INTERNAL
&&
572 uniphier_sd_addr_is_dmaable((long)data
->src
))
573 ret
= uniphier_sd_dma_xfer(dev
, data
);
575 ret
= uniphier_sd_pio_xfer(dev
, data
);
577 ret
= uniphier_sd_wait_for_irq(dev
, UNIPHIER_SD_INFO1
,
578 UNIPHIER_SD_INFO1_CMP
);
586 static int uniphier_sd_set_bus_width(struct uniphier_sd_priv
*priv
,
591 switch (mmc
->bus_width
) {
593 val
= UNIPHIER_SD_OPTION_WIDTH_1
;
596 val
= UNIPHIER_SD_OPTION_WIDTH_4
;
599 val
= UNIPHIER_SD_OPTION_WIDTH_8
;
605 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_OPTION
);
606 tmp
&= ~UNIPHIER_SD_OPTION_WIDTH_MASK
;
608 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_OPTION
);
613 static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv
*priv
,
618 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_IF_MODE
);
620 tmp
|= UNIPHIER_SD_IF_MODE_DDR
;
622 tmp
&= ~UNIPHIER_SD_IF_MODE_DDR
;
623 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_IF_MODE
);
626 static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv
*priv
,
629 unsigned int divisor
;
635 divisor
= DIV_ROUND_UP(priv
->mclk
, mmc
->clock
);
638 val
= UNIPHIER_SD_CLKCTL_DIV1
;
639 else if (divisor
<= 2)
640 val
= UNIPHIER_SD_CLKCTL_DIV2
;
641 else if (divisor
<= 4)
642 val
= UNIPHIER_SD_CLKCTL_DIV4
;
643 else if (divisor
<= 8)
644 val
= UNIPHIER_SD_CLKCTL_DIV8
;
645 else if (divisor
<= 16)
646 val
= UNIPHIER_SD_CLKCTL_DIV16
;
647 else if (divisor
<= 32)
648 val
= UNIPHIER_SD_CLKCTL_DIV32
;
649 else if (divisor
<= 64)
650 val
= UNIPHIER_SD_CLKCTL_DIV64
;
651 else if (divisor
<= 128)
652 val
= UNIPHIER_SD_CLKCTL_DIV128
;
653 else if (divisor
<= 256)
654 val
= UNIPHIER_SD_CLKCTL_DIV256
;
655 else if (divisor
<= 512 || !(priv
->caps
& UNIPHIER_SD_CAP_DIV1024
))
656 val
= UNIPHIER_SD_CLKCTL_DIV512
;
658 val
= UNIPHIER_SD_CLKCTL_DIV1024
;
660 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_CLKCTL
);
661 if (tmp
& UNIPHIER_SD_CLKCTL_SCLKEN
&&
662 (tmp
& UNIPHIER_SD_CLKCTL_DIV_MASK
) == val
)
665 /* stop the clock before changing its rate to avoid a glitch signal */
666 tmp
&= ~UNIPHIER_SD_CLKCTL_SCLKEN
;
667 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_CLKCTL
);
669 tmp
&= ~UNIPHIER_SD_CLKCTL_DIV_MASK
;
670 tmp
|= val
| UNIPHIER_SD_CLKCTL_OFFEN
;
671 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_CLKCTL
);
673 tmp
|= UNIPHIER_SD_CLKCTL_SCLKEN
;
674 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_CLKCTL
);
679 static int uniphier_sd_set_ios(struct udevice
*dev
)
681 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
682 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
685 dev_dbg(dev
, "clock %uHz, DDRmode %d, width %u\n",
686 mmc
->clock
, mmc
->ddr_mode
, mmc
->bus_width
);
688 ret
= uniphier_sd_set_bus_width(priv
, mmc
);
691 uniphier_sd_set_ddr_mode(priv
, mmc
);
692 uniphier_sd_set_clk_rate(priv
, mmc
);
697 static int uniphier_sd_get_cd(struct udevice
*dev
)
699 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
701 if (priv
->caps
& UNIPHIER_SD_CAP_NONREMOVABLE
)
704 return !!(uniphier_sd_readl(priv
, UNIPHIER_SD_INFO1
) &
705 UNIPHIER_SD_INFO1_CD
);
708 static const struct dm_mmc_ops uniphier_sd_ops
= {
709 .send_cmd
= uniphier_sd_send_cmd
,
710 .set_ios
= uniphier_sd_set_ios
,
711 .get_cd
= uniphier_sd_get_cd
,
714 static void uniphier_sd_host_init(struct uniphier_sd_priv
*priv
)
718 /* soft reset of the host */
719 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_SOFT_RST
);
720 tmp
&= ~UNIPHIER_SD_SOFT_RST_RSTX
;
721 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_SOFT_RST
);
722 tmp
|= UNIPHIER_SD_SOFT_RST_RSTX
;
723 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_SOFT_RST
);
725 /* FIXME: implement eMMC hw_reset */
727 uniphier_sd_writel(priv
, UNIPHIER_SD_STOP_SEC
, UNIPHIER_SD_STOP
);
730 * Connected to 32bit AXI.
731 * This register dropped backward compatibility at version 0x10.
732 * Write an appropriate value depending on the IP version.
734 uniphier_sd_writel(priv
, priv
->version
>= 0x10 ? 0x00000101 : 0x00000000,
735 UNIPHIER_SD_HOST_MODE
);
737 if (priv
->caps
& UNIPHIER_SD_CAP_DMA_INTERNAL
) {
738 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_DMA_MODE
);
739 tmp
|= UNIPHIER_SD_DMA_MODE_ADDR_INC
;
740 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_DMA_MODE
);
744 static int uniphier_sd_bind(struct udevice
*dev
)
746 struct uniphier_sd_plat
*plat
= dev_get_platdata(dev
);
748 return mmc_bind(dev
, &plat
->mmc
, &plat
->cfg
);
751 static int uniphier_sd_probe(struct udevice
*dev
)
753 struct uniphier_sd_plat
*plat
= dev_get_platdata(dev
);
754 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
755 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
756 const u32 quirks
= dev_get_driver_data(dev
);
760 #ifdef CONFIG_DM_REGULATOR
761 struct udevice
*vqmmc_dev
;
764 base
= devfdt_get_addr(dev
);
765 if (base
== FDT_ADDR_T_NONE
)
768 priv
->regbase
= devm_ioremap(dev
, base
, SZ_2K
);
772 #ifdef CONFIG_DM_REGULATOR
773 ret
= device_get_supply_regulator(dev
, "vqmmc-supply", &vqmmc_dev
);
775 /* Set the regulator to 3.3V until we support 1.8V modes */
776 regulator_set_value(vqmmc_dev
, 3300000);
777 regulator_set_enable(vqmmc_dev
, true);
781 ret
= clk_get_by_index(dev
, 0, &clk
);
783 dev_err(dev
, "failed to get host clock\n");
787 /* set to max rate */
788 priv
->mclk
= clk_set_rate(&clk
, ULONG_MAX
);
789 if (IS_ERR_VALUE(priv
->mclk
)) {
790 dev_err(dev
, "failed to set rate for host clock\n");
795 ret
= clk_enable(&clk
);
798 dev_err(dev
, "failed to enable host clock\n");
802 plat
->cfg
.name
= dev
->name
;
803 plat
->cfg
.host_caps
= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
805 switch (fdtdec_get_int(gd
->fdt_blob
, dev_of_offset(dev
), "bus-width",
808 plat
->cfg
.host_caps
|= MMC_MODE_8BIT
;
811 plat
->cfg
.host_caps
|= MMC_MODE_4BIT
;
816 dev_err(dev
, "Invalid \"bus-width\" value\n");
823 priv
->version
= uniphier_sd_readl(priv
, UNIPHIER_SD_VERSION
) &
824 UNIPHIER_SD_VERSION_IP
;
825 dev_dbg(dev
, "version %x\n", priv
->version
);
826 if (priv
->version
>= 0x10) {
827 priv
->caps
|= UNIPHIER_SD_CAP_DMA_INTERNAL
;
828 priv
->caps
|= UNIPHIER_SD_CAP_DIV1024
;
832 if (fdt_get_property(gd
->fdt_blob
, dev_of_offset(dev
), "non-removable",
834 priv
->caps
|= UNIPHIER_SD_CAP_NONREMOVABLE
;
836 uniphier_sd_host_init(priv
);
838 plat
->cfg
.voltages
= MMC_VDD_165_195
| MMC_VDD_32_33
| MMC_VDD_33_34
;
839 plat
->cfg
.f_min
= priv
->mclk
/
840 (priv
->caps
& UNIPHIER_SD_CAP_DIV1024
? 1024 : 512);
841 plat
->cfg
.f_max
= priv
->mclk
;
842 plat
->cfg
.b_max
= U32_MAX
; /* max value of UNIPHIER_SD_SECCNT */
844 upriv
->mmc
= &plat
->mmc
;
849 static const struct udevice_id uniphier_sd_match
[] = {
850 { .compatible
= "renesas,sdhi-r8a7795", .data
= UNIPHIER_SD_CAP_64BIT
},
851 { .compatible
= "renesas,sdhi-r8a7796", .data
= UNIPHIER_SD_CAP_64BIT
},
852 { .compatible
= "renesas,sdhi-r8a77970", .data
= UNIPHIER_SD_CAP_64BIT
},
853 { .compatible
= "renesas,sdhi-r8a77995", .data
= UNIPHIER_SD_CAP_64BIT
},
854 { .compatible
= "socionext,uniphier-sdhc", .data
= 0 },
858 U_BOOT_DRIVER(uniphier_mmc
) = {
859 .name
= "uniphier-mmc",
861 .of_match
= uniphier_sd_match
,
862 .bind
= uniphier_sd_bind
,
863 .probe
= uniphier_sd_probe
,
864 .priv_auto_alloc_size
= sizeof(struct uniphier_sd_priv
),
865 .platdata_auto_alloc_size
= sizeof(struct uniphier_sd_plat
),
866 .ops
= &uniphier_sd_ops
,