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mmc: uniphier-sd: Add support for 64bit controller
[people/ms/u-boot.git] / drivers / mmc / uniphier-sd.c
1 /*
2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <fdtdec.h>
11 #include <mmc.h>
12 #include <dm.h>
13 #include <linux/compat.h>
14 #include <linux/dma-direction.h>
15 #include <linux/io.h>
16 #include <linux/sizes.h>
17 #include <asm/unaligned.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #define UNIPHIER_SD_CMD 0x000 /* command */
22 #define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
23 #define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */
24 #define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */
25 #define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */
26 #define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
27 #define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
28 #define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */
29 #define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
30 #define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
31 #define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
32 #define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
33 #define UNIPHIER_SD_ARG 0x008 /* command argument */
34 #define UNIPHIER_SD_STOP 0x010 /* stop action control */
35 #define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */
36 #define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */
37 #define UNIPHIER_SD_SECCNT 0x014 /* sector counter */
38 #define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */
39 #define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */
40 #define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */
41 #define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */
42 #define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */
43 #define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */
44 #define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */
45 #define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */
46 #define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */
47 #define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */
48 #define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */
49 #define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
50 #define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */
51 #define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */
52 #define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */
53 #define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
54 #define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */
55 #define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
56 #define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
57 #define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */
58 #define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */
59 #define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
60 #define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
61 #define UNIPHIER_SD_INFO1_MASK 0x040
62 #define UNIPHIER_SD_INFO2_MASK 0x044
63 #define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */
64 #define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff
65 #define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
66 #define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
67 #define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
68 #define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
69 #define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
70 #define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
71 #define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
72 #define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
73 #define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
74 #define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
75 #define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
76 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
77 #define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
78 #define UNIPHIER_SD_SIZE 0x04c /* block size */
79 #define UNIPHIER_SD_OPTION 0x050
80 #define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13)
81 #define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13)
82 #define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13)
83 #define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13)
84 #define UNIPHIER_SD_BUF 0x060 /* read/write buffer */
85 #define UNIPHIER_SD_EXTMODE 0x1b0
86 #define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
87 #define UNIPHIER_SD_SOFT_RST 0x1c0
88 #define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
89 #define UNIPHIER_SD_VERSION 0x1c4 /* version register */
90 #define UNIPHIER_SD_VERSION_IP 0xff /* IP version */
91 #define UNIPHIER_SD_HOST_MODE 0x1c8
92 #define UNIPHIER_SD_IF_MODE 0x1cc
93 #define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */
94 #define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */
95 #define UNIPHIER_SD_VOLT_MASK (3 << 0)
96 #define UNIPHIER_SD_VOLT_OFF (0 << 0)
97 #define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */
98 #define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */
99 #define UNIPHIER_SD_DMA_MODE 0x410
100 #define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
101 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
102 #define UNIPHIER_SD_DMA_CTL 0x414
103 #define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
104 #define UNIPHIER_SD_DMA_RST 0x418
105 #define UNIPHIER_SD_DMA_RST_RD BIT(9)
106 #define UNIPHIER_SD_DMA_RST_WR BIT(8)
107 #define UNIPHIER_SD_DMA_INFO1 0x420
108 #define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/
109 #define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */
110 #define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
111 #define UNIPHIER_SD_DMA_INFO1_MASK 0x424
112 #define UNIPHIER_SD_DMA_INFO2 0x428
113 #define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17)
114 #define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16)
115 #define UNIPHIER_SD_DMA_INFO2_MASK 0x42c
116 #define UNIPHIER_SD_DMA_ADDR_L 0x440
117 #define UNIPHIER_SD_DMA_ADDR_H 0x444
118
119 /* alignment required by the DMA engine of this controller */
120 #define UNIPHIER_SD_DMA_MINALIGN 0x10
121
122 struct uniphier_sd_plat {
123 struct mmc_config cfg;
124 struct mmc mmc;
125 };
126
127 struct uniphier_sd_priv {
128 void __iomem *regbase;
129 unsigned long mclk;
130 unsigned int version;
131 u32 caps;
132 #define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
133 #define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
134 #define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
135 #define UNIPHIER_SD_CAP_64BIT BIT(3) /* Controller is 64bit */
136 };
137
138 static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, const u32 reg)
139 {
140 if (priv->caps & UNIPHIER_SD_CAP_64BIT)
141 return readl(priv->regbase + (reg << 1));
142 else
143 return readl(priv->regbase + reg);
144 }
145
146 static void uniphier_sd_writel(struct uniphier_sd_priv *priv,
147 const u32 val, const u32 reg)
148 {
149 if (priv->caps & UNIPHIER_SD_CAP_64BIT)
150 writel(val, priv->regbase + (reg << 1));
151 else
152 writel(val, priv->regbase + reg);
153 }
154
155 static dma_addr_t __dma_map_single(void *ptr, size_t size,
156 enum dma_data_direction dir)
157 {
158 unsigned long addr = (unsigned long)ptr;
159
160 if (dir == DMA_FROM_DEVICE)
161 invalidate_dcache_range(addr, addr + size);
162 else
163 flush_dcache_range(addr, addr + size);
164
165 return addr;
166 }
167
168 static void __dma_unmap_single(dma_addr_t addr, size_t size,
169 enum dma_data_direction dir)
170 {
171 if (dir != DMA_TO_DEVICE)
172 invalidate_dcache_range(addr, addr + size);
173 }
174
175 static int uniphier_sd_check_error(struct udevice *dev)
176 {
177 struct uniphier_sd_priv *priv = dev_get_priv(dev);
178 u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2);
179
180 if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) {
181 /*
182 * TIMEOUT must be returned for unsupported command. Do not
183 * display error log since this might be a part of sequence to
184 * distinguish between SD and MMC.
185 */
186 return -ETIMEDOUT;
187 }
188
189 if (info2 & UNIPHIER_SD_INFO2_ERR_TO) {
190 dev_err(dev, "timeout error\n");
191 return -ETIMEDOUT;
192 }
193
194 if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC |
195 UNIPHIER_SD_INFO2_ERR_IDX)) {
196 dev_err(dev, "communication out of sync\n");
197 return -EILSEQ;
198 }
199
200 if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR |
201 UNIPHIER_SD_INFO2_ERR_ILW)) {
202 dev_err(dev, "illegal access\n");
203 return -EIO;
204 }
205
206 return 0;
207 }
208
209 static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
210 u32 flag)
211 {
212 struct uniphier_sd_priv *priv = dev_get_priv(dev);
213 long wait = 1000000;
214 int ret;
215
216 while (!(uniphier_sd_readl(priv, reg) & flag)) {
217 if (wait-- < 0) {
218 dev_err(dev, "timeout\n");
219 return -ETIMEDOUT;
220 }
221
222 ret = uniphier_sd_check_error(dev);
223 if (ret)
224 return ret;
225
226 udelay(1);
227 }
228
229 return 0;
230 }
231
232 static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
233 uint blocksize)
234 {
235 struct uniphier_sd_priv *priv = dev_get_priv(dev);
236 int i, ret;
237
238 /* wait until the buffer is filled with data */
239 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
240 UNIPHIER_SD_INFO2_BRE);
241 if (ret)
242 return ret;
243
244 /*
245 * Clear the status flag _before_ read the buffer out because
246 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered.
247 */
248 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
249
250 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
251 for (i = 0; i < blocksize / 4; i++)
252 *(*pbuf)++ = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
253 } else {
254 for (i = 0; i < blocksize / 4; i++)
255 put_unaligned(uniphier_sd_readl(priv, UNIPHIER_SD_BUF),
256 (*pbuf)++);
257 }
258
259 return 0;
260 }
261
262 static int uniphier_sd_pio_write_one_block(struct udevice *dev,
263 const u32 **pbuf, uint blocksize)
264 {
265 struct uniphier_sd_priv *priv = dev_get_priv(dev);
266 int i, ret;
267
268 /* wait until the buffer becomes empty */
269 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
270 UNIPHIER_SD_INFO2_BWE);
271 if (ret)
272 return ret;
273
274 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
275
276 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
277 for (i = 0; i < blocksize / 4; i++)
278 uniphier_sd_writel(priv, *(*pbuf)++, UNIPHIER_SD_BUF);
279 } else {
280 for (i = 0; i < blocksize / 4; i++)
281 uniphier_sd_writel(priv, get_unaligned((*pbuf)++),
282 UNIPHIER_SD_BUF);
283 }
284
285 return 0;
286 }
287
288 static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
289 {
290 u32 *dest = (u32 *)data->dest;
291 const u32 *src = (const u32 *)data->src;
292 int i, ret;
293
294 for (i = 0; i < data->blocks; i++) {
295 if (data->flags & MMC_DATA_READ)
296 ret = uniphier_sd_pio_read_one_block(dev, &dest,
297 data->blocksize);
298 else
299 ret = uniphier_sd_pio_write_one_block(dev, &src,
300 data->blocksize);
301 if (ret)
302 return ret;
303 }
304
305 return 0;
306 }
307
308 static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv,
309 dma_addr_t dma_addr)
310 {
311 u32 tmp;
312
313 uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1);
314 uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2);
315
316 /* enable DMA */
317 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
318 tmp |= UNIPHIER_SD_EXTMODE_DMA_EN;
319 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
320
321 uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L);
322
323 /* suppress the warning "right shift count >= width of type" */
324 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
325
326 uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H);
327
328 uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL);
329 }
330
331 static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
332 unsigned int blocks)
333 {
334 struct uniphier_sd_priv *priv = dev_get_priv(dev);
335 long wait = 1000000 + 10 * blocks;
336
337 while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) {
338 if (wait-- < 0) {
339 dev_err(dev, "timeout during DMA\n");
340 return -ETIMEDOUT;
341 }
342
343 udelay(10);
344 }
345
346 if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) {
347 dev_err(dev, "error during DMA\n");
348 return -EIO;
349 }
350
351 return 0;
352 }
353
354 static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
355 {
356 struct uniphier_sd_priv *priv = dev_get_priv(dev);
357 size_t len = data->blocks * data->blocksize;
358 void *buf;
359 enum dma_data_direction dir;
360 dma_addr_t dma_addr;
361 u32 poll_flag, tmp;
362 int ret;
363
364 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
365
366 if (data->flags & MMC_DATA_READ) {
367 buf = data->dest;
368 dir = DMA_FROM_DEVICE;
369 poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2;
370 tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD;
371 } else {
372 buf = (void *)data->src;
373 dir = DMA_TO_DEVICE;
374 poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR;
375 tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD;
376 }
377
378 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
379
380 dma_addr = __dma_map_single(buf, len, dir);
381
382 uniphier_sd_dma_start(priv, dma_addr);
383
384 ret = uniphier_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
385
386 __dma_unmap_single(dma_addr, len, dir);
387
388 return ret;
389 }
390
391 /* check if the address is DMA'able */
392 static bool uniphier_sd_addr_is_dmaable(unsigned long addr)
393 {
394 if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN))
395 return false;
396
397 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
398 defined(CONFIG_SPL_BUILD)
399 /*
400 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
401 * of L2, which is unreachable from the DMA engine.
402 */
403 if (addr < CONFIG_SPL_STACK)
404 return false;
405 #endif
406
407 return true;
408 }
409
410 static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
411 struct mmc_data *data)
412 {
413 struct uniphier_sd_priv *priv = dev_get_priv(dev);
414 int ret;
415 u32 tmp;
416
417 if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
418 dev_err(dev, "command busy\n");
419 return -EBUSY;
420 }
421
422 /* clear all status flags */
423 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1);
424 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
425
426 /* disable DMA once */
427 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
428 tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN;
429 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
430
431 uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG);
432
433 tmp = cmd->cmdidx;
434
435 if (data) {
436 uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE);
437 uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT);
438
439 /* Do not send CMD12 automatically */
440 tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA;
441
442 if (data->blocks > 1)
443 tmp |= UNIPHIER_SD_CMD_MULTI;
444
445 if (data->flags & MMC_DATA_READ)
446 tmp |= UNIPHIER_SD_CMD_RD;
447 }
448
449 /*
450 * Do not use the response type auto-detection on this hardware.
451 * CMD8, for example, has different response types on SD and eMMC,
452 * while this controller always assumes the response type for SD.
453 * Set the response type manually.
454 */
455 switch (cmd->resp_type) {
456 case MMC_RSP_NONE:
457 tmp |= UNIPHIER_SD_CMD_RSP_NONE;
458 break;
459 case MMC_RSP_R1:
460 tmp |= UNIPHIER_SD_CMD_RSP_R1;
461 break;
462 case MMC_RSP_R1b:
463 tmp |= UNIPHIER_SD_CMD_RSP_R1B;
464 break;
465 case MMC_RSP_R2:
466 tmp |= UNIPHIER_SD_CMD_RSP_R2;
467 break;
468 case MMC_RSP_R3:
469 tmp |= UNIPHIER_SD_CMD_RSP_R3;
470 break;
471 default:
472 dev_err(dev, "unknown response type\n");
473 return -EINVAL;
474 }
475
476 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
477 cmd->cmdidx, tmp, cmd->cmdarg);
478 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD);
479
480 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
481 UNIPHIER_SD_INFO1_RSP);
482 if (ret)
483 return ret;
484
485 if (cmd->resp_type & MMC_RSP_136) {
486 u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76);
487 u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54);
488 u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32);
489 u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
490
491 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
492 ((rsp_103_72 & 0xff000000) >> 24);
493 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
494 ((rsp_71_40 & 0xff000000) >> 24);
495 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
496 ((rsp_39_8 & 0xff000000) >> 24);
497 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
498 } else {
499 /* bit 39-8 */
500 cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
501 }
502
503 if (data) {
504 /* use DMA if the HW supports it and the buffer is aligned */
505 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL &&
506 uniphier_sd_addr_is_dmaable((long)data->src))
507 ret = uniphier_sd_dma_xfer(dev, data);
508 else
509 ret = uniphier_sd_pio_xfer(dev, data);
510
511 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
512 UNIPHIER_SD_INFO1_CMP);
513 if (ret)
514 return ret;
515 }
516
517 return ret;
518 }
519
520 static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv,
521 struct mmc *mmc)
522 {
523 u32 val, tmp;
524
525 switch (mmc->bus_width) {
526 case 1:
527 val = UNIPHIER_SD_OPTION_WIDTH_1;
528 break;
529 case 4:
530 val = UNIPHIER_SD_OPTION_WIDTH_4;
531 break;
532 case 8:
533 val = UNIPHIER_SD_OPTION_WIDTH_8;
534 break;
535 default:
536 return -EINVAL;
537 }
538
539 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION);
540 tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK;
541 tmp |= val;
542 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION);
543
544 return 0;
545 }
546
547 static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv,
548 struct mmc *mmc)
549 {
550 u32 tmp;
551
552 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE);
553 if (mmc->ddr_mode)
554 tmp |= UNIPHIER_SD_IF_MODE_DDR;
555 else
556 tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
557 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE);
558 }
559
560 static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
561 struct mmc *mmc)
562 {
563 unsigned int divisor;
564 u32 val, tmp;
565
566 if (!mmc->clock)
567 return;
568
569 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
570
571 if (divisor <= 1)
572 val = UNIPHIER_SD_CLKCTL_DIV1;
573 else if (divisor <= 2)
574 val = UNIPHIER_SD_CLKCTL_DIV2;
575 else if (divisor <= 4)
576 val = UNIPHIER_SD_CLKCTL_DIV4;
577 else if (divisor <= 8)
578 val = UNIPHIER_SD_CLKCTL_DIV8;
579 else if (divisor <= 16)
580 val = UNIPHIER_SD_CLKCTL_DIV16;
581 else if (divisor <= 32)
582 val = UNIPHIER_SD_CLKCTL_DIV32;
583 else if (divisor <= 64)
584 val = UNIPHIER_SD_CLKCTL_DIV64;
585 else if (divisor <= 128)
586 val = UNIPHIER_SD_CLKCTL_DIV128;
587 else if (divisor <= 256)
588 val = UNIPHIER_SD_CLKCTL_DIV256;
589 else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024))
590 val = UNIPHIER_SD_CLKCTL_DIV512;
591 else
592 val = UNIPHIER_SD_CLKCTL_DIV1024;
593
594 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL);
595 if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN &&
596 (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val)
597 return;
598
599 /* stop the clock before changing its rate to avoid a glitch signal */
600 tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
601 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
602
603 tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK;
604 tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN;
605 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
606
607 tmp |= UNIPHIER_SD_CLKCTL_SCLKEN;
608 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
609
610 udelay(1000);
611 }
612
613 static int uniphier_sd_set_ios(struct udevice *dev)
614 {
615 struct uniphier_sd_priv *priv = dev_get_priv(dev);
616 struct mmc *mmc = mmc_get_mmc_dev(dev);
617 int ret;
618
619 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
620 mmc->clock, mmc->ddr_mode, mmc->bus_width);
621
622 ret = uniphier_sd_set_bus_width(priv, mmc);
623 if (ret)
624 return ret;
625 uniphier_sd_set_ddr_mode(priv, mmc);
626 uniphier_sd_set_clk_rate(priv, mmc);
627
628 return 0;
629 }
630
631 static int uniphier_sd_get_cd(struct udevice *dev)
632 {
633 struct uniphier_sd_priv *priv = dev_get_priv(dev);
634
635 if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE)
636 return 1;
637
638 return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) &
639 UNIPHIER_SD_INFO1_CD);
640 }
641
642 static const struct dm_mmc_ops uniphier_sd_ops = {
643 .send_cmd = uniphier_sd_send_cmd,
644 .set_ios = uniphier_sd_set_ios,
645 .get_cd = uniphier_sd_get_cd,
646 };
647
648 static void uniphier_sd_host_init(struct uniphier_sd_priv *priv)
649 {
650 u32 tmp;
651
652 /* soft reset of the host */
653 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST);
654 tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX;
655 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
656 tmp |= UNIPHIER_SD_SOFT_RST_RSTX;
657 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
658
659 /* FIXME: implement eMMC hw_reset */
660
661 uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP);
662
663 /*
664 * Connected to 32bit AXI.
665 * This register dropped backward compatibility at version 0x10.
666 * Write an appropriate value depending on the IP version.
667 */
668 uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000,
669 UNIPHIER_SD_HOST_MODE);
670
671 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) {
672 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
673 tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
674 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
675 }
676 }
677
678 static int uniphier_sd_bind(struct udevice *dev)
679 {
680 struct uniphier_sd_plat *plat = dev_get_platdata(dev);
681
682 return mmc_bind(dev, &plat->mmc, &plat->cfg);
683 }
684
685 static int uniphier_sd_probe(struct udevice *dev)
686 {
687 struct uniphier_sd_plat *plat = dev_get_platdata(dev);
688 struct uniphier_sd_priv *priv = dev_get_priv(dev);
689 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
690 fdt_addr_t base;
691 struct clk clk;
692 int ret;
693
694 base = devfdt_get_addr(dev);
695 if (base == FDT_ADDR_T_NONE)
696 return -EINVAL;
697
698 priv->regbase = devm_ioremap(dev, base, SZ_2K);
699 if (!priv->regbase)
700 return -ENOMEM;
701
702 ret = clk_get_by_index(dev, 0, &clk);
703 if (ret < 0) {
704 dev_err(dev, "failed to get host clock\n");
705 return ret;
706 }
707
708 /* set to max rate */
709 priv->mclk = clk_set_rate(&clk, ULONG_MAX);
710 if (IS_ERR_VALUE(priv->mclk)) {
711 dev_err(dev, "failed to set rate for host clock\n");
712 clk_free(&clk);
713 return priv->mclk;
714 }
715
716 ret = clk_enable(&clk);
717 clk_free(&clk);
718 if (ret) {
719 dev_err(dev, "failed to enable host clock\n");
720 return ret;
721 }
722
723 plat->cfg.name = dev->name;
724 plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
725
726 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
727 1)) {
728 case 8:
729 plat->cfg.host_caps |= MMC_MODE_8BIT;
730 break;
731 case 4:
732 plat->cfg.host_caps |= MMC_MODE_4BIT;
733 break;
734 case 1:
735 break;
736 default:
737 dev_err(dev, "Invalid \"bus-width\" value\n");
738 return -EINVAL;
739 }
740
741 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
742 NULL))
743 priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
744
745 priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) &
746 UNIPHIER_SD_VERSION_IP;
747 dev_dbg(dev, "version %x\n", priv->version);
748 if (priv->version >= 0x10) {
749 priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL;
750 priv->caps |= UNIPHIER_SD_CAP_DIV1024;
751 }
752
753 uniphier_sd_host_init(priv);
754
755 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
756 plat->cfg.f_min = priv->mclk /
757 (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512);
758 plat->cfg.f_max = priv->mclk;
759 plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
760
761 upriv->mmc = &plat->mmc;
762
763 return 0;
764 }
765
766 static const struct udevice_id uniphier_sd_match[] = {
767 { .compatible = "socionext,uniphier-sdhc" },
768 { /* sentinel */ }
769 };
770
771 U_BOOT_DRIVER(uniphier_mmc) = {
772 .name = "uniphier-mmc",
773 .id = UCLASS_MMC,
774 .of_match = uniphier_sd_match,
775 .bind = uniphier_sd_bind,
776 .probe = uniphier_sd_probe,
777 .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv),
778 .platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat),
779 .ops = &uniphier_sd_ops,
780 };
"Das U-Boot" Source Tree