2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/compat.h>
14 #include <linux/dma-direction.h>
16 #include <linux/sizes.h>
17 #include <asm/unaligned.h>
19 DECLARE_GLOBAL_DATA_PTR
;
21 #define UNIPHIER_SD_CMD 0x000 /* command */
22 #define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
23 #define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */
24 #define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */
25 #define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */
26 #define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
27 #define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
28 #define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */
29 #define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
30 #define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
31 #define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
32 #define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
33 #define UNIPHIER_SD_ARG 0x008 /* command argument */
34 #define UNIPHIER_SD_STOP 0x010 /* stop action control */
35 #define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */
36 #define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */
37 #define UNIPHIER_SD_SECCNT 0x014 /* sector counter */
38 #define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */
39 #define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */
40 #define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */
41 #define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */
42 #define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */
43 #define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */
44 #define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */
45 #define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */
46 #define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */
47 #define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */
48 #define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */
49 #define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
50 #define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */
51 #define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */
52 #define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */
53 #define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
54 #define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */
55 #define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
56 #define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
57 #define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */
58 #define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */
59 #define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
60 #define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
61 #define UNIPHIER_SD_INFO1_MASK 0x040
62 #define UNIPHIER_SD_INFO2_MASK 0x044
63 #define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */
64 #define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff
65 #define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
66 #define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
67 #define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
68 #define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
69 #define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
70 #define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
71 #define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
72 #define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
73 #define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
74 #define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
75 #define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
76 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
77 #define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
78 #define UNIPHIER_SD_SIZE 0x04c /* block size */
79 #define UNIPHIER_SD_OPTION 0x050
80 #define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13)
81 #define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13)
82 #define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13)
83 #define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13)
84 #define UNIPHIER_SD_BUF 0x060 /* read/write buffer */
85 #define UNIPHIER_SD_EXTMODE 0x1b0
86 #define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
87 #define UNIPHIER_SD_SOFT_RST 0x1c0
88 #define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
89 #define UNIPHIER_SD_VERSION 0x1c4 /* version register */
90 #define UNIPHIER_SD_VERSION_IP 0xff /* IP version */
91 #define UNIPHIER_SD_HOST_MODE 0x1c8
92 #define UNIPHIER_SD_IF_MODE 0x1cc
93 #define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */
94 #define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */
95 #define UNIPHIER_SD_VOLT_MASK (3 << 0)
96 #define UNIPHIER_SD_VOLT_OFF (0 << 0)
97 #define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */
98 #define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */
99 #define UNIPHIER_SD_DMA_MODE 0x410
100 #define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
101 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
102 #define UNIPHIER_SD_DMA_CTL 0x414
103 #define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
104 #define UNIPHIER_SD_DMA_RST 0x418
105 #define UNIPHIER_SD_DMA_RST_RD BIT(9)
106 #define UNIPHIER_SD_DMA_RST_WR BIT(8)
107 #define UNIPHIER_SD_DMA_INFO1 0x420
108 #define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/
109 #define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */
110 #define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
111 #define UNIPHIER_SD_DMA_INFO1_MASK 0x424
112 #define UNIPHIER_SD_DMA_INFO2 0x428
113 #define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17)
114 #define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16)
115 #define UNIPHIER_SD_DMA_INFO2_MASK 0x42c
116 #define UNIPHIER_SD_DMA_ADDR_L 0x440
117 #define UNIPHIER_SD_DMA_ADDR_H 0x444
119 /* alignment required by the DMA engine of this controller */
120 #define UNIPHIER_SD_DMA_MINALIGN 0x10
122 struct uniphier_sd_plat
{
123 struct mmc_config cfg
;
127 struct uniphier_sd_priv
{
128 void __iomem
*regbase
;
130 unsigned int version
;
132 #define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
133 #define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
134 #define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
135 #define UNIPHIER_SD_CAP_64BIT BIT(3) /* Controller is 64bit */
138 static u64
uniphier_sd_readq(struct uniphier_sd_priv
*priv
, const u32 reg
)
140 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
)
141 return readq(priv
->regbase
+ (reg
<< 1));
143 return readq(priv
->regbase
+ reg
);
146 static void uniphier_sd_writeq(struct uniphier_sd_priv
*priv
,
147 const u64 val
, const u32 reg
)
149 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
)
150 writeq(val
, priv
->regbase
+ (reg
<< 1));
152 writeq(val
, priv
->regbase
+ reg
);
155 static u32
uniphier_sd_readl(struct uniphier_sd_priv
*priv
, const u32 reg
)
157 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
)
158 return readl(priv
->regbase
+ (reg
<< 1));
160 return readl(priv
->regbase
+ reg
);
163 static void uniphier_sd_writel(struct uniphier_sd_priv
*priv
,
164 const u32 val
, const u32 reg
)
166 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
)
167 writel(val
, priv
->regbase
+ (reg
<< 1));
169 writel(val
, priv
->regbase
+ reg
);
172 static dma_addr_t
__dma_map_single(void *ptr
, size_t size
,
173 enum dma_data_direction dir
)
175 unsigned long addr
= (unsigned long)ptr
;
177 if (dir
== DMA_FROM_DEVICE
)
178 invalidate_dcache_range(addr
, addr
+ size
);
180 flush_dcache_range(addr
, addr
+ size
);
185 static void __dma_unmap_single(dma_addr_t addr
, size_t size
,
186 enum dma_data_direction dir
)
188 if (dir
!= DMA_TO_DEVICE
)
189 invalidate_dcache_range(addr
, addr
+ size
);
192 static int uniphier_sd_check_error(struct udevice
*dev
)
194 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
195 u32 info2
= uniphier_sd_readl(priv
, UNIPHIER_SD_INFO2
);
197 if (info2
& UNIPHIER_SD_INFO2_ERR_RTO
) {
199 * TIMEOUT must be returned for unsupported command. Do not
200 * display error log since this might be a part of sequence to
201 * distinguish between SD and MMC.
206 if (info2
& UNIPHIER_SD_INFO2_ERR_TO
) {
207 dev_err(dev
, "timeout error\n");
211 if (info2
& (UNIPHIER_SD_INFO2_ERR_END
| UNIPHIER_SD_INFO2_ERR_CRC
|
212 UNIPHIER_SD_INFO2_ERR_IDX
)) {
213 dev_err(dev
, "communication out of sync\n");
217 if (info2
& (UNIPHIER_SD_INFO2_ERR_ILA
| UNIPHIER_SD_INFO2_ERR_ILR
|
218 UNIPHIER_SD_INFO2_ERR_ILW
)) {
219 dev_err(dev
, "illegal access\n");
226 static int uniphier_sd_wait_for_irq(struct udevice
*dev
, unsigned int reg
,
229 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
233 while (!(uniphier_sd_readl(priv
, reg
) & flag
)) {
235 dev_err(dev
, "timeout\n");
239 ret
= uniphier_sd_check_error(dev
);
249 static int uniphier_sd_pio_read_one_block(struct udevice
*dev
, u32
**pbuf
,
252 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
255 /* wait until the buffer is filled with data */
256 ret
= uniphier_sd_wait_for_irq(dev
, UNIPHIER_SD_INFO2
,
257 UNIPHIER_SD_INFO2_BRE
);
262 * Clear the status flag _before_ read the buffer out because
263 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered.
265 uniphier_sd_writel(priv
, 0, UNIPHIER_SD_INFO2
);
267 if (likely(IS_ALIGNED((unsigned long)*pbuf
, 4))) {
268 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
) {
269 for (i
= 0; i
< blocksize
/ 8; i
++) {
271 data
= uniphier_sd_readq(priv
,
274 *(*pbuf
)++ = data
>> 32;
277 for (i
= 0; i
< blocksize
/ 4; i
++) {
279 data
= uniphier_sd_readl(priv
, UNIPHIER_SD_BUF
);
284 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
) {
285 for (i
= 0; i
< blocksize
/ 8; i
++) {
287 data
= uniphier_sd_readq(priv
,
289 put_unaligned(data
, (*pbuf
)++);
290 put_unaligned(data
>> 32, (*pbuf
)++);
293 for (i
= 0; i
< blocksize
/ 4; i
++) {
295 data
= uniphier_sd_readl(priv
, UNIPHIER_SD_BUF
);
296 put_unaligned(data
, (*pbuf
)++);
304 static int uniphier_sd_pio_write_one_block(struct udevice
*dev
,
305 const u32
**pbuf
, uint blocksize
)
307 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
310 /* wait until the buffer becomes empty */
311 ret
= uniphier_sd_wait_for_irq(dev
, UNIPHIER_SD_INFO2
,
312 UNIPHIER_SD_INFO2_BWE
);
316 uniphier_sd_writel(priv
, 0, UNIPHIER_SD_INFO2
);
318 if (likely(IS_ALIGNED((unsigned long)*pbuf
, 4))) {
319 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
) {
320 for (i
= 0; i
< blocksize
/ 8; i
++) {
321 u64 data
= *(*pbuf
)++;
322 data
|= (u64
)*(*pbuf
)++ << 32;
323 uniphier_sd_writeq(priv
, data
,
327 for (i
= 0; i
< blocksize
/ 4; i
++) {
328 uniphier_sd_writel(priv
, *(*pbuf
)++,
333 if (priv
->caps
& UNIPHIER_SD_CAP_64BIT
) {
334 for (i
= 0; i
< blocksize
/ 8; i
++) {
335 u64 data
= get_unaligned((*pbuf
)++);
336 data
|= (u64
)get_unaligned((*pbuf
)++) << 32;
337 uniphier_sd_writeq(priv
, data
,
341 for (i
= 0; i
< blocksize
/ 4; i
++) {
342 u32 data
= get_unaligned((*pbuf
)++);
343 uniphier_sd_writel(priv
, data
,
352 static int uniphier_sd_pio_xfer(struct udevice
*dev
, struct mmc_data
*data
)
354 u32
*dest
= (u32
*)data
->dest
;
355 const u32
*src
= (const u32
*)data
->src
;
358 for (i
= 0; i
< data
->blocks
; i
++) {
359 if (data
->flags
& MMC_DATA_READ
)
360 ret
= uniphier_sd_pio_read_one_block(dev
, &dest
,
363 ret
= uniphier_sd_pio_write_one_block(dev
, &src
,
372 static void uniphier_sd_dma_start(struct uniphier_sd_priv
*priv
,
377 uniphier_sd_writel(priv
, 0, UNIPHIER_SD_DMA_INFO1
);
378 uniphier_sd_writel(priv
, 0, UNIPHIER_SD_DMA_INFO2
);
381 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_EXTMODE
);
382 tmp
|= UNIPHIER_SD_EXTMODE_DMA_EN
;
383 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_EXTMODE
);
385 uniphier_sd_writel(priv
, dma_addr
& U32_MAX
, UNIPHIER_SD_DMA_ADDR_L
);
387 /* suppress the warning "right shift count >= width of type" */
388 dma_addr
>>= min_t(int, 32, 8 * sizeof(dma_addr
));
390 uniphier_sd_writel(priv
, dma_addr
& U32_MAX
, UNIPHIER_SD_DMA_ADDR_H
);
392 uniphier_sd_writel(priv
, UNIPHIER_SD_DMA_CTL_START
, UNIPHIER_SD_DMA_CTL
);
395 static int uniphier_sd_dma_wait_for_irq(struct udevice
*dev
, u32 flag
,
398 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
399 long wait
= 1000000 + 10 * blocks
;
401 while (!(uniphier_sd_readl(priv
, UNIPHIER_SD_DMA_INFO1
) & flag
)) {
403 dev_err(dev
, "timeout during DMA\n");
410 if (uniphier_sd_readl(priv
, UNIPHIER_SD_DMA_INFO2
)) {
411 dev_err(dev
, "error during DMA\n");
418 static int uniphier_sd_dma_xfer(struct udevice
*dev
, struct mmc_data
*data
)
420 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
421 size_t len
= data
->blocks
* data
->blocksize
;
423 enum dma_data_direction dir
;
428 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_DMA_MODE
);
430 if (data
->flags
& MMC_DATA_READ
) {
432 dir
= DMA_FROM_DEVICE
;
433 poll_flag
= UNIPHIER_SD_DMA_INFO1_END_RD2
;
434 tmp
|= UNIPHIER_SD_DMA_MODE_DIR_RD
;
436 buf
= (void *)data
->src
;
438 poll_flag
= UNIPHIER_SD_DMA_INFO1_END_WR
;
439 tmp
&= ~UNIPHIER_SD_DMA_MODE_DIR_RD
;
442 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_DMA_MODE
);
444 dma_addr
= __dma_map_single(buf
, len
, dir
);
446 uniphier_sd_dma_start(priv
, dma_addr
);
448 ret
= uniphier_sd_dma_wait_for_irq(dev
, poll_flag
, data
->blocks
);
450 __dma_unmap_single(dma_addr
, len
, dir
);
455 /* check if the address is DMA'able */
456 static bool uniphier_sd_addr_is_dmaable(unsigned long addr
)
458 if (!IS_ALIGNED(addr
, UNIPHIER_SD_DMA_MINALIGN
))
461 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
462 defined(CONFIG_SPL_BUILD)
464 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
465 * of L2, which is unreachable from the DMA engine.
467 if (addr
< CONFIG_SPL_STACK
)
474 static int uniphier_sd_send_cmd(struct udevice
*dev
, struct mmc_cmd
*cmd
,
475 struct mmc_data
*data
)
477 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
481 if (uniphier_sd_readl(priv
, UNIPHIER_SD_INFO2
) & UNIPHIER_SD_INFO2_CBSY
) {
482 dev_err(dev
, "command busy\n");
486 /* clear all status flags */
487 uniphier_sd_writel(priv
, 0, UNIPHIER_SD_INFO1
);
488 uniphier_sd_writel(priv
, 0, UNIPHIER_SD_INFO2
);
490 /* disable DMA once */
491 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_EXTMODE
);
492 tmp
&= ~UNIPHIER_SD_EXTMODE_DMA_EN
;
493 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_EXTMODE
);
495 uniphier_sd_writel(priv
, cmd
->cmdarg
, UNIPHIER_SD_ARG
);
500 uniphier_sd_writel(priv
, data
->blocksize
, UNIPHIER_SD_SIZE
);
501 uniphier_sd_writel(priv
, data
->blocks
, UNIPHIER_SD_SECCNT
);
503 /* Do not send CMD12 automatically */
504 tmp
|= UNIPHIER_SD_CMD_NOSTOP
| UNIPHIER_SD_CMD_DATA
;
506 if (data
->blocks
> 1)
507 tmp
|= UNIPHIER_SD_CMD_MULTI
;
509 if (data
->flags
& MMC_DATA_READ
)
510 tmp
|= UNIPHIER_SD_CMD_RD
;
514 * Do not use the response type auto-detection on this hardware.
515 * CMD8, for example, has different response types on SD and eMMC,
516 * while this controller always assumes the response type for SD.
517 * Set the response type manually.
519 switch (cmd
->resp_type
) {
521 tmp
|= UNIPHIER_SD_CMD_RSP_NONE
;
524 tmp
|= UNIPHIER_SD_CMD_RSP_R1
;
527 tmp
|= UNIPHIER_SD_CMD_RSP_R1B
;
530 tmp
|= UNIPHIER_SD_CMD_RSP_R2
;
533 tmp
|= UNIPHIER_SD_CMD_RSP_R3
;
536 dev_err(dev
, "unknown response type\n");
540 dev_dbg(dev
, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
541 cmd
->cmdidx
, tmp
, cmd
->cmdarg
);
542 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_CMD
);
544 ret
= uniphier_sd_wait_for_irq(dev
, UNIPHIER_SD_INFO1
,
545 UNIPHIER_SD_INFO1_RSP
);
549 if (cmd
->resp_type
& MMC_RSP_136
) {
550 u32 rsp_127_104
= uniphier_sd_readl(priv
, UNIPHIER_SD_RSP76
);
551 u32 rsp_103_72
= uniphier_sd_readl(priv
, UNIPHIER_SD_RSP54
);
552 u32 rsp_71_40
= uniphier_sd_readl(priv
, UNIPHIER_SD_RSP32
);
553 u32 rsp_39_8
= uniphier_sd_readl(priv
, UNIPHIER_SD_RSP10
);
555 cmd
->response
[0] = ((rsp_127_104
& 0x00ffffff) << 8) |
556 ((rsp_103_72
& 0xff000000) >> 24);
557 cmd
->response
[1] = ((rsp_103_72
& 0x00ffffff) << 8) |
558 ((rsp_71_40
& 0xff000000) >> 24);
559 cmd
->response
[2] = ((rsp_71_40
& 0x00ffffff) << 8) |
560 ((rsp_39_8
& 0xff000000) >> 24);
561 cmd
->response
[3] = (rsp_39_8
& 0xffffff) << 8;
564 cmd
->response
[0] = uniphier_sd_readl(priv
, UNIPHIER_SD_RSP10
);
568 /* use DMA if the HW supports it and the buffer is aligned */
569 if (priv
->caps
& UNIPHIER_SD_CAP_DMA_INTERNAL
&&
570 uniphier_sd_addr_is_dmaable((long)data
->src
))
571 ret
= uniphier_sd_dma_xfer(dev
, data
);
573 ret
= uniphier_sd_pio_xfer(dev
, data
);
575 ret
= uniphier_sd_wait_for_irq(dev
, UNIPHIER_SD_INFO1
,
576 UNIPHIER_SD_INFO1_CMP
);
584 static int uniphier_sd_set_bus_width(struct uniphier_sd_priv
*priv
,
589 switch (mmc
->bus_width
) {
591 val
= UNIPHIER_SD_OPTION_WIDTH_1
;
594 val
= UNIPHIER_SD_OPTION_WIDTH_4
;
597 val
= UNIPHIER_SD_OPTION_WIDTH_8
;
603 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_OPTION
);
604 tmp
&= ~UNIPHIER_SD_OPTION_WIDTH_MASK
;
606 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_OPTION
);
611 static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv
*priv
,
616 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_IF_MODE
);
618 tmp
|= UNIPHIER_SD_IF_MODE_DDR
;
620 tmp
&= ~UNIPHIER_SD_IF_MODE_DDR
;
621 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_IF_MODE
);
624 static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv
*priv
,
627 unsigned int divisor
;
633 divisor
= DIV_ROUND_UP(priv
->mclk
, mmc
->clock
);
636 val
= UNIPHIER_SD_CLKCTL_DIV1
;
637 else if (divisor
<= 2)
638 val
= UNIPHIER_SD_CLKCTL_DIV2
;
639 else if (divisor
<= 4)
640 val
= UNIPHIER_SD_CLKCTL_DIV4
;
641 else if (divisor
<= 8)
642 val
= UNIPHIER_SD_CLKCTL_DIV8
;
643 else if (divisor
<= 16)
644 val
= UNIPHIER_SD_CLKCTL_DIV16
;
645 else if (divisor
<= 32)
646 val
= UNIPHIER_SD_CLKCTL_DIV32
;
647 else if (divisor
<= 64)
648 val
= UNIPHIER_SD_CLKCTL_DIV64
;
649 else if (divisor
<= 128)
650 val
= UNIPHIER_SD_CLKCTL_DIV128
;
651 else if (divisor
<= 256)
652 val
= UNIPHIER_SD_CLKCTL_DIV256
;
653 else if (divisor
<= 512 || !(priv
->caps
& UNIPHIER_SD_CAP_DIV1024
))
654 val
= UNIPHIER_SD_CLKCTL_DIV512
;
656 val
= UNIPHIER_SD_CLKCTL_DIV1024
;
658 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_CLKCTL
);
659 if (tmp
& UNIPHIER_SD_CLKCTL_SCLKEN
&&
660 (tmp
& UNIPHIER_SD_CLKCTL_DIV_MASK
) == val
)
663 /* stop the clock before changing its rate to avoid a glitch signal */
664 tmp
&= ~UNIPHIER_SD_CLKCTL_SCLKEN
;
665 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_CLKCTL
);
667 tmp
&= ~UNIPHIER_SD_CLKCTL_DIV_MASK
;
668 tmp
|= val
| UNIPHIER_SD_CLKCTL_OFFEN
;
669 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_CLKCTL
);
671 tmp
|= UNIPHIER_SD_CLKCTL_SCLKEN
;
672 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_CLKCTL
);
677 static int uniphier_sd_set_ios(struct udevice
*dev
)
679 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
680 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
683 dev_dbg(dev
, "clock %uHz, DDRmode %d, width %u\n",
684 mmc
->clock
, mmc
->ddr_mode
, mmc
->bus_width
);
686 ret
= uniphier_sd_set_bus_width(priv
, mmc
);
689 uniphier_sd_set_ddr_mode(priv
, mmc
);
690 uniphier_sd_set_clk_rate(priv
, mmc
);
695 static int uniphier_sd_get_cd(struct udevice
*dev
)
697 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
699 if (priv
->caps
& UNIPHIER_SD_CAP_NONREMOVABLE
)
702 return !!(uniphier_sd_readl(priv
, UNIPHIER_SD_INFO1
) &
703 UNIPHIER_SD_INFO1_CD
);
706 static const struct dm_mmc_ops uniphier_sd_ops
= {
707 .send_cmd
= uniphier_sd_send_cmd
,
708 .set_ios
= uniphier_sd_set_ios
,
709 .get_cd
= uniphier_sd_get_cd
,
712 static void uniphier_sd_host_init(struct uniphier_sd_priv
*priv
)
716 /* soft reset of the host */
717 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_SOFT_RST
);
718 tmp
&= ~UNIPHIER_SD_SOFT_RST_RSTX
;
719 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_SOFT_RST
);
720 tmp
|= UNIPHIER_SD_SOFT_RST_RSTX
;
721 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_SOFT_RST
);
723 /* FIXME: implement eMMC hw_reset */
725 uniphier_sd_writel(priv
, UNIPHIER_SD_STOP_SEC
, UNIPHIER_SD_STOP
);
728 * Connected to 32bit AXI.
729 * This register dropped backward compatibility at version 0x10.
730 * Write an appropriate value depending on the IP version.
732 uniphier_sd_writel(priv
, priv
->version
>= 0x10 ? 0x00000101 : 0x00000000,
733 UNIPHIER_SD_HOST_MODE
);
735 if (priv
->caps
& UNIPHIER_SD_CAP_DMA_INTERNAL
) {
736 tmp
= uniphier_sd_readl(priv
, UNIPHIER_SD_DMA_MODE
);
737 tmp
|= UNIPHIER_SD_DMA_MODE_ADDR_INC
;
738 uniphier_sd_writel(priv
, tmp
, UNIPHIER_SD_DMA_MODE
);
742 static int uniphier_sd_bind(struct udevice
*dev
)
744 struct uniphier_sd_plat
*plat
= dev_get_platdata(dev
);
746 return mmc_bind(dev
, &plat
->mmc
, &plat
->cfg
);
749 static int uniphier_sd_probe(struct udevice
*dev
)
751 struct uniphier_sd_plat
*plat
= dev_get_platdata(dev
);
752 struct uniphier_sd_priv
*priv
= dev_get_priv(dev
);
753 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
754 const u32 quirks
= dev_get_driver_data(dev
);
759 base
= devfdt_get_addr(dev
);
760 if (base
== FDT_ADDR_T_NONE
)
763 priv
->regbase
= devm_ioremap(dev
, base
, SZ_2K
);
767 ret
= clk_get_by_index(dev
, 0, &clk
);
769 dev_err(dev
, "failed to get host clock\n");
773 /* set to max rate */
774 priv
->mclk
= clk_set_rate(&clk
, ULONG_MAX
);
775 if (IS_ERR_VALUE(priv
->mclk
)) {
776 dev_err(dev
, "failed to set rate for host clock\n");
781 ret
= clk_enable(&clk
);
784 dev_err(dev
, "failed to enable host clock\n");
788 plat
->cfg
.name
= dev
->name
;
789 plat
->cfg
.host_caps
= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
791 switch (fdtdec_get_int(gd
->fdt_blob
, dev_of_offset(dev
), "bus-width",
794 plat
->cfg
.host_caps
|= MMC_MODE_8BIT
;
797 plat
->cfg
.host_caps
|= MMC_MODE_4BIT
;
802 dev_err(dev
, "Invalid \"bus-width\" value\n");
809 priv
->version
= uniphier_sd_readl(priv
, UNIPHIER_SD_VERSION
) &
810 UNIPHIER_SD_VERSION_IP
;
811 dev_dbg(dev
, "version %x\n", priv
->version
);
812 if (priv
->version
>= 0x10) {
813 priv
->caps
|= UNIPHIER_SD_CAP_DMA_INTERNAL
;
814 priv
->caps
|= UNIPHIER_SD_CAP_DIV1024
;
818 if (fdt_get_property(gd
->fdt_blob
, dev_of_offset(dev
), "non-removable",
820 priv
->caps
|= UNIPHIER_SD_CAP_NONREMOVABLE
;
822 uniphier_sd_host_init(priv
);
824 plat
->cfg
.voltages
= MMC_VDD_165_195
| MMC_VDD_32_33
| MMC_VDD_33_34
;
825 plat
->cfg
.f_min
= priv
->mclk
/
826 (priv
->caps
& UNIPHIER_SD_CAP_DIV1024
? 1024 : 512);
827 plat
->cfg
.f_max
= priv
->mclk
;
828 plat
->cfg
.b_max
= U32_MAX
; /* max value of UNIPHIER_SD_SECCNT */
830 upriv
->mmc
= &plat
->mmc
;
835 static const struct udevice_id uniphier_sd_match
[] = {
836 { .compatible
= "socionext,uniphier-sdhc", .data
= 0 },
840 U_BOOT_DRIVER(uniphier_mmc
) = {
841 .name
= "uniphier-mmc",
843 .of_match
= uniphier_sd_match
,
844 .bind
= uniphier_sd_bind
,
845 .probe
= uniphier_sd_probe
,
846 .priv_auto_alloc_size
= sizeof(struct uniphier_sd_priv
),
847 .platdata_auto_alloc_size
= sizeof(struct uniphier_sd_plat
),
848 .ops
= &uniphier_sd_ops
,