drivers/mmc/uniphier-sd.c

   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <fdtdec.h>
  11 #include <mmc.h>
  12 #include <dm.h>
  13 #include <linux/compat.h>
  14 #include <linux/dma-direction.h>
  15 #include <linux/io.h>
  16 #include <linux/sizes.h>
  17 #include <asm/unaligned.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #define UNIPHIER_SD_CMD                 0x000   /* command */
  22 #define   UNIPHIER_SD_CMD_NOSTOP        BIT(14) /* No automatic CMD12 issue */
  23 #define   UNIPHIER_SD_CMD_MULTI         BIT(13) /* multiple block transfer */
  24 #define   UNIPHIER_SD_CMD_RD            BIT(12) /* 1: read, 0: write */
  25 #define   UNIPHIER_SD_CMD_DATA          BIT(11) /* data transfer */
  26 #define   UNIPHIER_SD_CMD_APP           BIT(6)  /* ACMD preceded by CMD55 */
  27 #define   UNIPHIER_SD_CMD_NORMAL        (0 << 8)/* auto-detect of resp-type */
  28 #define   UNIPHIER_SD_CMD_RSP_NONE      (3 << 8)/* response: none */
  29 #define   UNIPHIER_SD_CMD_RSP_R1        (4 << 8)/* response: R1, R5, R6, R7 */
  30 #define   UNIPHIER_SD_CMD_RSP_R1B       (5 << 8)/* response: R1b, R5b */
  31 #define   UNIPHIER_SD_CMD_RSP_R2        (6 << 8)/* response: R2 */
  32 #define   UNIPHIER_SD_CMD_RSP_R3        (7 << 8)/* response: R3, R4 */
  33 #define UNIPHIER_SD_ARG                 0x008   /* command argument */
  34 #define UNIPHIER_SD_STOP                0x010   /* stop action control */
  35 #define   UNIPHIER_SD_STOP_SEC          BIT(8)  /* use sector count */
  36 #define   UNIPHIER_SD_STOP_STP          BIT(0)  /* issue CMD12 */
  37 #define UNIPHIER_SD_SECCNT              0x014   /* sector counter */
  38 #define UNIPHIER_SD_RSP10               0x018   /* response[39:8] */
  39 #define UNIPHIER_SD_RSP32               0x020   /* response[71:40] */
  40 #define UNIPHIER_SD_RSP54               0x028   /* response[103:72] */
  41 #define UNIPHIER_SD_RSP76               0x030   /* response[127:104] */
  42 #define UNIPHIER_SD_INFO1               0x038   /* IRQ status 1 */
  43 #define   UNIPHIER_SD_INFO1_CD          BIT(5)  /* state of card detect */
  44 #define   UNIPHIER_SD_INFO1_INSERT      BIT(4)  /* card inserted */
  45 #define   UNIPHIER_SD_INFO1_REMOVE      BIT(3)  /* card removed */
  46 #define   UNIPHIER_SD_INFO1_CMP         BIT(2)  /* data complete */
  47 #define   UNIPHIER_SD_INFO1_RSP         BIT(0)  /* response complete */
  48 #define UNIPHIER_SD_INFO2               0x03c   /* IRQ status 2 */
  49 #define   UNIPHIER_SD_INFO2_ERR_ILA     BIT(15) /* illegal access err */
  50 #define   UNIPHIER_SD_INFO2_CBSY        BIT(14) /* command busy */
  51 #define   UNIPHIER_SD_INFO2_BWE         BIT(9)  /* write buffer ready */
  52 #define   UNIPHIER_SD_INFO2_BRE         BIT(8)  /* read buffer ready */
  53 #define   UNIPHIER_SD_INFO2_DAT0        BIT(7)  /* SDDAT0 */
  54 #define   UNIPHIER_SD_INFO2_ERR_RTO     BIT(6)  /* response time out */
  55 #define   UNIPHIER_SD_INFO2_ERR_ILR     BIT(5)  /* illegal read err */
  56 #define   UNIPHIER_SD_INFO2_ERR_ILW     BIT(4)  /* illegal write err */
  57 #define   UNIPHIER_SD_INFO2_ERR_TO      BIT(3)  /* time out error */
  58 #define   UNIPHIER_SD_INFO2_ERR_END     BIT(2)  /* END bit error */
  59 #define   UNIPHIER_SD_INFO2_ERR_CRC     BIT(1)  /* CRC error */
  60 #define   UNIPHIER_SD_INFO2_ERR_IDX     BIT(0)  /* cmd index error */
  61 #define UNIPHIER_SD_INFO1_MASK          0x040
  62 #define UNIPHIER_SD_INFO2_MASK          0x044
  63 #define UNIPHIER_SD_CLKCTL              0x048   /* clock divisor */
  64 #define   UNIPHIER_SD_CLKCTL_DIV_MASK   0x104ff
  65 #define   UNIPHIER_SD_CLKCTL_DIV1024    BIT(16) /* SDCLK = CLK / 1024 */
  66 #define   UNIPHIER_SD_CLKCTL_DIV512     BIT(7)  /* SDCLK = CLK / 512 */
  67 #define   UNIPHIER_SD_CLKCTL_DIV256     BIT(6)  /* SDCLK = CLK / 256 */
  68 #define   UNIPHIER_SD_CLKCTL_DIV128     BIT(5)  /* SDCLK = CLK / 128 */
  69 #define   UNIPHIER_SD_CLKCTL_DIV64      BIT(4)  /* SDCLK = CLK / 64 */
  70 #define   UNIPHIER_SD_CLKCTL_DIV32      BIT(3)  /* SDCLK = CLK / 32 */
  71 #define   UNIPHIER_SD_CLKCTL_DIV16      BIT(2)  /* SDCLK = CLK / 16 */
  72 #define   UNIPHIER_SD_CLKCTL_DIV8       BIT(1)  /* SDCLK = CLK / 8 */
  73 #define   UNIPHIER_SD_CLKCTL_DIV4       BIT(0)  /* SDCLK = CLK / 4 */
  74 #define   UNIPHIER_SD_CLKCTL_DIV2       0       /* SDCLK = CLK / 2 */
  75 #define   UNIPHIER_SD_CLKCTL_DIV1       BIT(10) /* SDCLK = CLK */
  76 #define   UNIPHIER_SD_CLKCTL_OFFEN      BIT(9)  /* stop SDCLK when unused */
  77 #define   UNIPHIER_SD_CLKCTL_SCLKEN     BIT(8)  /* SDCLK output enable */
  78 #define UNIPHIER_SD_SIZE                0x04c   /* block size */
  79 #define UNIPHIER_SD_OPTION              0x050
  80 #define   UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13)
  81 #define   UNIPHIER_SD_OPTION_WIDTH_1    (4 << 13)
  82 #define   UNIPHIER_SD_OPTION_WIDTH_4    (0 << 13)
  83 #define   UNIPHIER_SD_OPTION_WIDTH_8    (1 << 13)
  84 #define UNIPHIER_SD_BUF                 0x060   /* read/write buffer */
  85 #define UNIPHIER_SD_EXTMODE             0x1b0
  86 #define   UNIPHIER_SD_EXTMODE_DMA_EN    BIT(1)  /* transfer 1: DMA, 0: pio */
  87 #define UNIPHIER_SD_SOFT_RST            0x1c0
  88 #define UNIPHIER_SD_SOFT_RST_RSTX       BIT(0)  /* reset deassert */
  89 #define UNIPHIER_SD_VERSION             0x1c4   /* version register */
  90 #define UNIPHIER_SD_VERSION_IP          0xff    /* IP version */
  91 #define UNIPHIER_SD_HOST_MODE           0x1c8
  92 #define UNIPHIER_SD_IF_MODE             0x1cc
  93 #define   UNIPHIER_SD_IF_MODE_DDR       BIT(0)  /* DDR mode */
  94 #define UNIPHIER_SD_VOLT                0x1e4   /* voltage switch */
  95 #define   UNIPHIER_SD_VOLT_MASK         (3 << 0)
  96 #define   UNIPHIER_SD_VOLT_OFF          (0 << 0)
  97 #define   UNIPHIER_SD_VOLT_330          (1 << 0)/* 3.3V signal */
  98 #define   UNIPHIER_SD_VOLT_180          (2 << 0)/* 1.8V signal */
  99 #define UNIPHIER_SD_DMA_MODE            0x410
 100 #define   UNIPHIER_SD_DMA_MODE_DIR_RD   BIT(16) /* 1: from device, 0: to dev */
 101 #define   UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0)  /* 1: address inc, 0: fixed */
 102 #define UNIPHIER_SD_DMA_CTL             0x414
 103 #define   UNIPHIER_SD_DMA_CTL_START     BIT(0)  /* start DMA (auto cleared) */
 104 #define UNIPHIER_SD_DMA_RST             0x418
 105 #define   UNIPHIER_SD_DMA_RST_RD        BIT(9)
 106 #define   UNIPHIER_SD_DMA_RST_WR        BIT(8)
 107 #define UNIPHIER_SD_DMA_INFO1           0x420
 108 #define   UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/
 109 #define   UNIPHIER_SD_DMA_INFO1_END_RD  BIT(17) /* Don't use!  Hardware bug */
 110 #define   UNIPHIER_SD_DMA_INFO1_END_WR  BIT(16) /* DMA to device is complete */
 111 #define UNIPHIER_SD_DMA_INFO1_MASK      0x424
 112 #define UNIPHIER_SD_DMA_INFO2           0x428
 113 #define   UNIPHIER_SD_DMA_INFO2_ERR_RD  BIT(17)
 114 #define   UNIPHIER_SD_DMA_INFO2_ERR_WR  BIT(16)
 115 #define UNIPHIER_SD_DMA_INFO2_MASK      0x42c
 116 #define UNIPHIER_SD_DMA_ADDR_L          0x440
 117 #define UNIPHIER_SD_DMA_ADDR_H          0x444
 118
 119 /* alignment required by the DMA engine of this controller */
 120 #define UNIPHIER_SD_DMA_MINALIGN        0x10
 121
 122 struct uniphier_sd_plat {
 123         struct mmc_config cfg;
 124         struct mmc mmc;
 125 };
 126
 127 struct uniphier_sd_priv {
 128         void __iomem *regbase;
 129         unsigned long mclk;
 130         unsigned int version;
 131         u32 caps;
 132 #define UNIPHIER_SD_CAP_NONREMOVABLE    BIT(0)  /* Nonremovable e.g. eMMC */
 133 #define UNIPHIER_SD_CAP_DMA_INTERNAL    BIT(1)  /* have internal DMA engine */
 134 #define UNIPHIER_SD_CAP_DIV1024         BIT(2)  /* divisor 1024 is available */
 135 #define UNIPHIER_SD_CAP_64BIT           BIT(3)  /* Controller is 64bit */
 136 };
 137
 138 static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, const u32 reg)
 139 {
 140         if (priv->caps & UNIPHIER_SD_CAP_64BIT)
 141                 return readq(priv->regbase + (reg << 1));
 142         else
 143                 return readq(priv->regbase + reg);
 144 }
 145
 146 static void uniphier_sd_writeq(struct uniphier_sd_priv *priv,
 147                                const u64 val, const u32 reg)
 148 {
 149         if (priv->caps & UNIPHIER_SD_CAP_64BIT)
 150                 writeq(val, priv->regbase + (reg << 1));
 151         else
 152                 writeq(val, priv->regbase + reg);
 153 }
 154
 155 static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, const u32 reg)
 156 {
 157         if (priv->caps & UNIPHIER_SD_CAP_64BIT)
 158                 return readl(priv->regbase + (reg << 1));
 159         else
 160                 return readl(priv->regbase + reg);
 161 }
 162
 163 static void uniphier_sd_writel(struct uniphier_sd_priv *priv,
 164                                const u32 val, const u32 reg)
 165 {
 166         if (priv->caps & UNIPHIER_SD_CAP_64BIT)
 167                 writel(val, priv->regbase + (reg << 1));
 168         else
 169                 writel(val, priv->regbase + reg);
 170 }
 171
 172 static dma_addr_t __dma_map_single(void *ptr, size_t size,
 173                                    enum dma_data_direction dir)
 174 {
 175         unsigned long addr = (unsigned long)ptr;
 176
 177         if (dir == DMA_FROM_DEVICE)
 178                 invalidate_dcache_range(addr, addr + size);
 179         else
 180                 flush_dcache_range(addr, addr + size);
 181
 182         return addr;
 183 }
 184
 185 static void __dma_unmap_single(dma_addr_t addr, size_t size,
 186                                enum dma_data_direction dir)
 187 {
 188         if (dir != DMA_TO_DEVICE)
 189                 invalidate_dcache_range(addr, addr + size);
 190 }
 191
 192 static int uniphier_sd_check_error(struct udevice *dev)
 193 {
 194         struct uniphier_sd_priv *priv = dev_get_priv(dev);
 195         u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2);
 196
 197         if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) {
 198                 /*
 199                  * TIMEOUT must be returned for unsupported command.  Do not
 200                  * display error log since this might be a part of sequence to
 201                  * distinguish between SD and MMC.
 202                  */
 203                 return -ETIMEDOUT;
 204         }
 205
 206         if (info2 & UNIPHIER_SD_INFO2_ERR_TO) {
 207                 dev_err(dev, "timeout error\n");
 208                 return -ETIMEDOUT;
 209         }
 210
 211         if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC |
 212                      UNIPHIER_SD_INFO2_ERR_IDX)) {
 213                 dev_err(dev, "communication out of sync\n");
 214                 return -EILSEQ;
 215         }
 216
 217         if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR |
 218                      UNIPHIER_SD_INFO2_ERR_ILW)) {
 219                 dev_err(dev, "illegal access\n");
 220                 return -EIO;
 221         }
 222
 223         return 0;
 224 }
 225
 226 static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
 227                                     u32 flag)
 228 {
 229         struct uniphier_sd_priv *priv = dev_get_priv(dev);
 230         long wait = 1000000;
 231         int ret;
 232
 233         while (!(uniphier_sd_readl(priv, reg) & flag)) {
 234                 if (wait-- < 0) {
 235                         dev_err(dev, "timeout\n");
 236                         return -ETIMEDOUT;
 237                 }
 238
 239                 ret = uniphier_sd_check_error(dev);
 240                 if (ret)
 241                         return ret;
 242
 243                 udelay(1);
 244         }
 245
 246         return 0;
 247 }
 248
 249 static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
 250                                           uint blocksize)
 251 {
 252         struct uniphier_sd_priv *priv = dev_get_priv(dev);
 253         int i, ret;
 254
 255         /* wait until the buffer is filled with data */
 256         ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
 257                                        UNIPHIER_SD_INFO2_BRE);
 258         if (ret)
 259                 return ret;
 260
 261         /*
 262          * Clear the status flag _before_ read the buffer out because
 263          * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered.
 264          */
 265         uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
 266
 267         if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
 268                 if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
 269                         for (i = 0; i < blocksize / 8; i++) {
 270                                 u64 data;
 271                                 data = uniphier_sd_readq(priv,
 272                                                          UNIPHIER_SD_BUF);
 273                                 *(*pbuf)++ = data;
 274                                 *(*pbuf)++ = data >> 32;
 275                         }
 276                 } else {
 277                         for (i = 0; i < blocksize / 4; i++) {
 278                                 u32 data;
 279                                 data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
 280                                 *(*pbuf)++ = data;
 281                         }
 282                 }
 283         } else {
 284                 if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
 285                         for (i = 0; i < blocksize / 8; i++) {
 286                                 u64 data;
 287                                 data = uniphier_sd_readq(priv,
 288                                                          UNIPHIER_SD_BUF);
 289                                 put_unaligned(data, (*pbuf)++);
 290                                 put_unaligned(data >> 32, (*pbuf)++);
 291                         }
 292                 } else {
 293                         for (i = 0; i < blocksize / 4; i++) {
 294                                 u32 data;
 295                                 data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
 296                                 put_unaligned(data, (*pbuf)++);
 297                         }
 298                 }
 299         }
 300
 301         return 0;
 302 }
 303
 304 static int uniphier_sd_pio_write_one_block(struct udevice *dev,
 305                                            const u32 **pbuf, uint blocksize)
 306 {
 307         struct uniphier_sd_priv *priv = dev_get_priv(dev);
 308         int i, ret;
 309
 310         /* wait until the buffer becomes empty */
 311         ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
 312                                        UNIPHIER_SD_INFO2_BWE);
 313         if (ret)
 314                 return ret;
 315
 316         uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
 317
 318         if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
 319                 if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
 320                         for (i = 0; i < blocksize / 8; i++) {
 321                                 u64 data = *(*pbuf)++;
 322                                 data |= (u64)*(*pbuf)++ << 32;
 323                                 uniphier_sd_writeq(priv, data,
 324                                                    UNIPHIER_SD_BUF);
 325                         }
 326                 } else {
 327                         for (i = 0; i < blocksize / 4; i++) {
 328                                 uniphier_sd_writel(priv, *(*pbuf)++,
 329                                                    UNIPHIER_SD_BUF);
 330                         }
 331                 }
 332         } else {
 333                 if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
 334                         for (i = 0; i < blocksize / 8; i++) {
 335                                 u64 data = get_unaligned((*pbuf)++);
 336                                 data |= (u64)get_unaligned((*pbuf)++) << 32;
 337                                 uniphier_sd_writeq(priv, data,
 338                                                    UNIPHIER_SD_BUF);
 339                         }
 340                 } else {
 341                         for (i = 0; i < blocksize / 4; i++) {
 342                                 u32 data = get_unaligned((*pbuf)++);
 343                                 uniphier_sd_writel(priv, data,
 344                                                    UNIPHIER_SD_BUF);
 345                         }
 346                 }
 347         }
 348
 349         return 0;
 350 }
 351
 352 static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
 353 {
 354         u32 *dest = (u32 *)data->dest;
 355         const u32 *src = (const u32 *)data->src;
 356         int i, ret;
 357
 358         for (i = 0; i < data->blocks; i++) {
 359                 if (data->flags & MMC_DATA_READ)
 360                         ret = uniphier_sd_pio_read_one_block(dev, &dest,
 361                                                              data->blocksize);
 362                 else
 363                         ret = uniphier_sd_pio_write_one_block(dev, &src,
 364                                                               data->blocksize);
 365                 if (ret)
 366                         return ret;
 367         }
 368
 369         return 0;
 370 }
 371
 372 static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv,
 373                                   dma_addr_t dma_addr)
 374 {
 375         u32 tmp;
 376
 377         uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1);
 378         uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2);
 379
 380         /* enable DMA */
 381         tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
 382         tmp |= UNIPHIER_SD_EXTMODE_DMA_EN;
 383         uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
 384
 385         uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L);
 386
 387         /* suppress the warning "right shift count >= width of type" */
 388         dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
 389
 390         uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H);
 391
 392         uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL);
 393 }
 394
 395 static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
 396                                         unsigned int blocks)
 397 {
 398         struct uniphier_sd_priv *priv = dev_get_priv(dev);
 399         long wait = 1000000 + 10 * blocks;
 400
 401         while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) {
 402                 if (wait-- < 0) {
 403                         dev_err(dev, "timeout during DMA\n");
 404                         return -ETIMEDOUT;
 405                 }
 406
 407                 udelay(10);
 408         }
 409
 410         if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) {
 411                 dev_err(dev, "error during DMA\n");
 412                 return -EIO;
 413         }
 414
 415         return 0;
 416 }
 417
 418 static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
 419 {
 420         struct uniphier_sd_priv *priv = dev_get_priv(dev);
 421         size_t len = data->blocks * data->blocksize;
 422         void *buf;
 423         enum dma_data_direction dir;
 424         dma_addr_t dma_addr;
 425         u32 poll_flag, tmp;
 426         int ret;
 427
 428         tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
 429
 430         if (data->flags & MMC_DATA_READ) {
 431                 buf = data->dest;
 432                 dir = DMA_FROM_DEVICE;
 433                 poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2;
 434                 tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD;
 435         } else {
 436                 buf = (void *)data->src;
 437                 dir = DMA_TO_DEVICE;
 438                 poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR;
 439                 tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD;
 440         }
 441
 442         uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
 443
 444         dma_addr = __dma_map_single(buf, len, dir);
 445
 446         uniphier_sd_dma_start(priv, dma_addr);
 447
 448         ret = uniphier_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
 449
 450         __dma_unmap_single(dma_addr, len, dir);
 451
 452         return ret;
 453 }
 454
 455 /* check if the address is DMA'able */
 456 static bool uniphier_sd_addr_is_dmaable(unsigned long addr)
 457 {
 458         if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN))
 459                 return false;
 460
 461 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
 462         defined(CONFIG_SPL_BUILD)
 463         /*
 464          * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
 465          * of L2, which is unreachable from the DMA engine.
 466          */
 467         if (addr < CONFIG_SPL_STACK)
 468                 return false;
 469 #endif
 470
 471         return true;
 472 }
 473
 474 static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 475                                 struct mmc_data *data)
 476 {
 477         struct uniphier_sd_priv *priv = dev_get_priv(dev);
 478         int ret;
 479         u32 tmp;
 480
 481         if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
 482                 dev_err(dev, "command busy\n");
 483                 return -EBUSY;
 484         }
 485
 486         /* clear all status flags */
 487         uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1);
 488         uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
 489
 490         /* disable DMA once */
 491         tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
 492         tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN;
 493         uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
 494
 495         uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG);
 496
 497         tmp = cmd->cmdidx;
 498
 499         if (data) {
 500                 uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE);
 501                 uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT);
 502
 503                 /* Do not send CMD12 automatically */
 504                 tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA;
 505
 506                 if (data->blocks > 1)
 507                         tmp |= UNIPHIER_SD_CMD_MULTI;
 508
 509                 if (data->flags & MMC_DATA_READ)
 510                         tmp |= UNIPHIER_SD_CMD_RD;
 511         }
 512
 513         /*
 514          * Do not use the response type auto-detection on this hardware.
 515          * CMD8, for example, has different response types on SD and eMMC,
 516          * while this controller always assumes the response type for SD.
 517          * Set the response type manually.
 518          */
 519         switch (cmd->resp_type) {
 520         case MMC_RSP_NONE:
 521                 tmp |= UNIPHIER_SD_CMD_RSP_NONE;
 522                 break;
 523         case MMC_RSP_R1:
 524                 tmp |= UNIPHIER_SD_CMD_RSP_R1;
 525                 break;
 526         case MMC_RSP_R1b:
 527                 tmp |= UNIPHIER_SD_CMD_RSP_R1B;
 528                 break;
 529         case MMC_RSP_R2:
 530                 tmp |= UNIPHIER_SD_CMD_RSP_R2;
 531                 break;
 532         case MMC_RSP_R3:
 533                 tmp |= UNIPHIER_SD_CMD_RSP_R3;
 534                 break;
 535         default:
 536                 dev_err(dev, "unknown response type\n");
 537                 return -EINVAL;
 538         }
 539
 540         dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
 541                 cmd->cmdidx, tmp, cmd->cmdarg);
 542         uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD);
 543
 544         ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
 545                                        UNIPHIER_SD_INFO1_RSP);
 546         if (ret)
 547                 return ret;
 548
 549         if (cmd->resp_type & MMC_RSP_136) {
 550                 u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76);
 551                 u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54);
 552                 u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32);
 553                 u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
 554
 555                 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
 556                                    ((rsp_103_72  & 0xff000000) >> 24);
 557                 cmd->response[1] = ((rsp_103_72  & 0x00ffffff) << 8) |
 558                                    ((rsp_71_40   & 0xff000000) >> 24);
 559                 cmd->response[2] = ((rsp_71_40   & 0x00ffffff) << 8) |
 560                                    ((rsp_39_8    & 0xff000000) >> 24);
 561                 cmd->response[3] = (rsp_39_8     & 0xffffff)   << 8;
 562         } else {
 563                 /* bit 39-8 */
 564                 cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
 565         }
 566
 567         if (data) {
 568                 /* use DMA if the HW supports it and the buffer is aligned */
 569                 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL &&
 570                     uniphier_sd_addr_is_dmaable((long)data->src))
 571                         ret = uniphier_sd_dma_xfer(dev, data);
 572                 else
 573                         ret = uniphier_sd_pio_xfer(dev, data);
 574
 575                 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
 576                                                UNIPHIER_SD_INFO1_CMP);
 577                 if (ret)
 578                         return ret;
 579         }
 580
 581         return ret;
 582 }
 583
 584 static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv,
 585                                      struct mmc *mmc)
 586 {
 587         u32 val, tmp;
 588
 589         switch (mmc->bus_width) {
 590         case 1:
 591                 val = UNIPHIER_SD_OPTION_WIDTH_1;
 592                 break;
 593         case 4:
 594                 val = UNIPHIER_SD_OPTION_WIDTH_4;
 595                 break;
 596         case 8:
 597                 val = UNIPHIER_SD_OPTION_WIDTH_8;
 598                 break;
 599         default:
 600                 return -EINVAL;
 601         }
 602
 603         tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION);
 604         tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK;
 605         tmp |= val;
 606         uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION);
 607
 608         return 0;
 609 }
 610
 611 static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv,
 612                                      struct mmc *mmc)
 613 {
 614         u32 tmp;
 615
 616         tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE);
 617         if (mmc->ddr_mode)
 618                 tmp |= UNIPHIER_SD_IF_MODE_DDR;
 619         else
 620                 tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
 621         uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE);
 622 }
 623
 624 static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
 625                                      struct mmc *mmc)
 626 {
 627         unsigned int divisor;
 628         u32 val, tmp;
 629
 630         if (!mmc->clock)
 631                 return;
 632
 633         divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
 634
 635         if (divisor <= 1)
 636                 val = UNIPHIER_SD_CLKCTL_DIV1;
 637         else if (divisor <= 2)
 638                 val = UNIPHIER_SD_CLKCTL_DIV2;
 639         else if (divisor <= 4)
 640                 val = UNIPHIER_SD_CLKCTL_DIV4;
 641         else if (divisor <= 8)
 642                 val = UNIPHIER_SD_CLKCTL_DIV8;
 643         else if (divisor <= 16)
 644                 val = UNIPHIER_SD_CLKCTL_DIV16;
 645         else if (divisor <= 32)
 646                 val = UNIPHIER_SD_CLKCTL_DIV32;
 647         else if (divisor <= 64)
 648                 val = UNIPHIER_SD_CLKCTL_DIV64;
 649         else if (divisor <= 128)
 650                 val = UNIPHIER_SD_CLKCTL_DIV128;
 651         else if (divisor <= 256)
 652                 val = UNIPHIER_SD_CLKCTL_DIV256;
 653         else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024))
 654                 val = UNIPHIER_SD_CLKCTL_DIV512;
 655         else
 656                 val = UNIPHIER_SD_CLKCTL_DIV1024;
 657
 658         tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL);
 659         if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN &&
 660             (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val)
 661                 return;
 662
 663         /* stop the clock before changing its rate to avoid a glitch signal */
 664         tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
 665         uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
 666
 667         tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK;
 668         tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN;
 669         uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
 670
 671         tmp |= UNIPHIER_SD_CLKCTL_SCLKEN;
 672         uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
 673
 674         udelay(1000);
 675 }
 676
 677 static int uniphier_sd_set_ios(struct udevice *dev)
 678 {
 679         struct uniphier_sd_priv *priv = dev_get_priv(dev);
 680         struct mmc *mmc = mmc_get_mmc_dev(dev);
 681         int ret;
 682
 683         dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
 684                 mmc->clock, mmc->ddr_mode, mmc->bus_width);
 685
 686         ret = uniphier_sd_set_bus_width(priv, mmc);
 687         if (ret)
 688                 return ret;
 689         uniphier_sd_set_ddr_mode(priv, mmc);
 690         uniphier_sd_set_clk_rate(priv, mmc);
 691
 692         return 0;
 693 }
 694
 695 static int uniphier_sd_get_cd(struct udevice *dev)
 696 {
 697         struct uniphier_sd_priv *priv = dev_get_priv(dev);
 698
 699         if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE)
 700                 return 1;
 701
 702         return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) &
 703                   UNIPHIER_SD_INFO1_CD);
 704 }
 705
 706 static const struct dm_mmc_ops uniphier_sd_ops = {
 707         .send_cmd = uniphier_sd_send_cmd,
 708         .set_ios = uniphier_sd_set_ios,
 709         .get_cd = uniphier_sd_get_cd,
 710 };
 711
 712 static void uniphier_sd_host_init(struct uniphier_sd_priv *priv)
 713 {
 714         u32 tmp;
 715
 716         /* soft reset of the host */
 717         tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST);
 718         tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX;
 719         uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
 720         tmp |= UNIPHIER_SD_SOFT_RST_RSTX;
 721         uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
 722
 723         /* FIXME: implement eMMC hw_reset */
 724
 725         uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP);
 726
 727         /*
 728          * Connected to 32bit AXI.
 729          * This register dropped backward compatibility at version 0x10.
 730          * Write an appropriate value depending on the IP version.
 731          */
 732         uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000,
 733                            UNIPHIER_SD_HOST_MODE);
 734
 735         if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) {
 736                 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
 737                 tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
 738                 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
 739         }
 740 }
 741
 742 static int uniphier_sd_bind(struct udevice *dev)
 743 {
 744         struct uniphier_sd_plat *plat = dev_get_platdata(dev);
 745
 746         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 747 }
 748
 749 static int uniphier_sd_probe(struct udevice *dev)
 750 {
 751         struct uniphier_sd_plat *plat = dev_get_platdata(dev);
 752         struct uniphier_sd_priv *priv = dev_get_priv(dev);
 753         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 754         const u32 quirks = dev_get_driver_data(dev);
 755         fdt_addr_t base;
 756         struct clk clk;
 757         int ret;
 758
 759         base = devfdt_get_addr(dev);
 760         if (base == FDT_ADDR_T_NONE)
 761                 return -EINVAL;
 762
 763         priv->regbase = devm_ioremap(dev, base, SZ_2K);
 764         if (!priv->regbase)
 765                 return -ENOMEM;
 766
 767         ret = clk_get_by_index(dev, 0, &clk);
 768         if (ret < 0) {
 769                 dev_err(dev, "failed to get host clock\n");
 770                 return ret;
 771         }
 772
 773         /* set to max rate */
 774         priv->mclk = clk_set_rate(&clk, ULONG_MAX);
 775         if (IS_ERR_VALUE(priv->mclk)) {
 776                 dev_err(dev, "failed to set rate for host clock\n");
 777                 clk_free(&clk);
 778                 return priv->mclk;
 779         }
 780
 781         ret = clk_enable(&clk);
 782         clk_free(&clk);
 783         if (ret) {
 784                 dev_err(dev, "failed to enable host clock\n");
 785                 return ret;
 786         }
 787
 788         plat->cfg.name = dev->name;
 789         plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
 790
 791         switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
 792                                1)) {
 793         case 8:
 794                 plat->cfg.host_caps |= MMC_MODE_8BIT;
 795                 break;
 796         case 4:
 797                 plat->cfg.host_caps |= MMC_MODE_4BIT;
 798                 break;
 799         case 1:
 800                 break;
 801         default:
 802                 dev_err(dev, "Invalid \"bus-width\" value\n");
 803                 return -EINVAL;
 804         }
 805
 806         if (quirks) {
 807                 priv->caps = quirks;
 808         } else {
 809                 priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) &
 810                                                         UNIPHIER_SD_VERSION_IP;
 811                 dev_dbg(dev, "version %x\n", priv->version);
 812                 if (priv->version >= 0x10) {
 813                         priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL;
 814                         priv->caps |= UNIPHIER_SD_CAP_DIV1024;
 815                 }
 816         }
 817
 818         if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
 819                              NULL))
 820                 priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
 821
 822         uniphier_sd_host_init(priv);
 823
 824         plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
 825         plat->cfg.f_min = priv->mclk /
 826                         (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512);
 827         plat->cfg.f_max = priv->mclk;
 828         plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
 829
 830         upriv->mmc = &plat->mmc;
 831
 832         return 0;
 833 }
 834
 835 static const struct udevice_id uniphier_sd_match[] = {
 836         { .compatible = "renesas,sdhi-r8a7795", .data = UNIPHIER_SD_CAP_64BIT },
 837         { .compatible = "renesas,sdhi-r8a7796", .data = UNIPHIER_SD_CAP_64BIT },
 838         { .compatible = "socionext,uniphier-sdhc", .data = 0 },
 839         { /* sentinel */ }
 840 };
 841
 842 U_BOOT_DRIVER(uniphier_mmc) = {
 843         .name = "uniphier-mmc",
 844         .id = UCLASS_MMC,
 845         .of_match = uniphier_sd_match,
 846         .bind = uniphier_sd_bind,
 847         .probe = uniphier_sd_probe,
 848         .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv),
 849         .platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat),
 850         .ops = &uniphier_sd_ops,
 851 };