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Prepare v2023.04
[thirdparty/u-boot.git] / drivers / mmc / zynq_sdhci.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013 - 2022, Xilinx, Inc.
4 * (C) Copyright 2022, Advanced Micro Devices, Inc.
5 *
6 * Xilinx Zynq SD Host Controller Interface
7 */
8
9 #include <clk.h>
10 #include <common.h>
11 #include <dm.h>
12 #include <fdtdec.h>
13 #include <linux/delay.h>
14 #include "mmc_private.h"
15 #include <log.h>
16 #include <reset.h>
17 #include <dm/device_compat.h>
18 #include <linux/err.h>
19 #include <linux/libfdt.h>
20 #include <linux/iopoll.h>
21 #include <asm/types.h>
22 #include <linux/math64.h>
23 #include <asm/cache.h>
24 #include <malloc.h>
25 #include <sdhci.h>
26 #include <zynqmp_firmware.h>
27
28 #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
29 #define SDHCI_ARASAN_ITAPDLY_SEL_MASK GENMASK(7, 0)
30 #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
31 #define SDHCI_ARASAN_OTAPDLY_SEL_MASK GENMASK(5, 0)
32 #define SDHCI_ITAPDLY_CHGWIN BIT(9)
33 #define SDHCI_ITAPDLY_ENABLE BIT(8)
34 #define SDHCI_OTAPDLY_ENABLE BIT(6)
35
36 #define SDHCI_TUNING_LOOP_COUNT 40
37 #define MMC_BANK2 0x2
38
39 #define SD_DLL_CTRL 0xFF180358
40 #define SD_ITAP_DLY 0xFF180314
41 #define SD_OTAP_DLY 0xFF180318
42 #define SD0_DLL_RST BIT(2)
43 #define SD1_DLL_RST BIT(18)
44 #define SD0_ITAPCHGWIN BIT(9)
45 #define SD1_ITAPCHGWIN BIT(25)
46 #define SD0_ITAPDLYENA BIT(8)
47 #define SD1_ITAPDLYENA BIT(24)
48 #define SD0_ITAPDLYSEL_MASK GENMASK(7, 0)
49 #define SD1_ITAPDLYSEL_MASK GENMASK(23, 16)
50 #define SD0_OTAPDLYSEL_MASK GENMASK(5, 0)
51 #define SD1_OTAPDLYSEL_MASK GENMASK(21, 16)
52
53 #define MIN_PHY_CLK_HZ 50000000
54
55 #define PHY_CTRL_REG1 0x270
56 #define PHY_CTRL_ITAPDLY_ENA_MASK BIT(0)
57 #define PHY_CTRL_ITAPDLY_SEL_MASK GENMASK(5, 1)
58 #define PHY_CTRL_ITAPDLY_SEL_SHIFT 1
59 #define PHY_CTRL_ITAP_CHG_WIN_MASK BIT(6)
60 #define PHY_CTRL_OTAPDLY_ENA_MASK BIT(8)
61 #define PHY_CTRL_OTAPDLY_SEL_MASK GENMASK(15, 12)
62 #define PHY_CTRL_OTAPDLY_SEL_SHIFT 12
63 #define PHY_CTRL_STRB_SEL_MASK GENMASK(23, 16)
64 #define PHY_CTRL_STRB_SEL_SHIFT 16
65 #define PHY_CTRL_TEST_CTRL_MASK GENMASK(31, 24)
66
67 #define PHY_CTRL_REG2 0x274
68 #define PHY_CTRL_EN_DLL_MASK BIT(0)
69 #define PHY_CTRL_DLL_RDY_MASK BIT(1)
70 #define PHY_CTRL_FREQ_SEL_MASK GENMASK(6, 4)
71 #define PHY_CTRL_FREQ_SEL_SHIFT 4
72 #define PHY_CTRL_SEL_DLY_TX_MASK BIT(16)
73 #define PHY_CTRL_SEL_DLY_RX_MASK BIT(17)
74 #define FREQSEL_200M_170M 0x0
75 #define FREQSEL_170M_140M 0x1
76 #define FREQSEL_140M_110M 0x2
77 #define FREQSEL_110M_80M 0x3
78 #define FREQSEL_80M_50M 0x4
79 #define FREQSEL_275M_250M 0x5
80 #define FREQSEL_250M_225M 0x6
81 #define FREQSEL_225M_200M 0x7
82 #define PHY_DLL_TIMEOUT_MS 100
83
84 #define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN 39
85 #define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL 146
86 #define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0X77
87
88 struct arasan_sdhci_clk_data {
89 int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
90 int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
91 };
92
93 struct arasan_sdhci_plat {
94 struct mmc_config cfg;
95 struct mmc mmc;
96 };
97
98 struct arasan_sdhci_priv {
99 struct sdhci_host *host;
100 struct arasan_sdhci_clk_data clk_data;
101 u32 node_id;
102 u8 bank;
103 u8 no_1p8;
104 bool internal_phy_reg;
105 struct reset_ctl_bulk resets;
106 };
107
108 /* For Versal platforms zynqmp_mmio_write() won't be available */
109 __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
110 {
111 return 0;
112 }
113
114 __weak int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
115 u32 arg3, u32 *ret_payload)
116 {
117 return 0;
118 }
119
120 __weak int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
121 {
122 return 1;
123 }
124
125 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET)
126 /* Default settings for ZynqMP Clock Phases */
127 static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
128 0, 183, 54, 0, 0};
129 static const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72,
130 135, 48, 72, 135, 0};
131
132 /* Default settings for Versal Clock Phases */
133 static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132,
134 0, 0, 162, 90, 0, 0};
135 static const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72,
136 90, 36, 60, 90, 0};
137
138 /* Default settings for versal-net eMMC Clock Phases */
139 static const u32 versal_net_emmc_iclk_phases[] = {0, 0, 0, 0, 0, 0, 0, 0, 39,
140 0, 0};
141 static const u32 versal_net_emmc_oclk_phases[] = {0, 113, 0, 0, 0, 0, 0, 0,
142 113, 79, 45};
143
144 static const u8 mode2timing[] = {
145 [MMC_LEGACY] = MMC_TIMING_LEGACY,
146 [MMC_HS] = MMC_TIMING_MMC_HS,
147 [SD_HS] = MMC_TIMING_SD_HS,
148 [MMC_HS_52] = MMC_TIMING_MMC_HS,
149 [MMC_DDR_52] = MMC_TIMING_MMC_DDR52,
150 [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
151 [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
152 [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
153 [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
154 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
155 [MMC_HS_200] = MMC_TIMING_MMC_HS200,
156 [MMC_HS_400] = MMC_TIMING_MMC_HS400,
157 };
158
159 #if defined(CONFIG_ARCH_VERSAL_NET)
160 /**
161 * arasan_phy_set_delaychain - Set eMMC delay chain based Input/Output clock
162 *
163 * @host: Pointer to the sdhci_host structure
164 * @enable: Enable or disable Delay chain based Tx and Rx clock
165 * Return: None
166 *
167 * Enable or disable eMMC delay chain based Input and Output clock in
168 * PHY_CTRL_REG2
169 */
170 static void arasan_phy_set_delaychain(struct sdhci_host *host, bool enable)
171 {
172 u32 reg;
173
174 reg = sdhci_readw(host, PHY_CTRL_REG2);
175 if (enable)
176 reg |= PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK;
177 else
178 reg &= ~(PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK);
179
180 sdhci_writew(host, reg, PHY_CTRL_REG2);
181 }
182
183 /**
184 * arasan_phy_set_dll - Set eMMC DLL clock
185 *
186 * @host: Pointer to the sdhci_host structure
187 * @enable: Enable or disable DLL clock
188 * Return: 0 if success or timeout error
189 *
190 * Enable or disable eMMC DLL clock in PHY_CTRL_REG2. When DLL enable is
191 * set, wait till DLL is locked
192 */
193 static int arasan_phy_set_dll(struct sdhci_host *host, bool enable)
194 {
195 u32 reg;
196
197 reg = sdhci_readw(host, PHY_CTRL_REG2);
198 if (enable)
199 reg |= PHY_CTRL_EN_DLL_MASK;
200 else
201 reg &= ~PHY_CTRL_EN_DLL_MASK;
202
203 sdhci_writew(host, reg, PHY_CTRL_REG2);
204
205 /* If DLL is disabled return success */
206 if (!enable)
207 return 0;
208
209 /* If DLL is enabled wait till DLL loop is locked, which is
210 * indicated by dll_rdy bit(bit1) in PHY_CTRL_REG2
211 */
212 return readl_relaxed_poll_timeout(host->ioaddr + PHY_CTRL_REG2, reg,
213 (reg & PHY_CTRL_DLL_RDY_MASK),
214 1000 * PHY_DLL_TIMEOUT_MS);
215 }
216
217 /**
218 * arasan_phy_dll_set_freq - Select frequency range of DLL for eMMC
219 *
220 * @host: Pointer to the sdhci_host structure
221 * @clock: clock value
222 * Return: None
223 *
224 * Set frequency range bits based on the selected clock for eMMC
225 */
226 static void arasan_phy_dll_set_freq(struct sdhci_host *host, int clock)
227 {
228 u32 reg, freq_sel, freq;
229
230 freq = DIV_ROUND_CLOSEST(clock, 1000000);
231 if (freq <= 200 && freq > 170)
232 freq_sel = FREQSEL_200M_170M;
233 else if (freq <= 170 && freq > 140)
234 freq_sel = FREQSEL_170M_140M;
235 else if (freq <= 140 && freq > 110)
236 freq_sel = FREQSEL_140M_110M;
237 else if (freq <= 110 && freq > 80)
238 freq_sel = FREQSEL_110M_80M;
239 else
240 freq_sel = FREQSEL_80M_50M;
241
242 reg = sdhci_readw(host, PHY_CTRL_REG2);
243 reg &= ~PHY_CTRL_FREQ_SEL_MASK;
244 reg |= (freq_sel << PHY_CTRL_FREQ_SEL_SHIFT);
245 sdhci_writew(host, reg, PHY_CTRL_REG2);
246 }
247
248 static int arasan_sdhci_config_dll(struct sdhci_host *host, unsigned int clock, bool enable)
249 {
250 struct mmc *mmc = (struct mmc *)host->mmc;
251 struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
252
253 if (enable) {
254 if (priv->internal_phy_reg && clock >= MIN_PHY_CLK_HZ && enable)
255 arasan_phy_set_dll(host, 1);
256 return 0;
257 }
258
259 if (priv->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) {
260 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
261 arasan_phy_set_dll(host, 0);
262 arasan_phy_set_delaychain(host, 0);
263 arasan_phy_dll_set_freq(host, clock);
264 return 0;
265 }
266
267 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
268 arasan_phy_set_delaychain(host, 1);
269
270 return 0;
271 }
272 #endif
273
274 static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay)
275 {
276 int ret;
277
278 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
279 if (node_id == NODE_SD_0) {
280 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN,
281 SD0_ITAPCHGWIN);
282 if (ret)
283 return ret;
284
285 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA,
286 SD0_ITAPDLYENA);
287 if (ret)
288 return ret;
289
290 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
291 itap_delay);
292 if (ret)
293 return ret;
294
295 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN, 0);
296 if (ret)
297 return ret;
298 }
299 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN,
300 SD1_ITAPCHGWIN);
301 if (ret)
302 return ret;
303
304 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA,
305 SD1_ITAPDLYENA);
306 if (ret)
307 return ret;
308
309 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
310 (itap_delay << 16));
311 if (ret)
312 return ret;
313
314 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN, 0);
315 if (ret)
316 return ret;
317 } else {
318 return xilinx_pm_request(PM_IOCTL, node_id,
319 IOCTL_SET_SD_TAPDELAY,
320 PM_TAPDELAY_INPUT, itap_delay, NULL);
321 }
322
323 return 0;
324 }
325
326 static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay)
327 {
328 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
329 if (node_id == NODE_SD_0)
330 return zynqmp_mmio_write(SD_OTAP_DLY,
331 SD0_OTAPDLYSEL_MASK,
332 otap_delay);
333
334 return zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
335 (otap_delay << 16));
336 } else {
337 return xilinx_pm_request(PM_IOCTL, node_id,
338 IOCTL_SET_SD_TAPDELAY,
339 PM_TAPDELAY_OUTPUT, otap_delay, NULL);
340 }
341 }
342
343 static inline int zynqmp_dll_reset(u32 node_id, u32 type)
344 {
345 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
346 if (node_id == NODE_SD_0)
347 return zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST,
348 type == PM_DLL_RESET_ASSERT ?
349 SD0_DLL_RST : 0);
350
351 return zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST,
352 type == PM_DLL_RESET_ASSERT ?
353 SD1_DLL_RST : 0);
354 } else {
355 return xilinx_pm_request(PM_IOCTL, node_id,
356 IOCTL_SD_DLL_RESET, type, 0, NULL);
357 }
358 }
359
360 static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 node_id)
361 {
362 struct mmc *mmc = (struct mmc *)host->mmc;
363 struct udevice *dev = mmc->dev;
364 unsigned long timeout;
365 int ret;
366 u16 clk;
367
368 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
369 clk &= ~(SDHCI_CLOCK_CARD_EN);
370 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
371
372 /* Issue DLL Reset */
373 ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
374 if (ret) {
375 dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
376 return ret;
377 }
378
379 /* Allow atleast 1ms delay for proper DLL reset */
380 mdelay(1);
381 ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
382 if (ret) {
383 dev_err(dev, "dll_reset release failed with err: %d\n", ret);
384 return ret;
385 }
386
387 /* Wait max 20 ms */
388 timeout = 100;
389 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
390 & SDHCI_CLOCK_INT_STABLE)) {
391 if (timeout == 0) {
392 dev_err(dev, ": Internal clock never stabilised.\n");
393 return -EBUSY;
394 }
395 timeout--;
396 udelay(1000);
397 }
398
399 clk |= SDHCI_CLOCK_CARD_EN;
400 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
401
402 return 0;
403 }
404
405 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
406 {
407 struct mmc_cmd cmd;
408 struct mmc_data data;
409 u32 ctrl;
410 struct sdhci_host *host;
411 struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
412 int tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
413
414 dev_dbg(mmc->dev, "%s\n", __func__);
415
416 host = priv->host;
417
418 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
419 ctrl |= SDHCI_CTRL_EXEC_TUNING;
420 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
421
422 mdelay(1);
423
424 arasan_zynqmp_dll_reset(host, priv->node_id);
425
426 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
427 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
428
429 do {
430 cmd.cmdidx = opcode;
431 cmd.resp_type = MMC_RSP_R1;
432 cmd.cmdarg = 0;
433
434 data.blocksize = 64;
435 data.blocks = 1;
436 data.flags = MMC_DATA_READ;
437
438 if (tuning_loop_counter-- == 0)
439 break;
440
441 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
442 mmc->bus_width == 8)
443 data.blocksize = 128;
444
445 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
446 data.blocksize),
447 SDHCI_BLOCK_SIZE);
448 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
449 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
450
451 mmc_send_cmd(mmc, &cmd, NULL);
452 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
453
454 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
455 udelay(1);
456
457 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
458
459 if (tuning_loop_counter < 0) {
460 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
461 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
462 }
463
464 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
465 printf("%s:Tuning failed\n", __func__);
466 return -1;
467 }
468
469 udelay(1);
470 arasan_zynqmp_dll_reset(host, priv->node_id);
471
472 /* Enable only interrupts served by the SD controller */
473 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
474 SDHCI_INT_ENABLE);
475 /* Mask all sdhci interrupt sources */
476 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
477
478 return 0;
479 }
480
481 /**
482 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
483 *
484 * @host: Pointer to the sdhci_host structure.
485 * @degrees: The clock phase shift between 0 - 359.
486 * Return: 0
487 *
488 * Set the SD Output Clock Tap Delays for Output path
489 */
490 static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
491 int degrees)
492 {
493 struct mmc *mmc = (struct mmc *)host->mmc;
494 struct udevice *dev = mmc->dev;
495 struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
496 u8 tap_delay, tap_max = 0;
497 int timing = mode2timing[mmc->selected_mode];
498 int ret;
499
500 /*
501 * This is applicable for SDHCI_SPEC_300 and above
502 * ZynqMP does not set phase for <=25MHz clock.
503 * If degrees is zero, no need to do anything.
504 */
505 if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
506 return 0;
507
508 switch (timing) {
509 case MMC_TIMING_MMC_HS:
510 case MMC_TIMING_SD_HS:
511 case MMC_TIMING_UHS_SDR25:
512 case MMC_TIMING_UHS_DDR50:
513 case MMC_TIMING_MMC_DDR52:
514 /* For 50MHz clock, 30 Taps are available */
515 tap_max = 30;
516 break;
517 case MMC_TIMING_UHS_SDR50:
518 /* For 100MHz clock, 15 Taps are available */
519 tap_max = 15;
520 break;
521 case MMC_TIMING_UHS_SDR104:
522 case MMC_TIMING_MMC_HS200:
523 /* For 200MHz clock, 8 Taps are available */
524 tap_max = 8;
525 default:
526 break;
527 }
528
529 tap_delay = (degrees * tap_max) / 360;
530
531 /* Limit output tap_delay value to 6 bits */
532 tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
533
534 /* Set the Clock Phase */
535 ret = arasan_zynqmp_set_out_tapdelay(priv->node_id, tap_delay);
536 if (ret) {
537 dev_err(dev, "Error setting output Tap Delay\n");
538 return ret;
539 }
540
541 /* Release DLL Reset */
542 ret = zynqmp_dll_reset(priv->node_id, PM_DLL_RESET_RELEASE);
543 if (ret) {
544 dev_err(dev, "dll_reset release failed with err: %d\n", ret);
545 return ret;
546 }
547
548 return 0;
549 }
550
551 /**
552 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
553 *
554 * @host: Pointer to the sdhci_host structure.
555 * @degrees: The clock phase shift between 0 - 359.
556 * Return: 0
557 *
558 * Set the SD Input Clock Tap Delays for Input path
559 */
560 static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
561 int degrees)
562 {
563 struct mmc *mmc = (struct mmc *)host->mmc;
564 struct udevice *dev = mmc->dev;
565 struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
566 u8 tap_delay, tap_max = 0;
567 int timing = mode2timing[mmc->selected_mode];
568 int ret;
569
570 /*
571 * This is applicable for SDHCI_SPEC_300 and above
572 * ZynqMP does not set phase for <=25MHz clock.
573 * If degrees is zero, no need to do anything.
574 */
575 if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
576 return 0;
577
578 /* Assert DLL Reset */
579 ret = zynqmp_dll_reset(priv->node_id, PM_DLL_RESET_ASSERT);
580 if (ret) {
581 dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
582 return ret;
583 }
584
585 switch (timing) {
586 case MMC_TIMING_MMC_HS:
587 case MMC_TIMING_SD_HS:
588 case MMC_TIMING_UHS_SDR25:
589 case MMC_TIMING_UHS_DDR50:
590 case MMC_TIMING_MMC_DDR52:
591 /* For 50MHz clock, 120 Taps are available */
592 tap_max = 120;
593 break;
594 case MMC_TIMING_UHS_SDR50:
595 /* For 100MHz clock, 60 Taps are available */
596 tap_max = 60;
597 break;
598 case MMC_TIMING_UHS_SDR104:
599 case MMC_TIMING_MMC_HS200:
600 /* For 200MHz clock, 30 Taps are available */
601 tap_max = 30;
602 default:
603 break;
604 }
605
606 tap_delay = (degrees * tap_max) / 360;
607
608 /* Limit input tap_delay value to 8 bits */
609 tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
610
611 ret = arasan_zynqmp_set_in_tapdelay(priv->node_id, tap_delay);
612 if (ret) {
613 dev_err(dev, "Error setting Input Tap Delay\n");
614 return ret;
615 }
616
617 return 0;
618 }
619
620 /**
621 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
622 *
623 * @host: Pointer to the sdhci_host structure.
624 * @degrees: The clock phase shift between 0 - 359.
625 * Return: 0
626 *
627 * Set the SD Output Clock Tap Delays for Output path
628 */
629 static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
630 int degrees)
631 {
632 struct mmc *mmc = (struct mmc *)host->mmc;
633 u8 tap_delay, tap_max = 0;
634 int timing = mode2timing[mmc->selected_mode];
635 u32 regval;
636
637 /*
638 * This is applicable for SDHCI_SPEC_300 and above
639 * Versal does not set phase for <=25MHz clock.
640 * If degrees is zero, no need to do anything.
641 */
642 if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
643 return 0;
644
645 switch (timing) {
646 case MMC_TIMING_MMC_HS:
647 case MMC_TIMING_SD_HS:
648 case MMC_TIMING_UHS_SDR25:
649 case MMC_TIMING_UHS_DDR50:
650 case MMC_TIMING_MMC_DDR52:
651 /* For 50MHz clock, 30 Taps are available */
652 tap_max = 30;
653 break;
654 case MMC_TIMING_UHS_SDR50:
655 /* For 100MHz clock, 15 Taps are available */
656 tap_max = 15;
657 break;
658 case MMC_TIMING_UHS_SDR104:
659 case MMC_TIMING_MMC_HS200:
660 /* For 200MHz clock, 8 Taps are available */
661 tap_max = 8;
662 default:
663 break;
664 }
665
666 tap_delay = (degrees * tap_max) / 360;
667
668 /* Limit output tap_delay value to 6 bits */
669 tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
670
671 /* Set the Clock Phase */
672 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
673 regval |= SDHCI_OTAPDLY_ENABLE;
674 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
675 regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
676 regval |= tap_delay;
677 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
678
679 return 0;
680 }
681
682 /**
683 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
684 *
685 * @host: Pointer to the sdhci_host structure.
686 * @degrees: The clock phase shift between 0 - 359.
687 * Return: 0
688 *
689 * Set the SD Input Clock Tap Delays for Input path
690 */
691 static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
692 int degrees)
693 {
694 struct mmc *mmc = (struct mmc *)host->mmc;
695 u8 tap_delay, tap_max = 0;
696 int timing = mode2timing[mmc->selected_mode];
697 u32 regval;
698
699 /*
700 * This is applicable for SDHCI_SPEC_300 and above
701 * Versal does not set phase for <=25MHz clock.
702 * If degrees is zero, no need to do anything.
703 */
704 if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
705 return 0;
706
707 switch (timing) {
708 case MMC_TIMING_MMC_HS:
709 case MMC_TIMING_SD_HS:
710 case MMC_TIMING_UHS_SDR25:
711 case MMC_TIMING_UHS_DDR50:
712 case MMC_TIMING_MMC_DDR52:
713 /* For 50MHz clock, 120 Taps are available */
714 tap_max = 120;
715 break;
716 case MMC_TIMING_UHS_SDR50:
717 /* For 100MHz clock, 60 Taps are available */
718 tap_max = 60;
719 break;
720 case MMC_TIMING_UHS_SDR104:
721 case MMC_TIMING_MMC_HS200:
722 /* For 200MHz clock, 30 Taps are available */
723 tap_max = 30;
724 default:
725 break;
726 }
727
728 tap_delay = (degrees * tap_max) / 360;
729
730 /* Limit input tap_delay value to 8 bits */
731 tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
732
733 /* Set the Clock Phase */
734 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
735 regval |= SDHCI_ITAPDLY_CHGWIN;
736 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
737 regval |= SDHCI_ITAPDLY_ENABLE;
738 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
739 regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
740 regval |= tap_delay;
741 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
742 regval &= ~SDHCI_ITAPDLY_CHGWIN;
743 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
744
745 return 0;
746 }
747
748 /**
749 * sdhci_versal_net_emmc_sdcardclk_set_phase - Set eMMC Output Clock Tap Delays
750 *
751 * @host: Pointer to the sdhci_host structure.
752 * @degrees: The clock phase shift between 0 - 359.
753 * Return: 0
754 *
755 * Set eMMC Output Clock Tap Delays for Output path
756 */
757 static int sdhci_versal_net_emmc_sdcardclk_set_phase(struct sdhci_host *host, int degrees)
758 {
759 struct mmc *mmc = (struct mmc *)host->mmc;
760 int timing = mode2timing[mmc->selected_mode];
761 u8 tap_delay, tap_max = 0;
762 u32 regval;
763
764 switch (timing) {
765 case MMC_TIMING_MMC_HS:
766 case MMC_TIMING_MMC_DDR52:
767 tap_max = 16;
768 break;
769 case MMC_TIMING_MMC_HS200:
770 case MMC_TIMING_MMC_HS400:
771 /* For 200MHz clock, 32 Taps are available */
772 tap_max = 32;
773 break;
774 default:
775 break;
776 }
777
778 tap_delay = (degrees * tap_max) / 360;
779 /* Set the Clock Phase */
780 if (tap_delay) {
781 regval = sdhci_readl(host, PHY_CTRL_REG1);
782 regval |= PHY_CTRL_OTAPDLY_ENA_MASK;
783 sdhci_writel(host, regval, PHY_CTRL_REG1);
784 regval &= ~PHY_CTRL_OTAPDLY_SEL_MASK;
785 regval |= tap_delay << PHY_CTRL_OTAPDLY_SEL_SHIFT;
786 sdhci_writel(host, regval, PHY_CTRL_REG1);
787 }
788
789 return 0;
790 }
791
792 /**
793 * sdhci_versal_net_emmc_sampleclk_set_phase - Set eMMC Input Clock Tap Delays
794 *
795 * @host: Pointer to the sdhci_host structure.
796 * @degrees: The clock phase shift between 0 - 359.
797 * Return: 0
798 *
799 * Set eMMC Input Clock Tap Delays for Input path. If HS400 is selected,
800 * set strobe90 and strobe180 in PHY_CTRL_REG1.
801 */
802 static int sdhci_versal_net_emmc_sampleclk_set_phase(struct sdhci_host *host, int degrees)
803 {
804 struct mmc *mmc = (struct mmc *)host->mmc;
805 int timing = mode2timing[mmc->selected_mode];
806 u8 tap_delay, tap_max = 0;
807 u32 regval;
808
809 switch (timing) {
810 case MMC_TIMING_MMC_HS:
811 case MMC_TIMING_MMC_DDR52:
812 tap_max = 32;
813 break;
814 case MMC_TIMING_MMC_HS400:
815 /* Strobe select tap point for strb90 and strb180 */
816 regval = sdhci_readl(host, PHY_CTRL_REG1);
817 regval &= ~PHY_CTRL_STRB_SEL_MASK;
818 regval |= VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL << PHY_CTRL_STRB_SEL_SHIFT;
819 sdhci_writel(host, regval, PHY_CTRL_REG1);
820 break;
821 default:
822 break;
823 }
824
825 tap_delay = (degrees * tap_max) / 360;
826 /* Set the Clock Phase */
827 if (tap_delay) {
828 regval = sdhci_readl(host, PHY_CTRL_REG1);
829 regval |= PHY_CTRL_ITAP_CHG_WIN_MASK;
830 sdhci_writel(host, regval, PHY_CTRL_REG1);
831 regval |= PHY_CTRL_ITAPDLY_ENA_MASK;
832 sdhci_writel(host, regval, PHY_CTRL_REG1);
833 regval &= ~PHY_CTRL_ITAPDLY_SEL_MASK;
834 regval |= tap_delay << PHY_CTRL_ITAPDLY_SEL_SHIFT;
835 sdhci_writel(host, regval, PHY_CTRL_REG1);
836 regval &= ~PHY_CTRL_ITAP_CHG_WIN_MASK;
837 sdhci_writel(host, regval, PHY_CTRL_REG1);
838 }
839
840 return 0;
841 }
842
843 static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
844 {
845 struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
846 struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
847 struct mmc *mmc = (struct mmc *)host->mmc;
848 struct udevice *dev = mmc->dev;
849 u8 timing = mode2timing[mmc->selected_mode];
850 u32 iclk_phase = clk_data->clk_phase_in[timing];
851 u32 oclk_phase = clk_data->clk_phase_out[timing];
852 int ret;
853
854 dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
855
856 if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
857 device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
858 ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
859 if (ret)
860 return ret;
861
862 ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
863 if (ret)
864 return ret;
865 } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
866 device_is_compatible(dev, "xlnx,versal-8.9a")) {
867 ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
868 if (ret)
869 return ret;
870
871 ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
872 if (ret)
873 return ret;
874 } else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
875 device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
876 if (mmc->clock >= MIN_PHY_CLK_HZ)
877 if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN)
878 iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL;
879
880 ret = sdhci_versal_net_emmc_sampleclk_set_phase(host, iclk_phase);
881 if (ret)
882 return ret;
883
884 ret = sdhci_versal_net_emmc_sdcardclk_set_phase(host, oclk_phase);
885 if (ret)
886 return ret;
887 }
888
889 return 0;
890 }
891
892 static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char timing,
893 const char *prop)
894 {
895 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
896 struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
897 u32 clk_phase[2] = {0};
898
899 /*
900 * Read Tap Delay values from DT, if the DT does not contain the
901 * Tap Values then use the pre-defined values
902 */
903 if (dev_read_u32_array(dev, prop, &clk_phase[0], 2)) {
904 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
905 prop, clk_data->clk_phase_in[timing],
906 clk_data->clk_phase_out[timing]);
907 return;
908 }
909
910 /* The values read are Input and Output Clock Delays in order */
911 clk_data->clk_phase_in[timing] = clk_phase[0];
912 clk_data->clk_phase_out[timing] = clk_phase[1];
913 }
914
915 /**
916 * arasan_dt_parse_clk_phases - Read Tap Delay values from DT
917 *
918 * @dev: Pointer to our struct udevice.
919 *
920 * Called at initialization to parse the values of Tap Delays.
921 */
922 static void arasan_dt_parse_clk_phases(struct udevice *dev)
923 {
924 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
925 struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
926 int i;
927
928 if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
929 device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
930 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
931 clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i];
932 clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i];
933 }
934
935 if (priv->bank == MMC_BANK2) {
936 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90;
937 clk_data->clk_phase_out[MMC_TIMING_MMC_HS200] = 90;
938 }
939 }
940
941 if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
942 device_is_compatible(dev, "xlnx,versal-8.9a")) {
943 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
944 clk_data->clk_phase_in[i] = versal_iclk_phases[i];
945 clk_data->clk_phase_out[i] = versal_oclk_phases[i];
946 }
947 }
948
949 if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
950 device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
951 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
952 clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i];
953 clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i];
954 }
955 }
956
957 arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
958 "clk-phase-legacy");
959 arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
960 "clk-phase-mmc-hs");
961 arasan_dt_read_clk_phase(dev, MMC_TIMING_SD_HS,
962 "clk-phase-sd-hs");
963 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR12,
964 "clk-phase-uhs-sdr12");
965 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR25,
966 "clk-phase-uhs-sdr25");
967 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50,
968 "clk-phase-uhs-sdr50");
969 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104,
970 "clk-phase-uhs-sdr104");
971 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50,
972 "clk-phase-uhs-ddr50");
973 arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_DDR52,
974 "clk-phase-mmc-ddr52");
975 arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS200,
976 "clk-phase-mmc-hs200");
977 arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS400,
978 "clk-phase-mmc-hs400");
979 }
980
981 static const struct sdhci_ops arasan_ops = {
982 .platform_execute_tuning = &arasan_sdhci_execute_tuning,
983 .set_delay = &arasan_sdhci_set_tapdelay,
984 .set_control_reg = &sdhci_set_control_reg,
985 #if defined(CONFIG_ARCH_VERSAL_NET)
986 .config_dll = &arasan_sdhci_config_dll,
987 #endif
988 };
989 #endif
990
991 #if defined(CONFIG_ARCH_ZYNQMP)
992 static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv,
993 struct udevice *dev)
994 {
995 int ret;
996 struct clk clk;
997 unsigned long clock, mhz;
998
999 ret = xilinx_pm_request(PM_REQUEST_NODE, priv->node_id,
1000 ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
1001 ZYNQMP_PM_REQUEST_ACK_NO, NULL);
1002 if (ret) {
1003 dev_err(dev, "Request node failed for %d\n", priv->node_id);
1004 return ret;
1005 }
1006
1007 ret = reset_get_bulk(dev, &priv->resets);
1008 if (ret == -ENOTSUPP || ret == -ENOENT) {
1009 dev_err(dev, "Reset not found\n");
1010 return 0;
1011 } else if (ret) {
1012 dev_err(dev, "Reset failed\n");
1013 return ret;
1014 }
1015
1016 ret = reset_assert_bulk(&priv->resets);
1017 if (ret) {
1018 dev_err(dev, "Reset assert failed\n");
1019 return ret;
1020 }
1021
1022 ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_FIXED, 0);
1023 if (ret) {
1024 dev_err(dev, "SD_CONFIG_FIXED failed\n");
1025 return ret;
1026 }
1027
1028 ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_EMMC_SEL,
1029 dev_read_bool(dev, "non-removable"));
1030 if (ret) {
1031 dev_err(dev, "SD_CONFIG_EMMC_SEL failed\n");
1032 return ret;
1033 }
1034
1035 ret = clk_get_by_index(dev, 0, &clk);
1036 if (ret < 0) {
1037 dev_err(dev, "failed to get clock\n");
1038 return ret;
1039 }
1040
1041 clock = clk_get_rate(&clk);
1042 if (IS_ERR_VALUE(clock)) {
1043 dev_err(dev, "failed to get rate\n");
1044 return clock;
1045 }
1046
1047 mhz = DIV64_U64_ROUND_UP(clock, 1000000);
1048
1049 if (mhz > 100 && mhz <= 200)
1050 mhz = 200;
1051 else if (mhz > 50 && mhz <= 100)
1052 mhz = 100;
1053 else if (mhz > 25 && mhz <= 50)
1054 mhz = 50;
1055 else
1056 mhz = 25;
1057
1058 ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_BASECLK, mhz);
1059 if (ret) {
1060 dev_err(dev, "SD_CONFIG_BASECLK failed\n");
1061 return ret;
1062 }
1063
1064 ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_8BIT,
1065 (dev_read_u32_default(dev, "bus-width", 1) == 8));
1066 if (ret) {
1067 dev_err(dev, "SD_CONFIG_8BIT failed\n");
1068 return ret;
1069 }
1070
1071 ret = reset_deassert_bulk(&priv->resets);
1072 if (ret) {
1073 dev_err(dev, "Reset release failed\n");
1074 return ret;
1075 }
1076
1077 return 0;
1078 }
1079 #endif
1080
1081 static int arasan_sdhci_probe(struct udevice *dev)
1082 {
1083 struct arasan_sdhci_plat *plat = dev_get_plat(dev);
1084 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1085 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
1086 struct sdhci_host *host;
1087 struct clk clk;
1088 unsigned long clock;
1089 int ret;
1090
1091 host = priv->host;
1092
1093 #if defined(CONFIG_ARCH_ZYNQMP)
1094 if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
1095 ret = zynqmp_pm_is_function_supported(PM_IOCTL,
1096 IOCTL_SET_SD_CONFIG);
1097 if (!ret) {
1098 ret = sdhci_zynqmp_set_dynamic_config(priv, dev);
1099 if (ret)
1100 return ret;
1101 }
1102 }
1103 #endif
1104 if (device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
1105 priv->internal_phy_reg = true;
1106
1107 ret = clk_get_by_index(dev, 0, &clk);
1108 if (ret < 0) {
1109 dev_err(dev, "failed to get clock\n");
1110 return ret;
1111 }
1112
1113 clock = clk_get_rate(&clk);
1114 if (IS_ERR_VALUE(clock)) {
1115 dev_err(dev, "failed to get rate\n");
1116 return clock;
1117 }
1118
1119 dev_dbg(dev, "%s: CLK %ld\n", __func__, clock);
1120
1121 ret = clk_enable(&clk);
1122 if (ret) {
1123 dev_err(dev, "failed to enable clock\n");
1124 return ret;
1125 }
1126
1127 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
1128 SDHCI_QUIRK_BROKEN_R1B;
1129
1130 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
1131 host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
1132 #endif
1133
1134 if (priv->no_1p8)
1135 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
1136
1137 if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) &&
1138 device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
1139 host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400;
1140
1141 plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
1142
1143 ret = mmc_of_parse(dev, &plat->cfg);
1144 if (ret)
1145 return ret;
1146
1147 host->max_clk = clock;
1148
1149 host->mmc = &plat->mmc;
1150 host->mmc->dev = dev;
1151 host->mmc->priv = host;
1152
1153 ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
1154 CONFIG_ZYNQ_SDHCI_MIN_FREQ);
1155 if (ret)
1156 return ret;
1157 upriv->mmc = host->mmc;
1158
1159 /*
1160 * WORKAROUND: Versal platforms have an issue with card detect state.
1161 * Due to this, host controller is switching off voltage to sd card
1162 * causing sd card timeout error. Workaround this by adding a wait for
1163 * 1000msec till the card detect state gets stable.
1164 */
1165 if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) || IS_ENABLED(CONFIG_ARCH_VERSAL)) {
1166 u32 timeout = 1000000;
1167
1168 while (((sdhci_readl(host, SDHCI_PRESENT_STATE) &
1169 SDHCI_CARD_STATE_STABLE) == 0) && timeout) {
1170 udelay(1);
1171 timeout--;
1172 }
1173 if (!timeout) {
1174 dev_err(dev, "Sdhci card detect state not stable\n");
1175 return -ETIMEDOUT;
1176 }
1177 }
1178
1179 return sdhci_probe(dev);
1180 }
1181
1182 static int arasan_sdhci_of_to_plat(struct udevice *dev)
1183 {
1184 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
1185 u32 pm_info[2];
1186
1187 priv->host = calloc(1, sizeof(struct sdhci_host));
1188 if (!priv->host)
1189 return -1;
1190
1191 priv->host->name = dev->name;
1192
1193 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET)
1194 priv->host->ops = &arasan_ops;
1195 arasan_dt_parse_clk_phases(dev);
1196 #endif
1197
1198 priv->host->ioaddr = (void *)dev_read_addr(dev);
1199 if (IS_ERR(priv->host->ioaddr))
1200 return PTR_ERR(priv->host->ioaddr);
1201
1202 priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
1203 priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
1204
1205 priv->node_id = 0;
1206 if (!dev_read_u32_array(dev, "power-domains", pm_info, ARRAY_SIZE(pm_info)))
1207 priv->node_id = pm_info[1];
1208
1209 return 0;
1210 }
1211
1212 static int arasan_sdhci_bind(struct udevice *dev)
1213 {
1214 struct arasan_sdhci_plat *plat = dev_get_plat(dev);
1215
1216 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
1217 }
1218
1219 static const struct udevice_id arasan_sdhci_ids[] = {
1220 { .compatible = "arasan,sdhci-8.9a" },
1221 { .compatible = "xlnx,versal-net-5.1-emmc" },
1222 { }
1223 };
1224
1225 U_BOOT_DRIVER(arasan_sdhci_drv) = {
1226 .name = "arasan_sdhci",
1227 .id = UCLASS_MMC,
1228 .of_match = arasan_sdhci_ids,
1229 .of_to_plat = arasan_sdhci_of_to_plat,
1230 .ops = &sdhci_ops,
1231 .bind = arasan_sdhci_bind,
1232 .probe = arasan_sdhci_probe,
1233 .priv_auto = sizeof(struct arasan_sdhci_priv),
1234 .plat_auto = sizeof(struct arasan_sdhci_plat),
1235 };
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