3 * Michael Schwingen, <michael@schwingen.org>
5 * based in great part on jedec_probe.c from linux kernel:
6 * (C) 2000 Red Hat. GPL'd.
7 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* The DEBUG define must be before common to enable debugging */
33 #include <asm/processor.h>
35 #include <asm/byteorder.h>
36 #include <environment.h>
38 #define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
41 #define AM29DL800BB 0x22CB
42 #define AM29DL800BT 0x224A
44 #define AM29F800BB 0x2258
45 #define AM29F800BT 0x22D6
46 #define AM29LV400BB 0x22BA
47 #define AM29LV400BT 0x22B9
48 #define AM29LV800BB 0x225B
49 #define AM29LV800BT 0x22DA
50 #define AM29LV160DT 0x22C4
51 #define AM29LV160DB 0x2249
52 #define AM29F017D 0x003D
53 #define AM29F016D 0x00AD
54 #define AM29F080 0x00D5
55 #define AM29F040 0x00A4
56 #define AM29LV040B 0x004F
57 #define AM29F032B 0x0041
58 #define AM29F002T 0x00B0
61 #define SST39LF800 0x2781
62 #define SST39LF160 0x2782
63 #define SST39VF1601 0x234b
64 #define SST39LF512 0x00D4
65 #define SST39LF010 0x00D5
66 #define SST39LF020 0x00D6
67 #define SST39LF040 0x00D7
68 #define SST39SF010A 0x00B5
69 #define SST39SF020A 0x00B6
72 #define MX29LV040 0x004F
75 #define W39L040A 0x00D6
78 #define A29L040 0x0092
81 #define EN29LV040A 0x004F
84 * Unlock address sets for AMD command sets.
85 * Intel command sets use the MTD_UADDR_UNNECESSARY.
86 * Each identifier, except MTD_UADDR_UNNECESSARY, and
87 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
88 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
89 * initialization need not require initializing all of the
90 * unlock addresses for all bit widths.
93 MTD_UADDR_NOT_SUPPORTED
= 0, /* data width not supported */
94 MTD_UADDR_0x0555_0x02AA
,
95 MTD_UADDR_0x0555_0x0AAA
,
96 MTD_UADDR_0x5555_0x2AAA
,
97 MTD_UADDR_0x0AAA_0x0555
,
98 MTD_UADDR_DONT_CARE
, /* Requires an arbitrary address */
99 MTD_UADDR_UNNECESSARY
, /* Does not require any address */
110 * I don't like the fact that the first entry in unlock_addrs[]
111 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
112 * should not be used. The problem is that structures with
113 * initializers have extra fields initialized to 0. It is _very_
114 * desireable to have the unlock address entries for unsupported
115 * data widths automatically initialized - that means that
116 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
119 static const struct unlock_addr unlock_addrs
[] = {
120 [MTD_UADDR_NOT_SUPPORTED
] = {
125 [MTD_UADDR_0x0555_0x02AA
] = {
130 [MTD_UADDR_0x0555_0x0AAA
] = {
135 [MTD_UADDR_0x5555_0x2AAA
] = {
140 [MTD_UADDR_0x0AAA_0x0555
] = {
145 [MTD_UADDR_DONT_CARE
] = {
146 .addr1
= 0x0000, /* Doesn't matter which address */
147 .addr2
= 0x0000 /* is used - must be last entry */
150 [MTD_UADDR_UNNECESSARY
] = {
157 struct amd_flash_info
{
162 const int NumEraseRegions
;
164 const __u8 uaddr
[4]; /* unlock addrs for 8, 16, 32, 64 */
165 const ulong regions
[6];
168 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
170 #define SIZE_64KiB 16
171 #define SIZE_128KiB 17
172 #define SIZE_256KiB 18
173 #define SIZE_512KiB 19
179 static const struct amd_flash_info jedec_table
[] = {
180 #ifdef CONFIG_SYS_FLASH_LEGACY_256Kx8
182 .mfr_id
= (u16
)SST_MANUFACT
,
183 .dev_id
= SST39LF020
,
184 .name
= "SST 39LF020",
186 [0] = MTD_UADDR_0x5555_0x2AAA
/* x8 */
188 .DevSize
= SIZE_256KiB
,
189 .CmdSet
= P_ID_AMD_STD
,
192 ERASEINFO(0x01000,64),
196 #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx8
198 .mfr_id
= (u16
)AMD_MANUFACT
,
199 .dev_id
= AM29LV040B
,
200 .name
= "AMD AM29LV040B",
202 [0] = MTD_UADDR_0x0555_0x02AA
/* x8 */
204 .DevSize
= SIZE_512KiB
,
205 .CmdSet
= P_ID_AMD_STD
,
208 ERASEINFO(0x10000,8),
212 .mfr_id
= (u16
)SST_MANUFACT
,
213 .dev_id
= SST39LF040
,
214 .name
= "SST 39LF040",
216 [0] = MTD_UADDR_0x5555_0x2AAA
/* x8 */
218 .DevSize
= SIZE_512KiB
,
219 .CmdSet
= P_ID_AMD_STD
,
222 ERASEINFO(0x01000,128),
226 .mfr_id
= (u16
)STM_MANUFACT
,
227 .dev_id
= STM_ID_M29W040B
,
228 .name
= "ST Micro M29W040B",
230 [0] = MTD_UADDR_0x0555_0x02AA
/* x8 */
232 .DevSize
= SIZE_512KiB
,
233 .CmdSet
= P_ID_AMD_STD
,
236 ERASEINFO(0x10000,8),
240 .mfr_id
= (u16
)MX_MANUFACT
,
242 .name
= "MXIC MX29LV040",
244 [0] = MTD_UADDR_0x0555_0x02AA
/* x8 */
246 .DevSize
= SIZE_512KiB
,
247 .CmdSet
= P_ID_AMD_STD
,
250 ERASEINFO(0x10000, 8),
254 .mfr_id
= (u16
)WINB_MANUFACT
,
256 .name
= "WINBOND W39L040A",
258 [0] = MTD_UADDR_0x5555_0x2AAA
/* x8 */
260 .DevSize
= SIZE_512KiB
,
261 .CmdSet
= P_ID_AMD_STD
,
264 ERASEINFO(0x10000, 8),
268 .mfr_id
= (u16
)AMIC_MANUFACT
,
270 .name
= "AMIC A29L040",
272 [0] = MTD_UADDR_0x0555_0x02AA
/* x8 */
274 .DevSize
= SIZE_512KiB
,
275 .CmdSet
= P_ID_AMD_STD
,
278 ERASEINFO(0x10000, 8),
282 .mfr_id
= (u16
)EON_MANUFACT
,
283 .dev_id
= EN29LV040A
,
284 .name
= "EON EN29LV040A",
286 [0] = MTD_UADDR_0x0555_0x02AA
/* x8 */
288 .DevSize
= SIZE_512KiB
,
289 .CmdSet
= P_ID_AMD_STD
,
292 ERASEINFO(0x10000, 8),
296 #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16
298 .mfr_id
= (u16
)AMD_MANUFACT
,
299 .dev_id
= AM29LV400BB
,
300 .name
= "AMD AM29LV400BB",
302 [1] = MTD_UADDR_0x0555_0x02AA
/* x16 */
304 .DevSize
= SIZE_512KiB
,
305 .CmdSet
= CFI_CMDSET_AMD_LEGACY
,
308 ERASEINFO(0x04000,1),
309 ERASEINFO(0x02000,2),
310 ERASEINFO(0x08000,1),
311 ERASEINFO(0x10000,7),
315 .mfr_id
= (u16
)AMD_MANUFACT
,
316 .dev_id
= AM29LV800BB
,
317 .name
= "AMD AM29LV800BB",
319 [1] = MTD_UADDR_0x0555_0x02AA
/* x16 */
321 .DevSize
= SIZE_1MiB
,
322 .CmdSet
= CFI_CMDSET_AMD_LEGACY
,
325 ERASEINFO(0x04000, 1),
326 ERASEINFO(0x02000, 2),
327 ERASEINFO(0x08000, 1),
328 ERASEINFO(0x10000, 15),
334 static inline void fill_info(flash_info_t
*info
, const struct amd_flash_info
*jedec_entry
, ulong base
)
340 enum uaddr uaddr_idx
;
342 size_ratio
= info
->portwidth
/ info
->chipwidth
;
344 debug("Found JEDEC Flash: %s\n", jedec_entry
->name
);
345 info
->vendor
= jedec_entry
->CmdSet
;
346 /* Todo: do we need device-specific timeouts? */
347 info
->erase_blk_tout
= 30000;
348 info
->buffer_write_tout
= 1000;
349 info
->write_tout
= 100;
350 info
->name
= jedec_entry
->name
;
352 /* copy unlock addresses from device table to CFI info struct. This
353 is just here because the addresses are in the table anyway - if
354 the flash is not detected due to wrong unlock addresses,
355 flash_detect_legacy would have to try all of them before we even
357 switch(info
->chipwidth
) {
359 uaddr_idx
= jedec_entry
->uaddr
[0];
361 case FLASH_CFI_16BIT
:
362 uaddr_idx
= jedec_entry
->uaddr
[1];
364 case FLASH_CFI_32BIT
:
365 uaddr_idx
= jedec_entry
->uaddr
[2];
368 uaddr_idx
= MTD_UADDR_NOT_SUPPORTED
;
372 debug("unlock address index %d\n", uaddr_idx
);
373 info
->addr_unlock1
= unlock_addrs
[uaddr_idx
].addr1
;
374 info
->addr_unlock2
= unlock_addrs
[uaddr_idx
].addr2
;
375 debug("unlock addresses are 0x%x/0x%x\n", info
->addr_unlock1
, info
->addr_unlock2
);
379 for (i
= 0; i
< jedec_entry
->NumEraseRegions
; i
++) {
380 ulong erase_region_size
= jedec_entry
->regions
[i
] >> 8;
381 ulong erase_region_count
= (jedec_entry
->regions
[i
] & 0xff) + 1;
383 total_size
+= erase_region_size
* erase_region_count
;
384 debug ("erase_region_count = %d erase_region_size = %d\n",
385 erase_region_count
, erase_region_size
);
386 for (j
= 0; j
< erase_region_count
; j
++) {
387 if (sect_cnt
>= CONFIG_SYS_MAX_FLASH_SECT
) {
388 printf("ERROR: too many flash sectors\n");
391 info
->start
[sect_cnt
] = base
;
392 base
+= (erase_region_size
* size_ratio
);
396 info
->sector_count
= sect_cnt
;
397 info
->size
= total_size
* size_ratio
;
400 /*-----------------------------------------------------------------------
401 * match jedec ids against table. If a match is found, fill flash_info entry
403 int jedec_flash_match(flash_info_t
*info
, ulong base
)
408 if (info
->chipwidth
== 1)
411 for (i
= 0; i
< ARRAY_SIZE(jedec_table
); i
++) {
412 if ((jedec_table
[i
].mfr_id
& mask
) == (info
->manufacturer_id
& mask
) &&
413 (jedec_table
[i
].dev_id
& mask
) == (info
->device_id
& mask
)) {
414 fill_info(info
, &jedec_table
[i
], base
);