2 * Arasan NAND Flash Controller Driver
4 * Copyright (C) 2014 - 2015 Xilinx, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/errno.h>
13 #include <linux/mtd/mtd.h>
14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/mtd/nand_ecc.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/sys_proto.h>
21 struct arasan_nand_info
{
22 void __iomem
*nand_base
;
57 #define arasan_nand_base ((struct nand_regs __iomem *)ARASAN_NAND_BASEADDR)
59 struct arasan_nand_command_format
{
66 #define ONDIE_ECC_FEATURE_ADDR 0x90
68 #define ARASAN_PROG_RD_MASK 0x00000001
69 #define ARASAN_PROG_BLK_ERS_MASK 0x00000004
70 #define ARASAN_PROG_RD_ID_MASK 0x00000040
71 #define ARASAN_PROG_RD_STS_MASK 0x00000008
72 #define ARASAN_PROG_PG_PROG_MASK 0x00000010
73 #define ARASAN_PROG_RD_PARAM_PG_MASK 0x00000080
74 #define ARASAN_PROG_RST_MASK 0x00000100
75 #define ARASAN_PROG_GET_FTRS_MASK 0x00000200
76 #define ARASAN_PROG_SET_FTRS_MASK 0x00000400
77 #define ARASAN_PROG_CHNG_ROWADR_END_MASK 0x00400000
79 #define ARASAN_NAND_CMD_ECC_ON_MASK 0x80000000
80 #define ARASAN_NAND_CMD_CMD12_MASK 0xFFFF
81 #define ARASAN_NAND_CMD_PG_SIZE_MASK 0x3800000
82 #define ARASAN_NAND_CMD_PG_SIZE_SHIFT 23
83 #define ARASAN_NAND_CMD_CMD2_SHIFT 8
84 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000
85 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28
87 #define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000
88 #define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF
89 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16
90 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF
91 #define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000
92 #define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000
93 #define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25
95 #define ARASAN_NAND_INT_STS_ERR_EN_MASK 0x10
96 #define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK 0x08
97 #define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK 0x02
98 #define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK 0x01
99 #define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK 0x04
101 #define ARASAN_NAND_PKT_REG_PKT_CNT_MASK 0xFFF000
102 #define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK 0x7FF
103 #define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT 12
105 #define ARASAN_NAND_ROW_ADDR_CYCL_MASK 0x0F
106 #define ARASAN_NAND_COL_ADDR_CYCL_MASK 0xF0
107 #define ARASAN_NAND_COL_ADDR_CYCL_SHIFT 4
109 #define ARASAN_NAND_ECC_SIZE_SHIFT 16
110 #define ARASAN_NAND_ECC_BCH_SHIFT 27
112 #define ARASAN_NAND_PKTSIZE_1K 1024
113 #define ARASAN_NAND_PKTSIZE_512 512
115 #define ARASAN_NAND_POLL_TIMEOUT 1000000
116 #define ARASAN_NAND_INVALID_ADDR_CYCL 0xFF
118 #define ERR_ADDR_CYCLE -1
119 #define READ_BUFF_SIZE 0x4000
121 static struct arasan_nand_command_format
*curr_cmd
;
131 static struct arasan_nand_command_format arasan_nand_commands
[] = {
132 {NAND_CMD_READ0
, NAND_CMD_READSTART
, NAND_ADDR_CYCL_BOTH
,
133 ARASAN_PROG_RD_MASK
},
134 {NAND_CMD_RNDOUT
, NAND_CMD_RNDOUTSTART
, NAND_ADDR_CYCL_COL
,
135 ARASAN_PROG_RD_MASK
},
136 {NAND_CMD_READID
, NAND_CMD_NONE
, NAND_ADDR_CYCL_ONE
,
137 ARASAN_PROG_RD_ID_MASK
},
138 {NAND_CMD_STATUS
, NAND_CMD_NONE
, NAND_ADDR_CYCL_NONE
,
139 ARASAN_PROG_RD_STS_MASK
},
140 {NAND_CMD_SEQIN
, NAND_CMD_PAGEPROG
, NAND_ADDR_CYCL_BOTH
,
141 ARASAN_PROG_PG_PROG_MASK
},
142 {NAND_CMD_RNDIN
, NAND_CMD_NONE
, NAND_ADDR_CYCL_COL
,
143 ARASAN_PROG_CHNG_ROWADR_END_MASK
},
144 {NAND_CMD_ERASE1
, NAND_CMD_ERASE2
, NAND_ADDR_CYCL_ROW
,
145 ARASAN_PROG_BLK_ERS_MASK
},
146 {NAND_CMD_RESET
, NAND_CMD_NONE
, NAND_ADDR_CYCL_NONE
,
147 ARASAN_PROG_RST_MASK
},
148 {NAND_CMD_PARAM
, NAND_CMD_NONE
, NAND_ADDR_CYCL_ONE
,
149 ARASAN_PROG_RD_PARAM_PG_MASK
},
150 {NAND_CMD_GET_FEATURES
, NAND_CMD_NONE
, NAND_ADDR_CYCL_ONE
,
151 ARASAN_PROG_GET_FTRS_MASK
},
152 {NAND_CMD_SET_FEATURES
, NAND_CMD_NONE
, NAND_ADDR_CYCL_ONE
,
153 ARASAN_PROG_SET_FTRS_MASK
},
154 {NAND_CMD_NONE
, NAND_CMD_NONE
, NAND_ADDR_CYCL_NONE
, 0},
157 struct arasan_ecc_matrix
{
159 u32 ecc_codeword_size
;
167 static const struct arasan_ecc_matrix ecc_matrix
[] = {
168 {512, 512, 1, 0, 0, 0x20D, 0x3},
169 {512, 512, 4, 1, 3, 0x209, 0x7},
170 {512, 512, 8, 1, 2, 0x203, 0xD},
174 {2048, 512, 1, 0, 0, 0x834, 0xC},
175 {2048, 512, 4, 1, 3, 0x826, 0x1A},
176 {2048, 512, 8, 1, 2, 0x80c, 0x34},
177 {2048, 512, 12, 1, 1, 0x822, 0x4E},
178 {2048, 512, 16, 1, 0, 0x808, 0x68},
179 {2048, 1024, 24, 1, 4, 0x81c, 0x54},
183 {4096, 512, 1, 0, 0, 0x1068, 0x18},
184 {4096, 512, 4, 1, 3, 0x104c, 0x34},
185 {4096, 512, 8, 1, 2, 0x1018, 0x68},
186 {4096, 512, 12, 1, 1, 0x1044, 0x9C},
187 {4096, 512, 16, 1, 0, 0x1010, 0xD0},
188 {4096, 1024, 24, 1, 4, 0x1038, 0xA8},
192 {8192, 512, 1, 0, 0, 0x20d0, 0x30},
193 {8192, 512, 4, 1, 3, 0x2098, 0x68},
194 {8192, 512, 8, 1, 2, 0x2030, 0xD0},
195 {8192, 512, 12, 1, 1, 0x2088, 0x138},
196 {8192, 512, 16, 1, 0, 0x2020, 0x1A0},
197 {8192, 1024, 24, 1, 4, 0x2070, 0x150},
201 {16384, 512, 1, 0, 0, 0x4460, 0x60},
202 {16384, 512, 4, 1, 3, 0x43f0, 0xD0},
203 {16384, 512, 8, 1, 2, 0x4320, 0x1A0},
204 {16384, 512, 12, 1, 1, 0x4250, 0x270},
205 {16384, 512, 16, 1, 0, 0x4180, 0x340},
206 {16384, 1024, 24, 1, 4, 0x4220, 0x2A0}
209 static u8 buf_data
[READ_BUFF_SIZE
];
210 static u32 buf_index
;
212 static struct nand_ecclayout nand_oob
;
214 static struct nand_chip nand_chip
[CONFIG_SYS_MAX_NAND_DEVICE
];
216 static void arasan_nand_select_chip(struct mtd_info
*mtd
, int chip
)
220 static void arasan_nand_enable_ecc(void)
224 reg_val
= readl(&arasan_nand_base
->cmd_reg
);
225 reg_val
|= ARASAN_NAND_CMD_ECC_ON_MASK
;
227 writel(reg_val
, &arasan_nand_base
->cmd_reg
);
230 static u8
arasan_nand_get_addrcycle(struct mtd_info
*mtd
)
233 struct nand_chip
*chip
= mtd_to_nand(mtd
);
235 switch (curr_cmd
->addr_cycles
) {
236 case NAND_ADDR_CYCL_NONE
:
239 case NAND_ADDR_CYCL_ONE
:
242 case NAND_ADDR_CYCL_ROW
:
243 addrcycles
= chip
->onfi_params
.addr_cycles
&
244 ARASAN_NAND_ROW_ADDR_CYCL_MASK
;
246 case NAND_ADDR_CYCL_COL
:
247 addrcycles
= (chip
->onfi_params
.addr_cycles
&
248 ARASAN_NAND_COL_ADDR_CYCL_MASK
) >>
249 ARASAN_NAND_COL_ADDR_CYCL_SHIFT
;
251 case NAND_ADDR_CYCL_BOTH
:
252 addrcycles
= chip
->onfi_params
.addr_cycles
&
253 ARASAN_NAND_ROW_ADDR_CYCL_MASK
;
254 addrcycles
+= (chip
->onfi_params
.addr_cycles
&
255 ARASAN_NAND_COL_ADDR_CYCL_MASK
) >>
256 ARASAN_NAND_COL_ADDR_CYCL_SHIFT
;
259 addrcycles
= ARASAN_NAND_INVALID_ADDR_CYCL
;
265 static int arasan_nand_read_page(struct mtd_info
*mtd
, u8
*buf
, u32 size
)
267 struct nand_chip
*chip
= mtd_to_nand(mtd
);
268 u32 reg_val
, i
, pktsize
, pktnum
;
269 u32
*bufptr
= (u32
*)buf
;
274 if (chip
->ecc_step_ds
>= ARASAN_NAND_PKTSIZE_1K
)
275 pktsize
= ARASAN_NAND_PKTSIZE_1K
;
277 pktsize
= ARASAN_NAND_PKTSIZE_512
;
280 pktnum
= size
/pktsize
+ 1;
282 pktnum
= size
/pktsize
;
284 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
285 reg_val
|= ARASAN_NAND_INT_STS_ERR_EN_MASK
|
286 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK
;
287 writel(reg_val
, &arasan_nand_base
->intsts_enr
);
289 reg_val
= readl(&arasan_nand_base
->pkt_reg
);
290 reg_val
&= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK
|
291 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK
);
292 reg_val
|= (pktnum
<< ARASAN_NAND_PKT_REG_PKT_CNT_SHFT
) |
294 writel(reg_val
, &arasan_nand_base
->pkt_reg
);
296 arasan_nand_enable_ecc();
297 addr_cycles
= arasan_nand_get_addrcycle(mtd
);
298 if (addr_cycles
== ARASAN_NAND_INVALID_ADDR_CYCL
)
299 return ERR_ADDR_CYCLE
;
301 writel((NAND_CMD_RNDOUTSTART
<< ARASAN_NAND_CMD_CMD2_SHIFT
) |
302 NAND_CMD_RNDOUT
| (addr_cycles
<<
303 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT
),
304 &arasan_nand_base
->ecc_sprcmd_reg
);
305 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
307 while (rdcount
< pktnum
) {
308 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
309 while (!(readl(&arasan_nand_base
->intsts_reg
) &
310 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
) && timeout
) {
315 puts("arasan_read_page: timedout:Buff RDY\n");
321 if (pktnum
== rdcount
) {
322 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
323 reg_val
|= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
;
324 writel(reg_val
, &arasan_nand_base
->intsts_enr
);
326 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
327 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
,
328 &arasan_nand_base
->intsts_enr
);
330 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
331 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
,
332 &arasan_nand_base
->intsts_reg
);
334 for (i
= 0; i
< pktsize
/4; i
++)
335 bufptr
[i
] = readl(&arasan_nand_base
->buf_dataport
);
340 if (rdcount
>= pktnum
)
343 writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
,
344 &arasan_nand_base
->intsts_enr
);
347 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
349 while (!(readl(&arasan_nand_base
->intsts_reg
) &
350 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
355 puts("arasan rd_page timedout:Xfer CMPLT\n");
359 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
360 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
361 &arasan_nand_base
->intsts_enr
);
362 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
363 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
364 &arasan_nand_base
->intsts_reg
);
366 if (readl(&arasan_nand_base
->intsts_reg
) &
367 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK
) {
368 printf("arasan rd_page:sbiterror\n");
372 if (readl(&arasan_nand_base
->intsts_reg
) &
373 ARASAN_NAND_INT_STS_ERR_EN_MASK
) {
374 mtd
->ecc_stats
.failed
++;
375 printf("arasan rd_page:multibiterror\n");
382 static int arasan_nand_read_page_hwecc(struct mtd_info
*mtd
,
383 struct nand_chip
*chip
, u8
*buf
, int oob_required
, int page
)
387 status
= arasan_nand_read_page(mtd
, buf
, (mtd
->writesize
));
390 chip
->ecc
.read_oob(mtd
, chip
, page
);
395 static void arasan_nand_fill_tx(const u8
*buf
, int len
)
397 u32 __iomem
*nand
= &arasan_nand_base
->buf_dataport
;
399 if (((unsigned long)buf
& 0x3) != 0) {
400 if (((unsigned long)buf
& 0x1) != 0) {
408 if (((unsigned long)buf
& 0x3) != 0) {
410 writew(*(u16
*)buf
, nand
);
418 writel(*(u32
*)buf
, nand
);
425 writew(*(u16
*)buf
, nand
);
435 static int arasan_nand_write_page_hwecc(struct mtd_info
*mtd
,
436 struct nand_chip
*chip
, const u8
*buf
, int oob_required
,
439 u32 reg_val
, i
, pktsize
, pktnum
;
440 const u32
*bufptr
= (const u32
*)buf
;
441 u32 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
442 u32 size
= mtd
->writesize
;
444 u8 column_addr_cycles
;
445 struct arasan_nand_info
*nand
= nand_get_controller_data(chip
);
447 if (chip
->ecc_step_ds
>= ARASAN_NAND_PKTSIZE_1K
)
448 pktsize
= ARASAN_NAND_PKTSIZE_1K
;
450 pktsize
= ARASAN_NAND_PKTSIZE_512
;
453 pktnum
= size
/pktsize
+ 1;
455 pktnum
= size
/pktsize
;
457 reg_val
= readl(&arasan_nand_base
->pkt_reg
);
458 reg_val
&= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK
|
459 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK
);
460 reg_val
|= (pktnum
<< ARASAN_NAND_PKT_REG_PKT_CNT_SHFT
) | pktsize
;
461 writel(reg_val
, &arasan_nand_base
->pkt_reg
);
463 arasan_nand_enable_ecc();
464 column_addr_cycles
= (chip
->onfi_params
.addr_cycles
&
465 ARASAN_NAND_COL_ADDR_CYCL_MASK
) >>
466 ARASAN_NAND_COL_ADDR_CYCL_SHIFT
;
467 writel((NAND_CMD_RNDIN
| (column_addr_cycles
<< 28)),
468 &arasan_nand_base
->ecc_sprcmd_reg
);
469 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
471 while (rdcount
< pktnum
) {
472 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
473 while (!(readl(&arasan_nand_base
->intsts_reg
) &
474 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
) && timeout
) {
480 puts("arasan_write_page: timedout:Buff RDY\n");
486 if (pktnum
== rdcount
) {
487 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
488 reg_val
|= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
;
489 writel(reg_val
, &arasan_nand_base
->intsts_enr
);
491 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
492 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
,
493 &arasan_nand_base
->intsts_enr
);
496 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
497 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
,
498 &arasan_nand_base
->intsts_reg
);
500 for (i
= 0; i
< pktsize
/4; i
++)
501 writel(bufptr
[i
], &arasan_nand_base
->buf_dataport
);
505 if (rdcount
>= pktnum
)
508 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
,
509 &arasan_nand_base
->intsts_enr
);
512 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
514 while (!(readl(&arasan_nand_base
->intsts_reg
) &
515 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
520 puts("arasan write_page timedout:Xfer CMPLT\n");
524 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
525 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
526 &arasan_nand_base
->intsts_enr
);
527 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
528 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
529 &arasan_nand_base
->intsts_reg
);
532 chip
->ecc
.write_oob(mtd
, chip
, nand
->page
);
537 static int arasan_nand_read_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
540 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
541 chip
->read_buf(mtd
, chip
->oob_poi
, (mtd
->oobsize
));
546 static int arasan_nand_write_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
550 const u8
*buf
= chip
->oob_poi
;
552 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
553 chip
->write_buf(mtd
, buf
, mtd
->oobsize
);
558 static int arasan_nand_reset(struct arasan_nand_command_format
*curr_cmd
)
560 u32 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
563 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
564 &arasan_nand_base
->intsts_enr
);
565 cmd_reg
= readl(&arasan_nand_base
->cmd_reg
);
566 cmd_reg
&= ~ARASAN_NAND_CMD_CMD12_MASK
;
568 cmd_reg
|= curr_cmd
->cmd1
|
569 (curr_cmd
->cmd2
<< ARASAN_NAND_CMD_CMD2_SHIFT
);
570 writel(cmd_reg
, &arasan_nand_base
->cmd_reg
);
571 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
573 while (!(readl(&arasan_nand_base
->intsts_reg
) &
574 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
579 printf("ERROR:%s timedout\n", __func__
);
583 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
584 &arasan_nand_base
->intsts_enr
);
586 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
587 &arasan_nand_base
->intsts_reg
);
592 static u8
arasan_nand_page(struct mtd_info
*mtd
)
596 switch (mtd
->writesize
) {
616 printf("%s:Pagesize>16K\n", __func__
);
623 static int arasan_nand_send_wrcmd(struct arasan_nand_command_format
*curr_cmd
,
624 int column
, int page_addr
, struct mtd_info
*mtd
)
627 u8 page_val
, addr_cycles
;
629 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
,
630 &arasan_nand_base
->intsts_enr
);
631 reg_val
= readl(&arasan_nand_base
->cmd_reg
);
632 reg_val
&= ~ARASAN_NAND_CMD_CMD12_MASK
;
633 reg_val
|= curr_cmd
->cmd1
|
634 (curr_cmd
->cmd2
<< ARASAN_NAND_CMD_CMD2_SHIFT
);
635 if (curr_cmd
->cmd1
== NAND_CMD_SEQIN
) {
636 reg_val
&= ~ARASAN_NAND_CMD_PG_SIZE_MASK
;
637 page_val
= arasan_nand_page(mtd
);
638 reg_val
|= (page_val
<< ARASAN_NAND_CMD_PG_SIZE_SHIFT
);
641 reg_val
&= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK
;
642 addr_cycles
= arasan_nand_get_addrcycle(mtd
);
644 if (addr_cycles
== ARASAN_NAND_INVALID_ADDR_CYCL
)
645 return ERR_ADDR_CYCLE
;
647 reg_val
|= (addr_cycles
<<
648 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT
);
649 writel(reg_val
, &arasan_nand_base
->cmd_reg
);
654 page
= (page_addr
<< ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT
) &
655 ARASAN_NAND_MEM_ADDR1_PAGE_MASK
;
656 column
&= ARASAN_NAND_MEM_ADDR1_COL_MASK
;
657 writel(page
|column
, &arasan_nand_base
->memadr_reg1
);
659 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
660 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK
;
661 reg_val
|= (page_addr
>> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT
);
662 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
663 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
664 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_CS_MASK
;
665 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
670 static void arasan_nand_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
673 u32 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
675 reg_val
= readl(&arasan_nand_base
->pkt_reg
);
676 reg_val
&= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK
|
677 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK
);
679 reg_val
|= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT
) | len
;
680 writel(reg_val
, &arasan_nand_base
->pkt_reg
);
681 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
683 while (!(readl(&arasan_nand_base
->intsts_reg
) &
684 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
) && timeout
) {
690 puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n");
692 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
693 reg_val
|= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
;
694 writel(reg_val
, &arasan_nand_base
->intsts_enr
);
695 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
,
696 &arasan_nand_base
->intsts_enr
);
697 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
698 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
,
699 &arasan_nand_base
->intsts_reg
);
701 arasan_nand_fill_tx(buf
, len
);
703 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
704 while (!(readl(&arasan_nand_base
->intsts_reg
) &
705 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
710 puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n");
712 writel(readl(&arasan_nand_base
->intsts_enr
) |
713 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
714 &arasan_nand_base
->intsts_enr
);
715 writel(readl(&arasan_nand_base
->intsts_reg
) |
716 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
717 &arasan_nand_base
->intsts_reg
);
720 static int arasan_nand_erase(struct arasan_nand_command_format
*curr_cmd
,
721 int column
, int page_addr
, struct mtd_info
*mtd
)
724 u32 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
727 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
728 &arasan_nand_base
->intsts_enr
);
729 reg_val
= readl(&arasan_nand_base
->cmd_reg
);
730 reg_val
&= ~ARASAN_NAND_CMD_CMD12_MASK
;
731 reg_val
|= curr_cmd
->cmd1
|
732 (curr_cmd
->cmd2
<< ARASAN_NAND_CMD_CMD2_SHIFT
);
733 row_addr_cycles
= arasan_nand_get_addrcycle(mtd
);
735 if (row_addr_cycles
== ARASAN_NAND_INVALID_ADDR_CYCL
)
736 return ERR_ADDR_CYCLE
;
738 reg_val
&= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK
;
739 reg_val
|= (row_addr_cycles
<<
740 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT
);
742 writel(reg_val
, &arasan_nand_base
->cmd_reg
);
744 page
= (page_addr
<< ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT
) &
745 ARASAN_NAND_MEM_ADDR1_PAGE_MASK
;
746 column
= page_addr
& ARASAN_NAND_MEM_ADDR1_COL_MASK
;
747 writel(page
| column
, &arasan_nand_base
->memadr_reg1
);
749 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
750 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK
;
751 reg_val
|= (page_addr
>> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT
);
752 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
753 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
754 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_CS_MASK
;
755 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
756 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
758 while (!(readl(&arasan_nand_base
->intsts_reg
) &
759 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
764 printf("ERROR:%s timedout:Xfer CMPLT\n", __func__
);
768 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
769 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
770 &arasan_nand_base
->intsts_enr
);
771 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
772 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
773 &arasan_nand_base
->intsts_reg
);
778 static int arasan_nand_read_status(struct arasan_nand_command_format
*curr_cmd
,
779 int column
, int page_addr
, struct mtd_info
*mtd
)
782 u32 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
785 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
786 &arasan_nand_base
->intsts_enr
);
787 reg_val
= readl(&arasan_nand_base
->cmd_reg
);
788 reg_val
&= ~ARASAN_NAND_CMD_CMD12_MASK
;
789 reg_val
|= curr_cmd
->cmd1
|
790 (curr_cmd
->cmd2
<< ARASAN_NAND_CMD_CMD2_SHIFT
);
791 addr_cycles
= arasan_nand_get_addrcycle(mtd
);
793 if (addr_cycles
== ARASAN_NAND_INVALID_ADDR_CYCL
)
794 return ERR_ADDR_CYCLE
;
796 reg_val
&= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK
;
797 reg_val
|= (addr_cycles
<<
798 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT
);
800 writel(reg_val
, &arasan_nand_base
->cmd_reg
);
802 reg_val
= readl(&arasan_nand_base
->pkt_reg
);
803 reg_val
&= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK
|
804 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK
);
805 reg_val
|= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT
) | 1;
806 writel(reg_val
, &arasan_nand_base
->pkt_reg
);
808 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
809 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_CS_MASK
;
810 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
812 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
813 while (!(readl(&arasan_nand_base
->intsts_reg
) &
814 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
820 printf("ERROR:%s: timedout:Xfer CMPLT\n", __func__
);
824 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
825 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
826 &arasan_nand_base
->intsts_enr
);
827 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
828 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
829 &arasan_nand_base
->intsts_reg
);
834 static int arasan_nand_send_rdcmd(struct arasan_nand_command_format
*curr_cmd
,
835 int column
, int page_addr
, struct mtd_info
*mtd
)
837 u32 reg_val
, addr_cycles
, page
;
840 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
841 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
,
842 &arasan_nand_base
->intsts_enr
);
844 reg_val
= readl(&arasan_nand_base
->cmd_reg
);
845 reg_val
&= ~ARASAN_NAND_CMD_CMD12_MASK
;
846 reg_val
|= curr_cmd
->cmd1
|
847 (curr_cmd
->cmd2
<< ARASAN_NAND_CMD_CMD2_SHIFT
);
849 if (curr_cmd
->cmd1
== NAND_CMD_RNDOUT
||
850 curr_cmd
->cmd1
== NAND_CMD_READ0
) {
851 reg_val
&= ~ARASAN_NAND_CMD_PG_SIZE_MASK
;
852 page_val
= arasan_nand_page(mtd
);
853 reg_val
|= (page_val
<< ARASAN_NAND_CMD_PG_SIZE_SHIFT
);
856 reg_val
&= ~ARASAN_NAND_CMD_ECC_ON_MASK
;
858 reg_val
&= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK
;
860 addr_cycles
= arasan_nand_get_addrcycle(mtd
);
862 if (addr_cycles
== ARASAN_NAND_INVALID_ADDR_CYCL
)
863 return ERR_ADDR_CYCLE
;
865 reg_val
|= (addr_cycles
<< 28);
866 writel(reg_val
, &arasan_nand_base
->cmd_reg
);
871 page
= (page_addr
<< ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT
) &
872 ARASAN_NAND_MEM_ADDR1_PAGE_MASK
;
873 column
&= ARASAN_NAND_MEM_ADDR1_COL_MASK
;
874 writel(page
| column
, &arasan_nand_base
->memadr_reg1
);
876 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
877 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK
;
878 reg_val
|= (page_addr
>> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT
);
879 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
881 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
882 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_CS_MASK
;
883 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
889 static void arasan_nand_read_buf(struct mtd_info
*mtd
, u8
*buf
, int size
)
892 u32
*bufptr
= (u32
*)buf
;
893 u32 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
895 reg_val
= readl(&arasan_nand_base
->pkt_reg
);
896 reg_val
&= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK
|
897 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK
);
898 reg_val
|= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT
) | size
;
899 writel(reg_val
, &arasan_nand_base
->pkt_reg
);
901 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
903 while (!(readl(&arasan_nand_base
->intsts_reg
) &
904 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
) && timeout
) {
910 puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n");
912 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
913 reg_val
|= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
;
914 writel(reg_val
, &arasan_nand_base
->intsts_enr
);
916 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
,
917 &arasan_nand_base
->intsts_enr
);
918 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
919 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
,
920 &arasan_nand_base
->intsts_reg
);
923 for (i
= 0; i
< size
/ 4; i
++)
924 bufptr
[i
] = readl(&arasan_nand_base
->buf_dataport
);
927 bufptr
[i
] = readl(&arasan_nand_base
->buf_dataport
);
929 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
931 while (!(readl(&arasan_nand_base
->intsts_reg
) &
932 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
938 puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n");
940 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
941 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
942 &arasan_nand_base
->intsts_enr
);
943 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
944 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
945 &arasan_nand_base
->intsts_reg
);
948 static u8
arasan_nand_read_byte(struct mtd_info
*mtd
)
950 struct nand_chip
*chip
= mtd_to_nand(mtd
);
953 struct nand_onfi_params
*p
;
955 if (buf_index
== 0) {
956 p
= &chip
->onfi_params
;
957 if (curr_cmd
->cmd1
== NAND_CMD_READID
)
959 else if (curr_cmd
->cmd1
== NAND_CMD_PARAM
)
960 size
= sizeof(struct nand_onfi_params
);
961 else if (curr_cmd
->cmd1
== NAND_CMD_RNDOUT
)
962 size
= le16_to_cpu(p
->ext_param_page_length
) * 16;
963 else if (curr_cmd
->cmd1
== NAND_CMD_GET_FEATURES
)
965 else if (curr_cmd
->cmd1
== NAND_CMD_STATUS
)
966 return readb(&arasan_nand_base
->flash_sts_reg
);
969 chip
->read_buf(mtd
, &buf_data
[0], size
);
972 val
= *(&buf_data
[0] + buf_index
);
978 static void arasan_nand_cmd_function(struct mtd_info
*mtd
, unsigned int command
,
979 int column
, int page_addr
)
982 struct nand_chip
*chip
= mtd_to_nand(mtd
);
983 struct arasan_nand_info
*nand
= nand_get_controller_data(chip
);
986 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
987 &arasan_nand_base
->intsts_enr
);
989 if ((command
== NAND_CMD_READOOB
) &&
990 (mtd
->writesize
> 512)) {
991 column
+= mtd
->writesize
;
992 command
= NAND_CMD_READ0
;
995 /* Get the command format */
996 for (i
= 0; (arasan_nand_commands
[i
].cmd1
!= NAND_CMD_NONE
||
997 arasan_nand_commands
[i
].cmd2
!= NAND_CMD_NONE
); i
++) {
998 if (command
== arasan_nand_commands
[i
].cmd1
) {
999 curr_cmd
= &arasan_nand_commands
[i
];
1004 if (curr_cmd
== NULL
) {
1005 printf("Unsupported Command; 0x%x\n", command
);
1009 if (curr_cmd
->cmd1
== NAND_CMD_RESET
)
1010 ret
= arasan_nand_reset(curr_cmd
);
1012 if ((curr_cmd
->cmd1
== NAND_CMD_READID
) ||
1013 (curr_cmd
->cmd1
== NAND_CMD_PARAM
) ||
1014 (curr_cmd
->cmd1
== NAND_CMD_RNDOUT
) ||
1015 (curr_cmd
->cmd1
== NAND_CMD_GET_FEATURES
) ||
1016 (curr_cmd
->cmd1
== NAND_CMD_READ0
))
1017 ret
= arasan_nand_send_rdcmd(curr_cmd
, column
, page_addr
, mtd
);
1019 if ((curr_cmd
->cmd1
== NAND_CMD_SET_FEATURES
) ||
1020 (curr_cmd
->cmd1
== NAND_CMD_SEQIN
)) {
1021 nand
->page
= page_addr
;
1022 ret
= arasan_nand_send_wrcmd(curr_cmd
, column
, page_addr
, mtd
);
1025 if (curr_cmd
->cmd1
== NAND_CMD_ERASE1
)
1026 ret
= arasan_nand_erase(curr_cmd
, column
, page_addr
, mtd
);
1028 if (curr_cmd
->cmd1
== NAND_CMD_STATUS
)
1029 ret
= arasan_nand_read_status(curr_cmd
, column
, page_addr
, mtd
);
1032 printf("ERROR:%s:command:0x%x\n", __func__
, curr_cmd
->cmd1
);
1035 static int arasan_nand_ecc_init(struct mtd_info
*mtd
)
1038 u32 regval
, eccpos_start
, i
;
1039 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
1041 nand_chip
->ecc
.mode
= NAND_ECC_HW
;
1042 nand_chip
->ecc
.hwctl
= NULL
;
1043 nand_chip
->ecc
.read_page
= arasan_nand_read_page_hwecc
;
1044 nand_chip
->ecc
.write_page
= arasan_nand_write_page_hwecc
;
1045 nand_chip
->ecc
.read_oob
= arasan_nand_read_oob
;
1046 nand_chip
->ecc
.write_oob
= arasan_nand_write_oob
;
1048 for (i
= 0; i
< ARRAY_SIZE(ecc_matrix
); i
++) {
1049 if ((ecc_matrix
[i
].pagesize
== mtd
->writesize
) &&
1050 (ecc_matrix
[i
].ecc_codeword_size
>=
1051 nand_chip
->ecc_step_ds
)) {
1052 if (ecc_matrix
[i
].eccbits
>=
1053 nand_chip
->ecc_strength_ds
) {
1064 regval
= ecc_matrix
[found
].eccaddr
|
1065 (ecc_matrix
[found
].eccsize
<< ARASAN_NAND_ECC_SIZE_SHIFT
) |
1066 (ecc_matrix
[found
].bch
<< ARASAN_NAND_ECC_BCH_SHIFT
);
1067 writel(regval
, &arasan_nand_base
->ecc_reg
);
1069 if (ecc_matrix
[found
].bch
) {
1070 regval
= readl(&arasan_nand_base
->memadr_reg2
);
1071 regval
&= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK
;
1072 regval
|= (ecc_matrix
[found
].bchval
<<
1073 ARASAN_NAND_MEM_ADDR2_BCH_SHIFT
);
1074 writel(regval
, &arasan_nand_base
->memadr_reg2
);
1077 nand_oob
.eccbytes
= ecc_matrix
[found
].eccsize
;
1078 eccpos_start
= mtd
->oobsize
- nand_oob
.eccbytes
;
1080 for (i
= 0; i
< nand_oob
.eccbytes
; i
++)
1081 nand_oob
.eccpos
[i
] = eccpos_start
+ i
;
1083 nand_oob
.oobfree
[0].offset
= 2;
1084 nand_oob
.oobfree
[0].length
= eccpos_start
- 2;
1086 nand_chip
->ecc
.size
= ecc_matrix
[found
].ecc_codeword_size
;
1087 nand_chip
->ecc
.strength
= ecc_matrix
[found
].eccbits
;
1088 nand_chip
->ecc
.bytes
= ecc_matrix
[found
].eccsize
;
1089 nand_chip
->ecc
.layout
= &nand_oob
;
1094 static int arasan_nand_init(struct nand_chip
*nand_chip
, int devnum
)
1096 struct arasan_nand_info
*nand
;
1097 struct mtd_info
*mtd
;
1100 nand
= calloc(1, sizeof(struct arasan_nand_info
));
1102 printf("%s: failed to allocate\n", __func__
);
1106 nand
->nand_base
= arasan_nand_base
;
1107 mtd
= nand_to_mtd(nand_chip
);
1108 nand_set_controller_data(nand_chip
, nand
);
1110 /* Set the driver entry points for MTD */
1111 nand_chip
->cmdfunc
= arasan_nand_cmd_function
;
1112 nand_chip
->select_chip
= arasan_nand_select_chip
;
1113 nand_chip
->read_byte
= arasan_nand_read_byte
;
1115 /* Buffer read/write routines */
1116 nand_chip
->read_buf
= arasan_nand_read_buf
;
1117 nand_chip
->write_buf
= arasan_nand_write_buf
;
1118 nand_chip
->bbt_options
= NAND_BBT_USE_FLASH
;
1120 writel(0x0, &arasan_nand_base
->cmd_reg
);
1121 writel(0x0, &arasan_nand_base
->pgm_reg
);
1123 /* first scan to find the device and get the page size */
1124 if (nand_scan_ident(mtd
, 1, NULL
)) {
1125 printf("%s: nand_scan_ident failed\n", __func__
);
1129 if (arasan_nand_ecc_init(mtd
)) {
1130 printf("%s: nand_ecc_init failed\n", __func__
);
1134 if (nand_scan_tail(mtd
)) {
1135 printf("%s: nand_scan_tail failed\n", __func__
);
1139 if (nand_register(devnum
, mtd
)) {
1140 printf("Nand Register Fail\n");
1150 void board_nand_init(void)
1152 struct nand_chip
*nand
= &nand_chip
[0];
1154 if (arasan_nand_init(nand
, 0))
1155 puts("NAND init failed\n");