drivers/mtd/nand/davinci_nand.c

   1 /*
   2  * NAND driver for TI DaVinci based boards.
   3  *
   4  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   5  *
   6  * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
   7  */
   8
   9 /*
  10  *
  11  * linux/drivers/mtd/nand/nand_davinci.c
  12  *
  13  * NAND Flash Driver
  14  *
  15  * Copyright (C) 2006 Texas Instruments.
  16  *
  17  * ----------------------------------------------------------------------------
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  *  You should have received a copy of the GNU General Public License
  30  *  along with this program; if not, write to the Free Software
  31  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  32  * ----------------------------------------------------------------------------
  33  *
  34  *  Overview:
  35  *   This is a device driver for the NAND flash device found on the
  36  *   DaVinci board which utilizes the Samsung k9k2g08 part.
  37  *
  38  Modifications:
  39  ver. 1.0: Feb 2005, Vinod/Sudhakar
  40  -
  41  *
  42  */
  43
  44 #include <common.h>
  45 #include <asm/io.h>
  46 #include <nand.h>
  47 #include <asm/arch/nand_defs.h>
  48 #include <asm/arch/emif_defs.h>
  49
  50 /* Definitions for 4-bit hardware ECC */
  51 #define NAND_TIMEOUT                    10240
  52 #define NAND_ECC_BUSY                   0xC
  53 #define NAND_4BITECC_MASK               0x03FF03FF
  54 #define EMIF_NANDFSR_ECC_STATE_MASK     0x00000F00
  55 #define ECC_STATE_NO_ERR                0x0
  56 #define ECC_STATE_TOO_MANY_ERRS         0x1
  57 #define ECC_STATE_ERR_CORR_COMP_P       0x2
  58 #define ECC_STATE_ERR_CORR_COMP_N       0x3
  59
  60 static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
  61
  62 /*
  63  * Exploit the little endianness of the ARM to do multi-byte transfers
  64  * per device read. This can perform over twice as quickly as individual
  65  * byte transfers when buffer alignment is conducive.
  66  *
  67  * NOTE: This only works if the NAND is not connected to the 2 LSBs of
  68  * the address bus. On Davinci EVM platforms this has always been true.
  69  */
  70 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  71 {
  72         struct nand_chip *chip = mtd->priv;
  73         const u32 *nand = chip->IO_ADDR_R;
  74
  75         /* Make sure that buf is 32 bit aligned */
  76         if (((int)buf & 0x3) != 0) {
  77                 if (((int)buf & 0x1) != 0) {
  78                         if (len) {
  79                                 *buf = readb(nand);
  80                                 buf += 1;
  81                                 len--;
  82                         }
  83                 }
  84
  85                 if (((int)buf & 0x3) != 0) {
  86                         if (len >= 2) {
  87                                 *(u16 *)buf = readw(nand);
  88                                 buf += 2;
  89                                 len -= 2;
  90                         }
  91                 }
  92         }
  93
  94         /* copy aligned data */
  95         while (len >= 4) {
  96                 *(u32 *)buf = readl(nand);
  97                 buf += 4;
  98                 len -= 4;
  99         }
 100
 101         /* mop up any remaining bytes */
 102         if (len) {
 103                 if (len >= 2) {
 104                         *(u16 *)buf = readw(nand);
 105                         buf += 2;
 106                         len -= 2;
 107                 }
 108
 109                 if (len)
 110                         *buf = readb(nand);
 111         }
 112 }
 113
 114 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 115                                    int len)
 116 {
 117         struct nand_chip *chip = mtd->priv;
 118         const u32 *nand = chip->IO_ADDR_W;
 119
 120         /* Make sure that buf is 32 bit aligned */
 121         if (((int)buf & 0x3) != 0) {
 122                 if (((int)buf & 0x1) != 0) {
 123                         if (len) {
 124                                 writeb(*buf, nand);
 125                                 buf += 1;
 126                                 len--;
 127                         }
 128                 }
 129
 130                 if (((int)buf & 0x3) != 0) {
 131                         if (len >= 2) {
 132                                 writew(*(u16 *)buf, nand);
 133                                 buf += 2;
 134                                 len -= 2;
 135                         }
 136                 }
 137         }
 138
 139         /* copy aligned data */
 140         while (len >= 4) {
 141                 writel(*(u32 *)buf, nand);
 142                 buf += 4;
 143                 len -= 4;
 144         }
 145
 146         /* mop up any remaining bytes */
 147         if (len) {
 148                 if (len >= 2) {
 149                         writew(*(u16 *)buf, nand);
 150                         buf += 2;
 151                         len -= 2;
 152                 }
 153
 154                 if (len)
 155                         writeb(*buf, nand);
 156         }
 157 }
 158
 159 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 160 {
 161         struct          nand_chip *this = mtd->priv;
 162         u_int32_t       IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
 163
 164         if (ctrl & NAND_CTRL_CHANGE) {
 165                 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
 166
 167                 if ( ctrl & NAND_CLE )
 168                         IO_ADDR_W |= MASK_CLE;
 169                 if ( ctrl & NAND_ALE )
 170                         IO_ADDR_W |= MASK_ALE;
 171                 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
 172         }
 173
 174         if (cmd != NAND_CMD_NONE)
 175                 writeb(cmd, IO_ADDR_W);
 176 }
 177
 178 #ifdef CONFIG_SYS_NAND_HW_ECC
 179
 180 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
 181 {
 182         u_int32_t       val;
 183
 184         (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2]));
 185
 186         val = readl(&emif_regs->NANDFCR);
 187         val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
 188         val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
 189         writel(val, &emif_regs->NANDFCR);
 190 }
 191
 192 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
 193 {
 194         u_int32_t       ecc = 0;
 195
 196         ecc = readl(&(emif_regs->NANDFECC[region - 1]));
 197
 198         return(ecc);
 199 }
 200
 201 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 202 {
 203         u_int32_t               tmp;
 204         const int region = 1;
 205
 206         tmp = nand_davinci_readecc(mtd, region);
 207
 208         /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
 209          * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
 210         tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
 211
 212         /* Invert so that erased block ECC is correct */
 213         tmp = ~tmp;
 214
 215         *ecc_code++ = tmp;
 216         *ecc_code++ = tmp >>  8;
 217         *ecc_code++ = tmp >> 16;
 218
 219         /* NOTE:  the above code matches mainline Linux:
 220          *      .PQR.stu ==> ~PQRstu
 221          *
 222          * MontaVista/TI kernels encode those bytes differently, use
 223          * complicated (and allegedly sometimes-wrong) correction code,
 224          * and usually shipped with U-Boot that uses software ECC:
 225          *      .PQR.stu ==> PsQRtu
 226          *
 227          * If you need MV/TI compatible NAND I/O in U-Boot, it should
 228          * be possible to (a) change the mangling above, (b) reverse
 229          * that mangling in nand_davinci_correct_data() below.
 230          */
 231
 232         return 0;
 233 }
 234
 235 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
 236 {
 237         struct nand_chip *this = mtd->priv;
 238         u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
 239                                           (read_ecc[2] << 16);
 240         u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
 241                                           (calc_ecc[2] << 16);
 242         u_int32_t diff = ecc_calc ^ ecc_nand;
 243
 244         if (diff) {
 245                 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
 246                         /* Correctable error */
 247                         if ((diff >> (12 + 3)) < this->ecc.size) {
 248                                 uint8_t find_bit = 1 << ((diff >> 12) & 7);
 249                                 uint32_t find_byte = diff >> (12 + 3);
 250
 251                                 dat[find_byte] ^= find_bit;
 252                                 MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
 253                                          "bit ECC error at offset: %d, bit: "
 254                                          "%d\n", find_byte, find_bit);
 255                                 return 1;
 256                         } else {
 257                                 return -1;
 258                         }
 259                 } else if (!(diff & (diff - 1))) {
 260                         /* Single bit ECC error in the ECC itself,
 261                            nothing to fix */
 262                         MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
 263                                  "ECC.\n");
 264                         return 1;
 265                 } else {
 266                         /* Uncorrectable error */
 267                         MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
 268                         return -1;
 269                 }
 270         }
 271         return(0);
 272 }
 273 #endif /* CONFIG_SYS_NAND_HW_ECC */
 274
 275 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 276 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
 277 #if defined(CONFIG_SYS_NAND_PAGE_2K)
 278         .eccbytes = 40,
 279         .eccpos = {
 280                 24, 25, 26, 27, 28,
 281                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
 282                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
 283                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
 284                 59, 60, 61, 62, 63,
 285                 },
 286         .oobfree = {
 287                 {.offset = 2, .length = 22, },
 288         },
 289 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
 290         .eccbytes = 80,
 291         .eccpos = {
 292                 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
 293                 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
 294                 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
 295                 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
 296                 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
 297                 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
 298                 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
 299                 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
 300                 },
 301         .oobfree = {
 302                 {.offset = 2, .length = 46, },
 303         },
 304 #endif
 305 };
 306
 307 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
 308 {
 309         u32 val;
 310
 311         switch (mode) {
 312         case NAND_ECC_WRITE:
 313         case NAND_ECC_READ:
 314                 /*
 315                  * Start a new ECC calculation for reading or writing 512 bytes
 316                  * of data.
 317                  */
 318                 val = readl(&emif_regs->NANDFCR);
 319                 val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
 320                 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
 321                 val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
 322                 val |= DAVINCI_NANDFCR_4BIT_ECC_START;
 323                 writel(val, &emif_regs->NANDFCR);
 324                 break;
 325         case NAND_ECC_READSYN:
 326                 val = emif_regs->NAND4BITECC1;
 327                 break;
 328         default:
 329                 break;
 330         }
 331 }
 332
 333 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
 334 {
 335         ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK;
 336         ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK;
 337         ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK;
 338         ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK;
 339
 340         return 0;
 341 }
 342
 343 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
 344                                            const uint8_t *dat,
 345                                            uint8_t *ecc_code)
 346 {
 347         unsigned int hw_4ecc[4];
 348         unsigned int i;
 349
 350         nand_davinci_4bit_readecc(mtd, hw_4ecc);
 351
 352         /*Convert 10 bit ecc value to 8 bit */
 353         for (i = 0; i < 2; i++) {
 354                 unsigned int hw_ecc_low = hw_4ecc[i * 2];
 355                 unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
 356
 357                 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
 358                 *ecc_code++ = hw_ecc_low & 0xFF;
 359
 360                 /*
 361                  * Take 2 bits as LSB bits from val1 (count1=0) or val5
 362                  * (count1=1) and 6 bits from val2 (count1=0) or
 363                  * val5 (count1=1)
 364                  */
 365                 *ecc_code++ =
 366                     ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
 367
 368                 /*
 369                  * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
 370                  * 4 bits from val3 (count1=0) or val6 (count1=1)
 371                  */
 372                 *ecc_code++ =
 373                     ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
 374
 375                 /*
 376                  * Take 6 bits from val3(count1=0) or val6 (count1=1) and
 377                  * 2 bits from val4 (count1=0) or  val7 (count1=1)
 378                  */
 379                 *ecc_code++ =
 380                     ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
 381
 382                 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
 383                 *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
 384         }
 385
 386         return 0;
 387 }
 388
 389 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
 390                                           uint8_t *read_ecc, uint8_t *calc_ecc)
 391 {
 392         int i;
 393         unsigned int hw_4ecc[4];
 394         unsigned int iserror;
 395         unsigned short *ecc16;
 396         unsigned int numerrors, erroraddress, errorvalue;
 397         u32 val;
 398
 399         /*
 400          * Check for an ECC where all bytes are 0xFF.  If this is the case, we
 401          * will assume we are looking at an erased page and we should ignore
 402          * the ECC.
 403          */
 404         for (i = 0; i < 10; i++) {
 405                 if (read_ecc[i] != 0xFF)
 406                         break;
 407         }
 408         if (i == 10)
 409                 return 0;
 410
 411         /* Convert 8 bit in to 10 bit */
 412         ecc16 = (unsigned short *)&read_ecc[0];
 413
 414         /*
 415          * Write the parity values in the NAND Flash 4-bit ECC Load register.
 416          * Write each parity value one at a time starting from 4bit_ecc_val8
 417          * to 4bit_ecc_val1.
 418          */
 419
 420         /*Take 2 bits from 8th byte and 8 bits from 9th byte */
 421         writel(((ecc16[4]) >> 6) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
 422
 423         /* Take 4 bits from 7th byte and 6 bits from 8th byte */
 424         writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
 425                &emif_regs->NAND4BITECCLOAD);
 426
 427         /* Take 6 bits from 6th byte and 4 bits from 7th byte */
 428         writel((ecc16[3] >> 2) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
 429
 430         /* Take 8 bits from 5th byte and 2 bits from 6th byte */
 431         writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
 432                &emif_regs->NAND4BITECCLOAD);
 433
 434         /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
 435         writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
 436                &emif_regs->NAND4BITECCLOAD);
 437
 438         /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
 439         writel(((ecc16[1]) >> 4) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
 440
 441         /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
 442         writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
 443                &emif_regs->NAND4BITECCLOAD);
 444
 445         /* Take 10 bits from 0th and 1st bytes */
 446         writel((ecc16[0]) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
 447
 448         /*
 449          * Perform a dummy read to the EMIF Revision Code and Status register.
 450          * This is required to ensure time for syndrome calculation after
 451          * writing the ECC values in previous step.
 452          */
 453
 454         val = emif_regs->NANDFSR;
 455
 456         /*
 457          * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
 458          * A syndrome value of 0 means no bit errors. If the syndrome is
 459          * non-zero then go further otherwise return.
 460          */
 461         nand_davinci_4bit_readecc(mtd, hw_4ecc);
 462
 463         if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
 464                 return 0;
 465
 466         /*
 467          * Clear any previous address calculation by doing a dummy read of an
 468          * error address register.
 469          */
 470         val = emif_regs->NANDERRADD1;
 471
 472         /*
 473          * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
 474          * register to 1.
 475          */
 476         emif_regs->NANDFCR |= 1 << 13;
 477
 478         /*
 479          * Wait for the corr_state field (bits 8 to 11)in the
 480          * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
 481          */
 482         i = NAND_TIMEOUT;
 483         do {
 484                 val = emif_regs->NANDFSR;
 485                 val &= 0xc00;
 486                 i--;
 487         } while ((i > 0) && val);
 488
 489         iserror = emif_regs->NANDFSR;
 490         iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
 491         iserror = iserror >> 8;
 492
 493         /*
 494          * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
 495          * corrected (five or more errors).  The number of errors
 496          * calculated (err_num field) differs from the number of errors
 497          * searched.  ECC_STATE_ERR_CORR_COMP_P (0x2) means error
 498          * correction complete (errors on bit 8 or 9).
 499          * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
 500          * complete (error exists).
 501          */
 502
 503         if (iserror == ECC_STATE_NO_ERR) {
 504                 val = emif_regs->NANDERRVAL1;
 505                 return 0;
 506         } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
 507                 val = emif_regs->NANDERRVAL1;
 508                 return -1;
 509         }
 510
 511         numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1;
 512
 513         /* Read the error address, error value and correct */
 514         for (i = 0; i < numerrors; i++) {
 515                 if (i > 1) {
 516                         erroraddress =
 517                             ((emif_regs->NANDERRADD2 >>
 518                               (16 * (i & 1))) & 0x3FF);
 519                         erroraddress = ((512 + 7) - erroraddress);
 520                         errorvalue =
 521                             ((emif_regs->NANDERRVAL2 >>
 522                               (16 * (i & 1))) & 0xFF);
 523                 } else {
 524                         erroraddress =
 525                             ((emif_regs->NANDERRADD1 >>
 526                               (16 * (i & 1))) & 0x3FF);
 527                         erroraddress = ((512 + 7) - erroraddress);
 528                         errorvalue =
 529                             ((emif_regs->NANDERRVAL1 >>
 530                               (16 * (i & 1))) & 0xFF);
 531                 }
 532                 /* xor the corrupt data with error value */
 533                 if (erroraddress < 512)
 534                         dat[erroraddress] ^= errorvalue;
 535         }
 536
 537         return numerrors;
 538 }
 539 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
 540
 541 static int nand_davinci_dev_ready(struct mtd_info *mtd)
 542 {
 543         return emif_regs->NANDFSR & 0x1;
 544 }
 545
 546 static void nand_flash_init(void)
 547 {
 548         /* This is for DM6446 EVM and *very* similar.  DO NOT GROW THIS!
 549          * Instead, have your board_init() set EMIF timings, based on its
 550          * knowledge of the clocks and what devices are hooked up ... and
 551          * don't even do that unless no UBL handled it.
 552          */
 553 #ifdef CONFIG_SOC_DM644X
 554         u_int32_t       acfg1 = 0x3ffffffc;
 555
 556         /*------------------------------------------------------------------*
 557          *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
 558          *                                                                  *
 559          *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
 560          *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
 561          *                                                                  *
 562          *------------------------------------------------------------------*/
 563          acfg1 = 0
 564                 | (0 << 31 )    /* selectStrobe */
 565                 | (0 << 30 )    /* extWait */
 566                 | (1 << 26 )    /* writeSetup   10 ns */
 567                 | (3 << 20 )    /* writeStrobe  40 ns */
 568                 | (1 << 17 )    /* writeHold    10 ns */
 569                 | (1 << 13 )    /* readSetup    10 ns */
 570                 | (5 << 7 )     /* readStrobe   60 ns */
 571                 | (1 << 4 )     /* readHold     10 ns */
 572                 | (3 << 2 )     /* turnAround   ?? ns */
 573                 | (0 << 0 )     /* asyncSize    8-bit bus */
 574                 ;
 575
 576         emif_regs->AB1CR = acfg1; /* CS2 */
 577
 578         emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */
 579 #endif
 580 }
 581
 582 void davinci_nand_init(struct nand_chip *nand)
 583 {
 584         nand->chip_delay  = 0;
 585 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
 586         nand->options     |= NAND_USE_FLASH_BBT;
 587 #endif
 588 #ifdef CONFIG_SYS_NAND_HW_ECC
 589         nand->ecc.mode = NAND_ECC_HW;
 590         nand->ecc.size = 512;
 591         nand->ecc.bytes = 3;
 592         nand->ecc.calculate = nand_davinci_calculate_ecc;
 593         nand->ecc.correct  = nand_davinci_correct_data;
 594         nand->ecc.hwctl  = nand_davinci_enable_hwecc;
 595 #else
 596         nand->ecc.mode = NAND_ECC_SOFT;
 597 #endif /* CONFIG_SYS_NAND_HW_ECC */
 598 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 599         nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
 600         nand->ecc.size = 512;
 601         nand->ecc.bytes = 10;
 602         nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
 603         nand->ecc.correct = nand_davinci_4bit_correct_data;
 604         nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
 605         nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
 606 #endif
 607         /* Set address of hardware control function */
 608         nand->cmd_ctrl = nand_davinci_hwcontrol;
 609
 610         nand->read_buf = nand_davinci_read_buf;
 611         nand->write_buf = nand_davinci_write_buf;
 612
 613         nand->dev_ready = nand_davinci_dev_ready;
 614
 615         nand_flash_init();
 616 }
 617
 618 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
 619
 620 int board_nand_init(struct nand_chip *chip)
 621 {
 622         davinci_nand_init(chip);
 623         return 0;
 624 }